Physical Design PPA Engineer
Beaverton, Oregon, United States
Hardware
Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. We are looking for a motivated Senior ASIC Physical Design PPA (Performance, Power, Area) Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role, and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today!
Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before envisioned. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.
Description
Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. As Physical Design PPA Enginner, you will be responsible for generating automation and infrastructure to scale and improve the efficiency and reliability of the PPA regression and problems. You will do a deep dive to root cause and address any unexpected result. You will be working with CAD and design teams to drive these improvements and updates in our production design flows in an effective and timely manner. You will collaborate cross functionally with design, power, post silicon, and CAD to deliver on PPA goals.
Minimum Qualifications
- BS and a minimum of 3 years of relevant industry experience
Key Qualifications
Preferred Qualifications
- We are looking for applicants with experience and strong understanding of the RTL2GDSII flow and concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
- Ideal candidate will have hands-on experience in PPA ( Performance, Power, Area) analysis for different Physical designs and evaluate new Stdcell libraries in leading tech nodes.
- Familiar with development of block/partitions for silicon validation of foundation IPs.
- Good understanding of Place-and-Route design as well as associated tools/flow, ability to analyze physical databases and drive new ideas.
- Experience with industry standard synthesis, physical design and STA tools.
- Familiar with ASIC integration flows, including power distribution, global signal planning, I/O planning and hard IP integration is highly desired.
- Familiar with tapeout of partitions and Verification Flows like LEQ, IR/EM, Timing and DFM closure is preferred.
- Hands-on experience with ECO implementation, both functional and timing closure is helpful.
- Familiar with DFT insertion, and multi-mode timing constraints is a strong plus.
- Strong scripting skills using Perl/Tcl.
- Strong written/verbal communication skills.
Education & Experience
Additional Requirements
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.