Summary
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Device-Parameter Estimation through IDDQ Signatures Michihiro SHINTANI Takashi SATO Publication IEICE TRANSACTIONS on Information and Systems Vol.E96-D No.2 pp.303-313 Publication Date: 2013/02/01 Online ISSN: 1745-1361 DOI: 10.1587/transinf.E96.D.303 Print ISSN: 0916-8532 Type of Manuscript: PAPER Category: Dependable Computing Keyword: IDDQ testing, statistical leakage current analysis, Bayes' theorem, Full Text: PDF(1.3MB)>>
Summary: We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations. | ||||||||||
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