Alex Bedarida

Data processing system has a data processing core (C) or CPU for processing data (Dx). Data is written to or read from a memory (S) by a read or write access to the memory and such an access process combines access requests of a first data processing unit with those of a second data processing unit (L).

Two or more operating systems to share a same physical memory while operating simultaneously within a hybrid computer system, without requiring modifications to the program code of the operating systems or application programs. One embodiment of the present invention contains circuitry that is located between the operating systems and the physical memory within the hybrid computer system. In operation, these circuits receive a memory request for one of the operating systems together with the… Mehr anzeigen

Two or more operating systems to share a same physical memory while operating simultaneously within a hybrid computer system, without requiring modifications to the program code of the operating systems or application programs. One embodiment of the present invention contains circuitry that is located between the operating systems and the physical memory within the hybrid computer system. In operation, these circuits receive a memory request for one of the operating systems together with the specific memory address requested and a signal indicating which operating system originated the memory access request. The circuit determines which operating system the memory access request is performed on behalf of. If the memory request is performed on behalf of predetermined first operating system, the received memory address is translated and sent to the physical memory of the computer system. This translation of the physical address is transparent to the first operating system. If a memory access request is detected for the second operating system, the present invention does not perform any address translation and the original memory address is forwarded to the physical memory. The present invention is able to detect memory access requests that are for a particular operating system by: 1) accesses that originate from the CPU where the operating system is running; and 2) accesses that originate from a peripheral or other external device but are performed on behalf of the particular operating system. Weniger anzeigen

A computer system includes a microprocessor running in big-endian mode and both big-endian and little-endian peripherals, including a little-endian SCSI controller that controls a hard disk. When a program calls for a data transfer between the hard disk and random-access memory, the operating system determines a peripheral-accessible memory address range for the data transfer. A bridge driver intercepts this range and determines whether or not the data needs to be swizzled to take into account… Mehr anzeigen

A computer system includes a microprocessor running in big-endian mode and both big-endian and little-endian peripherals, including a little-endian SCSI controller that controls a hard disk. When a program calls for a data transfer between the hard disk and random-access memory, the operating system determines a peripheral-accessible memory address range for the data transfer. A bridge driver intercepts this range and determines whether or not the data needs to be swizzled to take into account differing endianness. The determination is encoded into the most significant bit of a processor-assertable address range, and the bits of lesser significance indicate the peripheral-accessible address range. The processor-assertable address range is conveyed to the SCSI controller originating the data transfer. A communications bridge extracts the processor-assertable address from the origination information from the SCSI controller. The bridge maps the processor-assertable address range to a product space of peripheral-accessible addresses and a command set. The mapping indicates the peripheral-accessible address range intended by the operating system and an indication that swizzling need to be performed. In addition, the second most significant bit of the processor-assertable address is used to indicate that cache snooping is required for the transfer. The invention efficiently allows peripherals designed for one endian environment to work in a different endian environment. Weniger anzeigen

A method and apparatus for determining whether an address corresponds to a cacheable memory location within a discontiguously-arranged cacheable memory space. In one embodiment, the present invention includes the following steps: First the present invention receives an address for a memory location. Next, the present invention masks a first portion of the received address with an "admask" and compares the result of the admask itself to determine whether they are a predetermined value. The… Mehr anzeigen

A method and apparatus for determining whether an address corresponds to a cacheable memory location within a discontiguously-arranged cacheable memory space. In one embodiment, the present invention includes the following steps: First the present invention receives an address for a memory location. Next, the present invention masks a first portion of the received address with an "admask" and compares the result of the admask itself to determine whether they are a predetermined value. The present invention also masks a second portion of the received address with a "tagmask" and compares the result to the tagmask itself to determine whether they are a predetermined value. Next, the present invention generates a cacheable signal provided the first portion of the received address matches the admask and the second portion of the received address matches the tagmask. In so doing, the present invention provides a method and apparatus for caching discontiguous memory address spaces with shorter cache tags. Weniger anzeigen