The interplay between hardware and software is a critical part of designing next-gen chips for fast-growing industries such as #AI and #HPC. Join CHIPS Alliance, OpenPOWER Foundation and RISC-V International at this co-located #OSSummitEurope event for industry insight on the current #opensource landscape with Antmicro, ChipFlow, Infineon Technologies, MIPS and Technische Universität Wien: https://lnkd.in/dF7djPC7 The Linux Foundation Linux Foundation Europe Rob Mains James Kulina Calista Redmond Andrea Gallo Lori Servin Christoph Sandner Rob Taylor Itai Yarom Daniel Mueller-Gritschneder Johannes Geier
CHIPS Alliance
Semiconductor Manufacturing
A collaborative organization that lowers the cost of RTL hardware development - building open source SoC and related IP
About us
An open source organization focused on lowering the cost of RTL hardware development. By collaboratively sharing development resources, the organization will create open source CPUs, SoC and complex IP that all members can utilize.
- Website
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http://www.chipsalliance.org
External link for CHIPS Alliance
- Industry
- Semiconductor Manufacturing
- Company size
- 11-50 employees
- Type
- Nonprofit
Employees at CHIPS Alliance
Updates
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CHIPS Alliance reposted this
Proudly sponsoring #ORConf by FOSSi Foundation in Gothenburg this year, continously pushing the boundaries of #opensource digital design and industry collaboration. Meet our team this weekend and join the debate with talks on CHIPS Alliance #Caliptra 2.0 and architectural exploration + SoC development in #Renode https://lnkd.in/d7FqvbMk Olof Kindgren Stefan Wallentowitz Julius Baxter
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CHIPS Alliance reposted this
Working towards #Caliptra 2.0, we added User mode support to the RISC-V International #VeeR EL2 core. Read about the implementation, PMP support & the testing infrastructure with #Verilator, RISCV-DV, #Tock and #Renode: https://lnkd.in/diCjtFGC CHIPS Alliance Google AMD Microsoft NVIDIA
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CHIPS Alliance reposted this
Our #Caliptra talk at #ORConf in Gothenburg will go into recent developments in IP, tools and verification flows, incl. a new open source I3C core, additions to the #RISCV VeeR core, SystemRDL integration with #Renode simulation & more: https://lnkd.in/d7FqvbMk FOSSi Foundation Olof Kindgren Stefan Wallentowitz CHIPS Alliance Rob Mains The Linux Foundation AMD Google NVIDIA Microsoft
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CHIPS Alliance reposted this
Learn how we used SMT solvers and #SystemVerilog to SMT-LIB2 conversion to implement constrained randomization in #Verilator on the road to fully #opensource #ASIC verification with #UVM: https://lnkd.in/dsXaGFP8 CHIPS Alliance Google Western Digital RISC-V International TRISTAN
Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion
antmicro.com
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Our member Antmicro helped improve The OpenROAD Project flow by speeding up the #opensource toolchain's performance for fast turnaround design feedback. Learn about the results & workflow implemented to optimize execution times of complex #ASIC designs: https://lnkd.in/d5vEb_i2 Google
Speeding Up OpenROAD For Fast Design Feedback
chipsalliance.org
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CHIPS Alliance reposted this
During our #LatchUpConf talk we discussed recent developments in #opensource RTL verification with #Verilator, including constrained randomization, #UVM support, coroutines and integration with #Astsee: https://lnkd.in/dF2izrai FOSSi Foundation CHIPS Alliance Google Western Digital
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I am pleased to announce the 1.0 release of the Caliptra Root of Trust macro, which is a collaborative project between CHIPS Alliance and the Open Compute Project comprised of the founding partners AMD, Google, Microsoft, and Nvidia. Details are here: https://lnkd.in/gxXSHayw
Caliptra
chipsalliance.github.io
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CHIPS Alliance reposted this
Join us at #ossummit tomorrow for Open Hardware & Software Mini Summit. We're taking a look at the complexities of the hardware space and discuss the possibilities of #opensource collaboration between software and hardware engineers in #ASIC design: https://sched.co/1aBJ0 CHIPS Alliance OpenPOWER Foundation RISC-V International The Linux Foundation #Renode
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Antmicro added Physical Memory Protection to the VeeR EL2 @risc_v core for the #Caliptra RoT project Learn about PMP principles and implementation details and the testing process with #pyUVM: https://lnkd.in/gXiQ6zSE AMD Google Microsoft NVIDIA
Adding Physical Memory Protection to the VeeR EL2 RISC-V Core
chipsalliance.org