Hot Interconnects

As the final day of IEEE Hot Interconnects 2024 concludes, we've reached a significant milestone - welcoming 1,200+ registrants and hosting 987 attendees. The Organizing Committee is deeply grateful to all participants for placing your trust in our ability to deliver a high-quality conference. Together, we’ve made this event a success. 🙌 A sincere thank you to our sponsors - Eliyan Corporation, Arista Networks, Salience Labs, GigaIO, Nutanix, Lenovo, and our media partner HPCwire - your support has been essential. 💼 Keynote speakers Mark Baciak (NeuralFabric Corp.), Tony Chan Carusone (Alphawave Semi), and Pavan Balaji (Meta) provided valuable insights that enriched this year’s event. 🎙️ We also had the honor of hosting invited talks from Andy Bechtolsheim (Arista Networks), Sreejit Chakravarty (Ampere), and Uri Elzur (Intel Corporation), each of whom brought unique perspectives to the conference. 🗣️ The panel on “Bandwidth Scaling for AI Interconnect - More Wavelengths vs More Fiber?” offered deep, thought-provoking discussions, thanks to the industry experts Dr. Dan Kuchta (IBM Research), Dr. Peter Winzer (Nubis Communications), Dr. Rebecca Schaevitz (Mixx Technologies Inc.), Dr. Amit Nagra (Intel Corporation), Dr. Alan Liu (Quintessent Inc.), and Dr. Bardia Pezeshki (Avicena Tech). 🔍 Thank you to the authors who contributed to a strong Technical Program, as well as the tutorial presenters and Program Committee members who shaped this year’s content. 📚 What’s Next: 📺 Within the next month, all session content will be uploaded to YouTube, allowing everyone to revisit and reflect on the insightful discussions. 📝 We’re also working on making the slides available on https://hoti.org/, with authors' permission. 📖 Selected technical papers are currently under review and will be published as part of the IEEE Micro proceedings. Hot Interconnects 2024 has been a meaningful event, and we look forward to bringing even more value to HotI'25. 🌟 Stay tuned for updates coming next week! IEEE Computer Society #hoti #hoti24 #AI #datacenter #interconnection #smartnic #fpga #conference2024

Hot Interconnects in the news! Thanks for the reference, Davide Bassani. #hoti #hoti24 #conference2024

📅 Day 2 of IEEE Hot Interconnects 2024 has wrapped up with 1100+ registrants and 900+ attendees, and it was packed with insights and innovation! Tomorrow brings more excitement with a series of tutorials you won't want to miss. Here’s a quick recap of today's event: -- Pavan Balaji from Meta shared an in-depth keynote on the massive infrastructure supporting Llama3. -- Andy Bechtolsheim from Arista Networks explored whether interconnect technology can keep pace with AI's demands in a thought-provoking talk. -- Sreejit Chakravarty from Ampere addressed the challenges of standardizing chiplet-level interconnects test and repair. -- Uri Elzur from Intel Corporation offered an informative overview of UEC, highlighting its growing relevance. -- We delved into two technical sessions covering optimization for collective operations and collectives for Deep Learning. -- Alan Benjamin from GigaIO delivered an insightful sponsor talk, adding valuable perspectives. Missed today’s sessions? You can still catch up! Register for access here: https://lnkd.in/gy-69CQX or watch them on YouTube in about a month. Stay tuned for another day of innovation and discovery. IEEE Computer Society #hoti #hoti24 #AI #datacenter #interconnection #smartnic #fpga #conference2024

📅 The first day of IEEE Hot Interconnects 2024 is officially over! With over 1000+ registrations and 750+ attendees, today's sessions were truly exceptional. Here are some highlights: -- Mark Baciak from NeuralFabric Corp. delivered an enlightening overview of Micro-Models, large language models, and the evolving chip and data center design landscape. -- Tony Chan Carusone from Alphawave Semi gave a transformative talk on how chiplet technology is meeting AI's demands through enhanced connectivity and efficiency. -- The panel discussion on "Bandwidth Scaling for AI Interconnect - More Wavelengths vs More Fiber?" featured industry experts Dr. Dan Kuchta (IBM Research), Dr. Peter Winzer (Nubis Communications), Dr. Rebecca Schaevitz (Mixx Technologies Inc), Dr. Amit Nagra (Intel Corporation), Dr. Alan Liu (Quintessent Inc.), and Dr. Bardia Pezeshki (Avicena Tech) - a must-watch! -- We had an incredible range of technical sessions, covering everything from Interconnection Network design to communication for large language models. -- Engaging talks from our Platinum sponsor, Ramin Farjadrad from Eliyan Corporation, added valuable insights. Catch up on all the talks here: https://lnkd.in/gy-69CQX (register for access) or watch them on YouTube later in about a month timeframe. Stay tuned for more updates as we head into Day 2! IEEE Computer Society #hoti #hoti24 #AI #datacenter #interconnection #conference2024

If you haven’t registered yet, there’s still time to join us for IEEE Hot Interconnects - happening tomorrow! 👉 Register Here for free: https://lnkd.in/gkEy-bvX Why Register?    Free Proceedings: All attendees receive complimentary access to the conference proceedings.    Session Recordings: Can’t attend every session? No worries! Register and attend to gain access to all session recordings on our event page post-conference. Link to join the conference lobby: https://lnkd.in/gy-69CQX Don’t miss out on these valuable resources. See you there tomorrow! IEEE Computer Society #hoti #hoti24 #hpc #datacenter #interconnection #smartnic #fpga #conference2024

🕒 Less than 48 hrs until IEEE Hot Interconnects 2024! Free Registration Link: https://lnkd.in/gkEy-bvX The final countdown is on! Join us as we explore "Can Interconnects Keep up with AI?" through insightful panels, keynotes, invited talks, technical papers, and tutorials. 📅 Date: Aug 21 - Aug 23, 2024 📍 Location: Virtual Featured Sessions:    Panel:        "Bandwidth Scaling for AI Interconnect - More Wavelengths versus More Fiber?"             Dr. Dan Kuchta (Research Staff Member, IBM Research Yorktown)             Dr. Peter Winzer (Founder & CTO, Nubis Communications)             Dr. Rebecca Schaevitz (Co-founder & Chief Product Officer, Mixx Technologies Inc)             Dr. Amit Nagra (VP & GM, Silicon Photonics Product Division, Intel Corporation)             Dr. Alan Liu (Co-founder & CEO, Quintessent Inc.)             Dr. Bardia Pezeshki (Founder & CEO, Avicena Tech)        Moderator: Dr. Katharine Schmidtke (Co-founder, Eribel Systems)    Keynotes:        "Connectivity for AI Everywhere: The Role of Chiplets" - Dr. Tony Chan Carusone, CTO, Alphawave Semi and Professor of ECE, University of Toronto        "Powering Llama 3: A Sneak-peek into Meta's Massive Infrastructure for Generative AI" - Dr. Pavan Balaji, Principal Research Scientist and Technical Lead, Meta        "Keeping Pace: Micro-Models, Large Language Models, and the Co-Evolution of Chip and Data Center Design in a Rapidly Shifting AI Landscape" - Mark Baciak, CTO, NeuralFabric Corp.    Invited Talks:        "Can Interconnects Keep Up with AI? YES!" - Andy Bechtolsheim, Founder and Chief Architect of Arista Networks        "IEEE P3405: A Chip-let Interconnect Test and Repair Standard" - Dr. Sreejit Chakravarty, Distinguished Engineer at Ampere Computing "Ultra Ethernet Consortium (UEC) overview – solving the AI/HPC Scale-Out Network Challenge" - Uri Elzur, Sr. Principal Engineer at Intel Corporation We also have an exciting lineup of technical paper sessions and tutorials. Explore the full program here: https://hoti.org/program Thanks to our sponsors: Eliyan Corporation, Arista Networks, Salience Labs, GigaIO, Nutanix, and Lenovo, and media partner: HPCwire Visit https://hoti.org/ for more details. IEEE Computer Society #hoti #hoti24 #hpc #datacenter #interconnection #smartnic #fpga #conference2024

We are pleased to announce that Uri Elzur, Sr. Principal Engineer at Intel Corporation, will deliver an invited talk on Ultra Ethernet Consortium (UEC) at Hot Interconnects 2024. Title: Ultra Ethernet Consortium (UEC) overview – solving the AI/HPC Scale-Out Network Challenge Abstract: The industry race for an ever faster, better, lower total cost of ownership (TCO), easy to operate and lower CO2 footprint AI and HPC “At Scale” solutions, was never stronger, large scale distributed parallel processing is not new, but AI does present new challenges on the network, critical for best Job Completion Time (JCT). AI and HPC “At Scale” workloads are distributed parallel processing where tail latency directly impacts the Job Completion Time. The Network technology crucially affects the machine performance for these essentially parallel processing problems. Large Language Models (LLMs), as well as recommendation, are trained on clusters of thousands of GPUs, straining the ability to effectively manage tail latency. The network industry is responding with a set of well-coordinated technologies to modernize the communication stack on top of the ubiquitous Ethernet networks. In this talk, we will cover the key challenges of existing network technologies and the Ultra Ethernet Consortium’s direction to address them. Speaker Bio: Uri Elzur is a Senior Principal Engineer and leads the GPU network architecture work at Intel’s DCAI Group. In this role, he is responsible for creating networking related technical strategy and architecture, for AI/ML and HPC networks. Uri represents Intel on the Ultra Ethernet consortium and chairs its Technical Advisory Committee. His experience in hardware, networking and multiple open source top-to-bottom stack architectures, serves him well as a guide. Prior to this position, Uri has focused on SDN/NFV and has also represented Intel as VC Architecture for the Telco industry Open-O MANO community, ETSI Experiential Networked Intelligence (ENI), IETF NSH co-editor, OpenStack, OpenDaylight SDN (TSC and board), and worked on vSwitch technology and RDMA/iWARP. Uri is a networking specialist with more than 30 years of industry experience and a proven track record of creating innovative product architectures, strategies and in Networking, Virtualization, Security etc. Previously, Uri has held a position of a Sr. Director at Broadcom, managing the networking/NIC architecture team. In that role Uri led multiple innovations in the areas of Virtualization, TCP offload, RDMA, iSER and iSCSI/FCoE. Don't miss the valuable insights on UEC. Register now: https://lnkd.in/gkEy-bvX #hoti #hoti24 #hpc #datacenter #interconnection #smartnic #fpga #conference2024

A big thanks to our sponsors and media partner! As we approach Hot Interconnects 2024 next week, we’d like to express our sincere gratitude to our valued sponsors and our media partner. We especially thank our sponsors: Eliyan Corporation, Arista Networks, Salience Labs, GigaIO, Nutanix, and Lenovo. We also extend our appreciation to HPCwire for their partnership, which helps us reach a broader audience. Your support is vital to the success of this event, and we’re proud to have you with us. Thanks to your commitment, we’re able to bring together industry leaders to share insights, explore emerging technologies, and foster meaningful connections. Don’t miss this opportunity to engage with cutting-edge technical content and connect with professionals in the field. 🔗 https://lnkd.in/gkEy-bvX We look forward to welcoming you! #hoti #hoti24 #hpc #datacenter #interconnection #smartnic #fpga #conference2024

Only 10 Days to go for Hot Interconnects 2024 - secure your spot now! 🎟️ Free registration is still open: 🔗 https://lnkd.in/grVxbnNj   We’re honored to have Tony Chan Carusone, CTO at Alphawave Semi, delivering a keynote on “Connectivity for AI Everywhere: The Role of Chiplets.” This is a pivotal session for anyone invested in the future of AI and chiplet technology.   Abstract: Chiplet technology is set to be a transformational paradigm. It offers compelling advantages in cost, time-to-market, and power consumption. AI has emerged as a primary catalyst for this trend because the only way to meet the accelerated demands of AI is by using chiplets. By combining dense logic, memory, and high-speed connectivity chiplets, new silicon systems tailored to specific workloads can be created without starting from scratch each time. As chiplet adoption increases, so do the bandwidth demands both within the package across die-to-die interfaces, and beyond the package. Low-latency inter-die communication is crucial for compute performance, and high-speed optical interconnects are vital for scaling AI clusters.   Don’t miss this chance to connect with industry leaders and expand your professional network. Time is running out—register today and be part of Hot Interconnects 2024. We can’t wait to see you there! #hoti #hoti24 #hpc #datacenter #interconnection #smartnic #fpga #conference2024