Anurag Goyal

* Designed 5 stage pipeline processor for RISC-V RV32I ISA.
* Implemented Hazard Detection Unit and Forwarding Unit to minimize the pipeline stall to one instruction in case of RAW dependency.
* Verified for functionality on Arty S7 development kit incorporating Xilinx Spartan-7 FPGA at 150MHz.

• Implemented a system which invokes a command prompt which supports commands such as reading the circuit from pre-specified format text file, pre-processing, levelization, test generators using D-algorithm and PODEM and parallel and deductive fault simulator. Tested on ISCAS benchmark circuit.
• Read circuit into a doubly-linked list. Implemented D-algorithm after pre-processing. Generated a 5-valued logic vector (if detectable) for each stuck at fault list from pre-processing.

• Implemented the Scaler Read, Scaler Write, Burst Read/Write, Block Read/Write and Atomic Read/Write operations in Verilog.
• Synthesized the design using the Synopsis Design Compiler.
• Optimized and completed the Post Synthesis Simulation using NCSim.

• Implemented the above design using Verilog.
• Simulated, Synthesized and conducted Post synthesis simulation using NCSim and Synopsys Design Compiler.

• Implemented the RTL design for the above modules in Verilog.
• Completed the place and route using ‘Cadence Encounter’ and Static Timing Analysis using ‘Synopsys PrimeTime’

Worked on designing of remote controlled wireless semiautonomous car using IR and Proximity Sensors.

Developed switching control of Electrical appliances using Dial Tone Multi Frequency decoder and Microchip’s PIC 16F877A microcontroller.

• Worked on Microchip’s PIC 16F877A microcontroller along with CC2500 RF module working on 2.4GHz
• Designed PCB using EAGLE CAD
• Acquired programming knowledge of PWM and Analog to Digital Conversion.

• Designed a memory controller for DDR2 memory to perform basic read and write operations.

• Designed a memory controller to interface on board Cellular Ram with the picoblaze processor

• Implemented the concept of Named Data Networking.
• Designed a network router on the NetFPGA to route the packets based on the name of the packets.
• Implemented the same router using NDN Libraries in UNIX environment.
• Compared the performance of the two designs.

• Designed a 5 stage pipeline processor capable of supporting various instructions like ADD, Load Word, Store Word and Bit wise operation.
• Created schematics and layout for the same on Cadence Virtuoso.
• Optimized the above design for the minimum product of area, power and delay.

• Designed a Mini IDS to detect 64-bit data, and drop the entire packet if a match is found.
• Matching was done using Look up tables.

• Implemented SG, IG, LP and IG/LP modes of INV, NAND and NOR gates using Hspice.
• Calculated the number of fins to balance the rise and fall delay for each gate using Perl code to sweep the number of fins.

• Implemented a 5-stage Pipeline processor on NetFPGA and designed the processor’s custom ISA based on MIPS ISA.
• Created a compiler to translate C code to machine code and executed it on the network processor.

• Created schematics and layouts for the above design.
• Minimized the area and delay product on layout through sizing of the transistors.
• Verified the results using Perl Script.

• Created schematics and layouts for the above design.
• Minimized the area and delay product on layout through sizing of the transistors.

• Analysed nonstationary time series to predict the future trend with the utmost precision.
• Completed the Verilog code for the above system and verified the outputs with MATLAB..

• Implemented Hazard Detection Unit and Forwarding Unit to eliminate data dependency hazards.
• Completed the above design using Verilog on Model Sim.

• Layout implementation of CMOS gates (INV, NAND, NOR, XOR), MUX, 4-bit adder in 200nm CMOS technology using Cadence Virtuoso layout editor.
• Minimized the propagation delay through sizing of the transistors.

• Developed a MATLAB code to convert handwritten and printed text in a digital format.
• Acquired knowledge to implement Wavelet and Hough Transform on MATLAB.