INDRASHIS POWALI

INDRASHIS POWALI

Boise, Idaho, United States
972 followers 500+ connections

About

Self-driven, analytical, and innovative problem solver towards cost-effective and…

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Contributions

Activity

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Experience

  • Micron Technology Graphic
  • -

    Lubbock, Texas, United States

  • -

    Mumbai, Maharashtra, India

  • -

    Gurgaon, Haryana, India

  • -

    Kolkata, West Bengal, India

  • -

    Kolkata Area, India

Education

  • Texas Tech University Graphic

    Texas Tech University

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    Graduate Student in the Electrical & Computer Engineering at the Texas Tech University, Lubbock, Texas, USA

  • -

    Activities and Societies: Project: Temperature Controller using PID algorithm

Licenses & Certifications

Courses

  • Biosensors and Bioelectronics

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  • Design and Analysis of Analog Integrated Circuits

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  • Engineering Analysis

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  • Functional Materials

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  • Introduction to MicroSytems - I

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  • Introduction to Semiconductor Processing

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  • Introduction to VLSI Design

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  • Microwave Solid State Circuits

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  • Sensors and Detectors

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  • Solid State Devices

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  • Spintronic Devices and Applications

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Projects

  • Effect of Annealing on as-grown hexagonal Boron-nitride

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    Did high-temperature annealing of Lab-grown hexagonal Boron Nitride (h-BN), a Wide-Band-Gap
    Semiconductor, to find out whether characteristics improve

  • HVPE Growth of AlN

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    Did HVPE growth of AlN on SiC; Handled equipment for maintenance and troubleshooting

  • Self-biased 2-stage Operational Amplifier

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    Designed and simulated a self-biased 2-stage Op-Amp in Cadence Virtuoso using ami 0.6μm CMOS
    technology, optimized design to match parameters and smaller layout

  • High Linearity Low Noise Amplifier (SoC)

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    Designed and fabricated a PCB for a high linear LNA for 2.45 GHz operating frequency as part of a
    system-on-chip (SoC), fulfilling tape-out requirements

  • Rotating Micro-Mirror using Torsional Ratcheting Actuator

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    Designed a micro-actuation system using Chevron Actuator in AutoCAD and Autodesk Inventor and
    simulated in ANSYS for testing and performance

  • Simulation of Arithmetic Logical Unit (ALU) using 4-bit NAND Gates

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    Designed and simulated a 4-bit ALU in Cadence Virtuoso using 0.6μm process ON Semiconductor,
    design optimized to reduce transistor count and propagation delay

Honors & Awards

  • SEACAT SCHOLARSHIP

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Languages

  • Bengali

    Native or bilingual proficiency

  • Hindi

    Professional working proficiency

  • English

    Full professional proficiency

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