About
Leveraging over 20 years of engineering, management, and innovation experience, I hope to…
Activity
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Join the BAE Systems team! This is an exciting opportunity as a portfolio level director within the Navigation and Sensor Systems product line…
Join the BAE Systems team! This is an exciting opportunity as a portfolio level director within the Navigation and Sensor Systems product line…
Liked by James Li
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NEWS: BAE Systems and GlobalFoundries announce new strategic agreement. Learn more: http://baes.co/xUXo50Smkbf
NEWS: BAE Systems and GlobalFoundries announce new strategic agreement. Learn more: http://baes.co/xUXo50Smkbf
Liked by James Li
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Valentine`s Day Smith Chart: I 💘 it! An undergraduate student generated this Smith Chart for his girlfriend on Valentine`s Day (and showed it to his…
Valentine`s Day Smith Chart: I 💘 it! An undergraduate student generated this Smith Chart for his girlfriend on Valentine`s Day (and showed it to his…
Liked by James Li
Experience
Education
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UC San Diego
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Developed physics-based, electro-thermal finite element and compact models of high performance InP HBTs, GaN HBTs, GaN HEMTs, and other novel electron devices.
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Modeling Polysilicon Gate Depletion in Submicron MOS Devices
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Publications
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Investigation of Power Detectors for Microwave/mm-Wave Imaging Systems
Solid-State Electronics
Other authors -
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An Active Double-Balanced Down-Conversion Mixer in InP/Si BiCMOS Operating from 70-110 GHz
IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)
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Broadband Noise Performance of Heterogeneously Integrated InP BiCMOS DHBTs
IEEE Electron Device Letters
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Microwave noise properties of heterojunction bipolar transistors
IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)
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A Wide-Bandwidth W-band LNA in InP/Si BiCMOS Technology
IEEE MTT-S International Microwave Symposium
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Circuit Applications of Heterogeneously Integrated InP HBTs on RF-CMOS
Communications Microsystems Optoelectronics Sensors Emerging Technologies Workshop
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Heterogeneous Integration of InP HBTs on CMOS: Leveraging and Providing Value to Conventional Silicon Technologies
ECS Transactions
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Heterogeneous Integration of InP HBTs and RF-CMOS technologies for RFICs
IEEE International Microwave Symposium, 3-D IC Workshop (WSC)
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Pervasive Modeling in InP HBT Technology Development
IEEE Compound Semiconductor Integrated Circuits Symposium
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InP HBTs - Present Status and Future Trends
IEEE Bipolar Circuits and Technology Meeting
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Patents
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Method and apparatus for hybrid delta-sigma and Nyquist data converters
Issued US 9,912,348
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Digital predistortion linearization for power amplifiers
Issued US 9,813,089
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Agile radio architecture
Issued US 9,531,571
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Method for forming metallic sub-collector for HBT and BJT transistors
Issued US 9,508,552
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Thermal management for heterogeneously integrated technology
Issued US 9,087,854
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Modulation doped super-lattice base for heterojunction bipolar transistors
Issued US 8,957,455
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Modulation doped super-lattice base for heterojunction bipolar transistors
Issued US 8,178,946
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Bipolar transistor test structure with lateral test probe pads
Issued US 6,958,491
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Mechanically-stable BJT with reduced base-collector capacitance
Issued US 6,870,184
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BJT device configuration and fabrication method with reduced emitter width
Issued US 6,858,887
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Testing apparatus and method for determining an etch bias associated with a semiconductor-processing step
Issued US 6,815,237
A testing apparatus for determining the etch bias associated with a semiconductor-processing step includes a substrate, a first cathode finger with a first width on the substrate, a second cathode finger with a second width on the substrate, and a cathode large area on the substrate wherein the cathode large area has a third width W" and a length L" that are both substantially larger than either of the first and second widths.
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Method of fabricating a bipolar transistor
Issued US 6,800,531
A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion…
A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.
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Heterojunction bipolar transistor with InGaAs contact and etch stop layer for InP sub-collector
Issued US 6,797,995
A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion…
A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.
Other inventors -
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Bipolar transistor characterization apparatus with lateral test probe pads
Issued US 6,605,825
Test probe pads are located lateral to, and spaced from, the emitter, base or collector region of a bipolar transistor, preferably on separate pedestals, and connected to their respective transistor regions by air bridges. The probe pads, transistor contacts and air bridges are preferably formed as common metallizations. In the case of an HBT, a gap in the subcollector below the air bridges insulates the test transistor from capacitor loading by the probe pads. The test transistors can be used…
Test probe pads are located lateral to, and spaced from, the emitter, base or collector region of a bipolar transistor, preferably on separate pedestals, and connected to their respective transistor regions by air bridges. The probe pads, transistor contacts and air bridges are preferably formed as common metallizations. In the case of an HBT, a gap in the subcollector below the air bridges insulates the test transistor from capacitor loading by the probe pads. The test transistors can be used to characterize both themselves and functional circuit transistors fabricated with the same process on the same wafer by testing at an intermediate stage of manufacture, thus allowing wafers to be discarded without completing the manufacture if their transistors do not meet specifications.
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Method for polysilicon crystalline line width measurement post etch in undoped-poly process
Issued US 6,456,082
A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of said polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon…
A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of said polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon line; connecting a third probe to the substrate; connecting a first terminal of a capacitance meter to the first and second probes; connecting a second terminal of the capacitance meter to the third probe; and applying a direct current bias across the first and second probes. A capacitor may be connected between the first and second probes. Further steps include, connecting a fourth probe to a conductor that supports the substrate; and connecting the fourth probe to the third probe.
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Method for polysilicon crystalline line width measurement post etch in undoped-poly process
Issued US 6,066,952
A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of the polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon…
A method of measuring a width of an undoped or lightly doped polysilicon line is disclosed. The width measuring method includes generating carriers in the polysilicon line with an energy source; measuring a capacitance between the polysilicon line and a substrate separated from the polysilicon line by a dielectric layer; and determining a line width of the polysilicon line from the measured capacitance. The capacitance measurement includes connecting first and second probes to the polysilicon line; connecting a third probe to the substrate; connecting a first terminal of a capacitance meter to the first and second probes; connecting a second terminal of the capacitance meter to the third probe; and applying a direct current bias across the first and second probes. A capacitor may be connected between the first and second probes. Further steps include, connecting a fourth probe to a conductor that supports the substrate; and connecting the fourth probe to the third probe.
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Projects
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International Technology Roadmap for Semiconductors
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Collaboration between various industry leaders to define the technology roadmaps for RF and Analog/Mixed Signal semiconductor technologies including GaAs HBT, InP HBT, GaAs pHEMT, InP HEMT, GaN HEMT, SiGe BiCMOS, and RF-CMOS.
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40Gbps Optical Communications Components
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Developing InP DHBT process technology and 40Gbps optical communication components (TIA, modulator driver, ADC, DAC, CDR) to support low power, high data rate networks with the intention of spinning off from Rockwell Scientific Company.
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IBM Hard Disk Read Channels
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Developing Analog/Mixed-signal read channel ICs for IBM hard disks including the IBM Micro-Drive product line
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IBM PowerPC 615 Microprocessor
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Developing the first dual core microprocessor to natively run 32 bit x86, 32 bit PowerPC, and 64 bit PowerPC instructions
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Under-graduate Research OPportunity (UROP)
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Massachusetts Institute of Technology
Materials Science and Engineering Department
Metallurgy Laboratory of Dr. Nicholas J. Grant
Physical properties of crystalline and amorphous high strength metallic alloys formed by liquid dynamic compaction -
New York State Young Scholars Research Program (YSRP)
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Binghamton University
Physics Department
Solid State Physics Laboratory of Dr. Eric J. Cotts
Analysis of the thermal properties of crystalline and amorphous NiZr Alloys under Gamma Irradiation
Languages
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English
Native or bilingual proficiency
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Chinese
Limited working proficiency
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French
Elementary proficiency
Organizations
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IEEE
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- Present
More activity by James
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We are pleased to announce that Dr. Don Widener, PhD, CTO, Intelligence Solutions at BAE Systems, has joined the "Leveraging Collaboration to…
We are pleased to announce that Dr. Don Widener, PhD, CTO, Intelligence Solutions at BAE Systems, has joined the "Leveraging Collaboration to…
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Announcing the grand unveiling of our new state-of-the-art advanced packaging assembly center in Odon, Indiana! We recently hosted a fantastic…
Announcing the grand unveiling of our new state-of-the-art advanced packaging assembly center in Odon, Indiana! We recently hosted a fantastic…
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Action – that is the only word needed to describe yesterday! The Northeast Microelectronics Coalition (NEMC) Hub in action! Yesterday we were able…
Action – that is the only word needed to describe yesterday! The Northeast Microelectronics Coalition (NEMC) Hub in action! Yesterday we were able…
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Very proud to receive the first CHIPS Act grant here at BAE Systems. This will expand our Microelectronics Center's capability to deliver…
Very proud to receive the first CHIPS Act grant here at BAE Systems. This will expand our Microelectronics Center's capability to deliver…
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This morning, U.S. Department of Commerce Secretary Gina Raimondo announced $35 million in initial funding to modernize our Microelectronics Center…
This morning, U.S. Department of Commerce Secretary Gina Raimondo announced $35 million in initial funding to modernize our Microelectronics Center…
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Deep dive delivers insights. Transceiver experts came together for uninterrupted dialogue, discovery, and learning under a new knowledge sharing…
Deep dive delivers insights. Transceiver experts came together for uninterrupted dialogue, discovery, and learning under a new knowledge sharing…
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This week, members of the Northeast Microelectronics Coalition (NEMC) gathered for two days of networking, learning, and discussing future…
This week, members of the Northeast Microelectronics Coalition (NEMC) gathered for two days of networking, learning, and discussing future…
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Today, I had the honor to be the Master of Ceremonies at the SHIP Prototype Delivery Ceremony in Falls Church, VA. The Honorable Heidi Shyu, babak…
Today, I had the honor to be the Master of Ceremonies at the SHIP Prototype Delivery Ceremony in Falls Church, VA. The Honorable Heidi Shyu, babak…
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