About
Jaydeep Kulkarni received a B.E. degree from the University of Pune, India, in 2002, an…
Experience
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Education
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Volunteer Experience
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Technical Program Committee Member
Symposia on VLSI Technology and Circuits
- Present 2 years 3 months
Science and Technology
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Technical Program Committee Member
Design Automation Conference
- Present 1 year 1 month
Science and Technology
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Committee Member- Student Research Preview
International Solid-State Circuits Conference - ISSCC
- Present 1 year 8 months
Education
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Associate Editor
IEEE Transactions on Circuits and Systems I: Regular Papers
- Present 9 months
Science and Technology
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Distinguished Lecturer
IEEE Solid state circuits society
- 2 years
Education
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VLSI Systems & Applications Technical Committee Member
IEEE Circuits and Systems Society (CASS)
- Present 9 years 9 months
Science and Technology
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Technical program Committee Member
IEEE Custom Integrated Circuits Conference
- 4 years 7 months
Science and Technology
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Chair IEEE Central Texas SSCS/CAS Joint chapter
IEEE
- 3 years
Education
The mission of this joint IEEE chapter is to interact with the SSCS/CAS members in Central Texas area (surrounding Austin) through education, communication, recognition, leadership opportunities, and networking.
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Guest Editor for IEEE Micro, Special issue on Hot Chips 2020
IEEE
- Present 4 years 9 months
Science and Technology
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International Conference on Computer-Aided Design (ICCAD), Technical Program Committee Member
IEEE
- Present 7 years 2 months
Science and Technology
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Technical Program Committee, AICAS
IEEE Circuits and Systems Society (CASS)
- Present 5 years 3 months
Science and Technology
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General Co-chair, International Symposium on Low Power Electronics Design (ISLPED)
ACM, Association for Computing Machinery
- 1 year 1 month
Science and Technology
General Co-chair, 2018, ISLPED
Technical program co-chair, 2017 ISLPED
Session co-chair, 2016 ISLPED
Technical Program Committee Member, 2013-2016, ISLPED -
TPC Co-chair
Vlsi design conference 2023
- 1 year 2 months
Science and Technology
Publications
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Source-Underlapped GaSb-InAs TFETs With Applications to Gain Cell Embedded DRAMs
IEEE Transactions on Electron Devices
See publicationIn this paper, a detailed evaluation of sub-10-nm n-/p-type GaSb-InAs double-gate tunneling FETs (TFETs) is presented. Source underlapping is shown to achieve lower subthreshold swing (SS) in both n- and p-type GaSb-InAs TFETs and is verified with the analytical treatment. The impact of parameter variations on the performance of underlapped TFETs is investigated through atomistic, 2-D ballistic simulations using self-consistently coupled nonequilibrium Green's function-Poisson approach…
In this paper, a detailed evaluation of sub-10-nm n-/p-type GaSb-InAs double-gate tunneling FETs (TFETs) is presented. Source underlapping is shown to achieve lower subthreshold swing (SS) in both n- and p-type GaSb-InAs TFETs and is verified with the analytical treatment. The impact of parameter variations on the performance of underlapped TFETs is investigated through atomistic, 2-D ballistic simulations using self-consistently coupled nonequilibrium Green's function-Poisson approach. Variations in underlap length, underlap doping, fin thickness, and temperature are comprehensively studied. It is shown that the underlap length of 6 nm is optimal for achieving low SS and it is found that the underlapped TFETs can maintain sub-60-mV/decade SS even when 3-nm fin thickness is relaxed by 40%. We also study the potential of TFETs in ultralow-power and high-density dynamic memories. A novel 4T gain cell embedded Dynamic Random Access Memory (e-DRAM) is proposed, which utilizes the low-leakage current of the source-underlapped TFETs to improve the data-retention time to 25 μs at VDD = 0.35 V, thereby enabling the prospects of e-DRAM at nanoscale gate lengths operating at ultralow supply voltages.
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Post-Silicon Voltage Guard-Band Reduction in a 22nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
International Solid State Circuits Conference (ISSCC)
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5.6Mb/mm2 1R1W 8T SRAM Arrays Operating down to 560mV Utilizing Small-Signal Sensing with Charge Shared Bitline and Asymmetric Sense Amplifier in 14nm FinFET CMOS Technology
International Solid State Circuits Conference (ISSCC)
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A 409 GOPS/W Adaptive & Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin & Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature & Aging
IEEE journal of Solid State Circuits
Invited paper to JSSC special issue on ISSCC 2015
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A 409 GOPS/W Adaptive and Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging
International Solid State Circuits Conference (ISSCC)
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Enabling Wide Autonomous DVFS in a 22nm Graphics Execution Core Using a Digitally-Controlled Hybrid LDO/Switched-Capacitor VR with Fast Droop Mitigation
International Solid State Circuits Conference (ISSCC)
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Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability
IEEE Electron Device Letters
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A 22nm Graphics Execution Core with Wide Voltage Range and 40% Higher Peak GFLOPS/W via Adaptive Clocking, Selective Boosting, and State-Retentive Sleep”
International Solid State Circuits Conference (ISSCC)
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Tri-Mode Independent Gate FinFET based SRAM with Pass Gate Feedback: Technology-Circuit Co-design for Enhanced Cell Stability
IEEE Transactions on Electron Devices
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Dual-Vcc 8T-bitcell SRAM Array in 22nm Tri-gate CMOS for energy efficient operation across wide dynamic voltage range
VLSI Circuit Symposium
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Process-Variation Tolerant Heterojunction Intra-band Tunnel (HIBT) FETs for Low Voltage SRAMs
IEEE Transactions on Electron Devices
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Capacitive-coupling wordline boosting with self-induced Vcc collapse for write Vmin reduction in 22-nm 8T SRAM
International Solid-State Circuits Conference (ISSCC)
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Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
IEEE Transactions on VLSI systems
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Read-Disturb-Free, Differential Sensing 1R/1W Port 8T Bitcell Array
IEEE Transactions on VLSI systems
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Characterization of Random Process Variations using Ultra Low Power High Sensitivity, Bias Free Sub-threshold Process Sensor
IEEE Transactions on Circuits and Systems-I,
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Nano-Spiral Inductors for Low Power Digital Spintronic Circuits
IEEE Transactions on Magnetics
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Analysis of SRAM and eDRAM Cache Memories under Spatial Temperature Variations
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems
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Technology Circuit Co-design for Ultra Fast InSb Quantum Well Transistors
IEEE Transactions on Electron Devices
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A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
IEEE Journal of Solid-State Circuits
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A Fast LSF Search Algorithm Based on Inter-frame Correlation in G.723.1
EURASIP Journal On Applied Signal Processing
Patents
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low voltage swing repeater
Issued US 8,847,633
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Static random access memory cell and devices using the same
Issued US 7952912
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Apparatus for dual purpose charge pump
Filed US 14/137808
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Assist circuit for memory
Filed US 14/229767
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Memory write operation methods and circuits
Filed US 823642
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Adaptive self-repairing cache
US US20130262768 A1
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Apparatus for reducing di/dt during power wake-up
US USPTO 14/951,343
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Apparatus for reducing write minimum supply voltage for memory”
US USPTO 13/536,521
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Capacitive wordline boosting
US USPTO 14/752464
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Circuits and methods for memory
US 20130003469
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Current Steering Level Shifter
US USPTO 14/569,569
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Delta-Vdd aware Vmin assist techniques for ultra-low voltage level shifter
US USPTO 14/553,934
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Digitally trimmable integrated resistors including resistive memory devices
US USPTO 14/750,670
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Fast Fourier transform architecture
US PCT/US2015/66963
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Memory array having extended write operation
US 20110149661
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Memory device including encoded data-line multiplexer
US USPTO 14/ 859,884
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Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states
US 20120151235
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Methods and systems to selectively boost an operating voltage of, and controls to an 8t bit-cell array and/or other logic blocks
US WO2013147742 A1
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Multi-supply sequential logic unit
US WO2013089698 A1
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Register files including distributed capacitor circuit blocks
US USPTO, 14/937,010
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Resilient register file circuit for dynamic variation tolerance and method of operating the same
US PCT/US2011/067632
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Honors & Awards
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Distinguished Lecturer
IEEE Circuits and Systems Society (CASS)
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Best Associate Editor Award
IEEE Journal on Emerging and Selected Topics in Circuits and Systems
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SRC Innovator Award
Semiconductor Research Corporation (SRC)
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Junior Faculty Excellence in Teaching Award
University of Texas at Austin
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Senior Member, US National Academy of Inventors
US National Academy of Inventors
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NSF Career Award
National Science Foundation (NSF)
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Rising Star Faculty Award
Intel
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Mehboob Khan Outstanding Industry Liaison Award
Semiconductor Research Corporation (SRC)
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IEEE Transactions on VLSI Systems, Best Paper Award
IEEE Circuits and Systems Society
For the paper titled, "Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design"
Authors: Jaydeep P. Kulkarni, Kaushik Roy -
Senior Member
IEEE
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Patent Recognition Award
Intel
For filing 5 or more patents in an year
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Outstanding Doctoral Dissertation Award
Purdue University
Title: Low voltage Robust Memory Circuit Design
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Best Paper in Session Award
SRC TECHCON
Ultra-low Voltage Process Variation Tolerant Schmitt Trigger based SRAM Design
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SRC Inventor Recognition Awards
Semiconductor Research Corporation (SRC)
Two awards for inventing Schmitt Trigger based SRAM Designs.
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ISLPED Design Contest Award
International Symposium on Low Power Electronics Design (ISLPED)
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Intel Foundation Ph.D. Fellowship Award
Intel Corporation
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Best M.Tech student award, CEDT design medal
Indian Institute of Science (IISc)
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Top 10 University Ranker - Senior year
University of Pune
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Top 10 University Ranker - Junior year
University of Pune
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National Talent Search (NTS) scholarship
Government of India
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Best Project Award, National Children Science Congress, New Delhi
Government of India
Experimental demonstration of maximum air pollution mitigation with Ocimum Sanctum (Tualsi) plants
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