Kanu Gulati

Kanu Gulati

San Francisco Bay Area
9K followers 500+ connections

About

Kanu Gulati (@kanugulati at Twitter) is a Partner at Khosla Ventures, a Silicon Valley VC…

Experience

  • Khosla Ventures Graphic

    Khosla Ventures

    San Francisco Bay Area

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    Berkeley, California

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    UC Berkeley

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    San Francisco Bay Area

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    San Francisco Bay Area

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    San Francisco Bay Area

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    San Francisco Bay Area

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    College Station, TX

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    Strategic CAD Labs. Hillsboro, OR

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    Austin, Texas Area

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    Berkeley, California

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    Noida Area, India

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    Noida Area, India

Education

  • Harvard Business School Graphic

    Harvard Business School

    Activities and Societies: • Co-President, HBS VCPE Conference • 2nd place in Northeast Regional Finals Venture Capital Investment Competition (VCIC) • Head for Startup Panel, Techmedia Conference • HBS VCPE Career trek leader • First Year Honors

  • Activities and Societies: • Technical program Committee ISCAS, ISQED • Reviewer for TCAD, TVLSI, TODAES • Reviewer for DAC, ICCAD, IWLS, ASQED and ICCD • Member of IEEE and ACM

    Google Scholar: https://scholar.google.com/citations?user=1P6zBt4AAAAJ

    Books and Book Chapters:
    • "EDA Algorithm Acceleration with FPGAs, GPUs, and Custom ICs", Gulati, Khatri.
    • "Minimizing and Exploiting Leakage in VLSI Design", Jayakumar, Paul, Garg, Gulati, Khatri.
    • “Advanced Techniques in Logic Synthesis, Optimizations and Applications” Editors: Khatri and Gulati.
    • “A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations”, Cobb, Gulati…

    Google Scholar: https://scholar.google.com/citations?user=1P6zBt4AAAAJ

    Books and Book Chapters:
    • "EDA Algorithm Acceleration with FPGAs, GPUs, and Custom ICs", Gulati, Khatri.
    • "Minimizing and Exploiting Leakage in VLSI Design", Jayakumar, Paul, Garg, Gulati, Khatri.
    • “Advanced Techniques in Logic Synthesis, Optimizations and Applications” Editors: Khatri and Gulati.
    • “A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations”, Cobb, Gulati, Khatri.

  • Activities and Societies: • Research and Teaching Assistant • External Reviewer for DAC, ICCAD, IWLS, ASQED and ICCD, TCAD, TVLSI. • Member of IEEE and ACM • Tennis Intermediate

  • Activities and Societies: Event Head for IEEE Student Chapter Conference, Women's Sports In-charge, Inter College Badminton, Choreography Team

Volunteer Experience

  • Logistics Lead 'She Will' Campaign - Intel Computer Club

    Boys and Girls Clubs of America

    - 1 year 4 months

    Education

    - Taught 12 club members (ages 10-14) Android application development. Focused on apps that promote education.
    - Led 10 Intel volunteers in planning the app development workshop and schedule.

  • Workshop Mentor

    Afghan Women's Writing Project

    - 2 years 1 month

    Education

  • Mentor

    International Telementor Program

    - 2 years 1 month

    Education

Publications

Patents

  • Toggle equivalence preserving logic synthesis

    Issued US 7600211

    Other inventors
    • Evgueni Goldberg

Honors & Awards

  • Intel Division Recognition Award

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  • SCL Research Award

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  • NVIDIA Fellow

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  • Runner Up, Northeast Regionals in Venture Capital Investment Competition (VCIC) held at NYU Stern

    Venture Capital Investment Competiiton

Languages

  • English

    Native or bilingual proficiency

  • Hindi

    Native or bilingual proficiency

  • Punjabi

    Native or bilingual proficiency

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