Loïck Le Guevel

The superconducting fluxonium qubit has a great potential for high-fidelity quantum gates with its long coherence times and strong anharmonicity at the half flux quantum sweet spot. However, current implementations of two-qubit gates compromise fluxonium's coherence properties by requiring either a temporary population of the non-computational states or tuning the magnetic flux off the sweet spot. Here we realize a fast all-microwave cross-resonance gate between two capacitively-coupled… Show more

The superconducting fluxonium qubit has a great potential for high-fidelity quantum gates with its long coherence times and strong anharmonicity at the half flux quantum sweet spot. However, current implementations of two-qubit gates compromise fluxonium's coherence properties by requiring either a temporary population of the non-computational states or tuning the magnetic flux off the sweet spot. Here we realize a fast all-microwave cross-resonance gate between two capacitively-coupled fluxoniums with the qubit dynamics well confined to the computational space. We demonstrate a direct CNOT gate in 70 ns with fidelity up to F=0.9949(6) despite the limitations of a sub-optimal measurement setup and device coherence. Our results project a possible pathway towards reducing the two-qubit error rate below 10−4 with present-day technologies. Show less

In the strive for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. Here we report on a cryogenic circuit incorporating a CMOS-based active inductor enabling fast impedance measurements with a sensitivity of 10 aF and an input-referred noise of 3.7 aF/sqrt(Hz). This type of circuit is especially conceived for the readout of semiconductor spin qubits. As opposed to… Show more

In the strive for scalable quantum processors, significant effort is being devoted to the development of cryogenic classical hardware for the control and readout of a growing number of qubits. Here we report on a cryogenic circuit incorporating a CMOS-based active inductor enabling fast impedance measurements with a sensitivity of 10 aF and an input-referred noise of 3.7 aF/sqrt(Hz). This type of circuit is especially conceived for the readout of semiconductor spin qubits. As opposed to commonly used schemes based on dispersive rf reflectometry, which require mm-scale passive inductors, it allows for a markedly reduced footprint (50μm × 60μm), facilitating its integration in a scalable quantum-classical architecture. In addition, its active inductor results in a resonant circuit with tunable frequency and quality factor, enabling the optimization of readout sensitivity. Show less

The development of quantum electronic devices operating below a few Kelvin degrees is raising the demand for cryogenic complementary metal-oxide-semiconductor electronics (CMOS) to be used as in situ classical control/readout circuitry. Having a minimal spatial separation between quantum and classical hardware is necessary to limit the electrical wiring to room temperature and the associated heat load and parasitic capacitances. Here, we report prototypical demonstrations of hybrid circuits… Show more

The development of quantum electronic devices operating below a few Kelvin degrees is raising the demand for cryogenic complementary metal-oxide-semiconductor electronics (CMOS) to be used as in situ classical control/readout circuitry. Having a minimal spatial separation between quantum and classical hardware is necessary to limit the electrical wiring to room temperature and the associated heat load and parasitic capacitances. Here, we report prototypical demonstrations of hybrid circuits combining silicon quantum dot devices and a classical transimpedance amplifier, which is characterized and then used to measure the current through the quantum dots. The two devices are positioned next to each other at 4.2 K to assess the use of the cryogenic transimpedance amplifier with respect to a room-temperature transimpedance amplifier. A quantum device built on the same substrate as the transimpedance amplifier is characterized down to 10 mK. The transimpedance amplifier is based on commercial 28 nm fully depleted Silicon-on-insulator (FDSOI) CMOS. It consists of a two-stage Miller-compensated operational amplifier with a 10 MΩ polysilicon feedback resistor, yielding a gain of 1.1×107 V/A. We show that the transimpedance amplifier operates at 10 mK with only 1 μW of power consumption, low enough to prevent heating. It exhibits linear response up to ±40 nA and a measurement bandwidth of 2.6 kHz, which could be extended to about 200 kHz by design optimization. The realization of custom-made electronics in FDSOI technology for cryogenic operation at any temperature will improve measurement speed and quality inside cryostats with higher bandwidth, lower noise, and higher signal-to-noise ratio.
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The paper presents an 8-bit differential current steering digital-to-analog converter (DAC) for the cryogenic front-end of future quantum computers. Recently published characterization of CMOS technology reveals the deterioration of transistor matching properties at cryogenic temperatures. The preliminary study of current mismatch in the FDSOI technology at 4.2 K allows proper sizing of the 255 current-source unit cells to mitigate non-linearities and optimize the static DAC performance. Based… Show more

The paper presents an 8-bit differential current steering digital-to-analog converter (DAC) for the cryogenic front-end of future quantum computers. Recently published characterization of CMOS technology reveals the deterioration of transistor matching properties at cryogenic temperatures. The preliminary study of current mismatch in the FDSOI technology at 4.2 K allows proper sizing of the 255 current-source unit cells to mitigate non-linearities and optimize the static DAC performance. Based on this study we minimize the power consumption while maintaining the targeted non-linearity, i.e. 7.3μW for DNL=0.64 LSB. With a 6.6 mV output range and 26 B5V voltage step, our DAC is compatible with the foreseen requirements for fine-grain biasing a Si-based qubit matrix at an expected 100MS/s on-chip output drive. Show less

Variability of 28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (ULT), at T=100mK. High performance is achieved at ULT for short channel transistors, with ION>1mA/µm and IOFF below the equipment accuracy <1fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (RT) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations… Show more

Variability of 28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (ULT), at T=100mK. High performance is achieved at ULT for short channel transistors, with ION>1mA/µm and IOFF below the equipment accuracy <1fA, in particular by keeping advantage of forward back biasing (FBB), with the same efficiency from room temperature (RT) down to 100mK. The physical origins of MOSFET mismatch at ULT are studied, highlighting the impact of the charge fluctuations increase on both threshold voltage (VTH) and current gain factor (β) variabilities. Besides that, we demonstrated that the increase of VTH and β variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures. Show less

Mismatch performance of 28 nm FDSOI technology is electrically characterized at low temperatures using integrated on-chip addressing for a matrix of transistors. The first statistical results ever published on FDSOI variability at 4.2 K provide valuable information for future compact transistor modeling in cryogenic circuit design. Slight increase of the threshold voltage mismatch is observed at low temperature. Nevertheless, the suppression of fluctuations in the random distribution of dopants… Show more

Mismatch performance of 28 nm FDSOI technology is electrically characterized at low temperatures using integrated on-chip addressing for a matrix of transistors. The first statistical results ever published on FDSOI variability at 4.2 K provide valuable information for future compact transistor modeling in cryogenic circuit design. Slight increase of the threshold voltage mismatch is observed at low temperature. Nevertheless, the suppression of fluctuations in the random distribution of dopants for the fully-depleted transistor channel leads to a smaller threshold voltage variability for FDSOI at 4.2 K compared to advanced Bulk technology at room temperature. Show less

In the standard MOSFET description of the drain current ID as a function of applied gate voltage VGS, the subthreshold swing SS(T) dVGS/d log ID has a fundamental lower limit as a function of temperature T given by SS(T) = ln10 kBT/e. However, recent low-temperature studies of different advanced CMOS technologies have reported SS(4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of SS(T ) in 28 nm fully-depleted silicon-on-insulator… Show more

In the standard MOSFET description of the drain current ID as a function of applied gate voltage VGS, the subthreshold swing SS(T) dVGS/d log ID has a fundamental lower limit as a function of temperature T given by SS(T) = ln10 kBT/e. However, recent low-temperature studies of different advanced CMOS technologies have reported SS(4 K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of SS(T ) in 28 nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n-and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4 K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold ID ~ e eVGS/kBT0for T0 = 35K with saturation value SS(T < T) = ln10 kBT/e. The proposed model adequately describes the experimental data of SS(T ) from 300 down to 4 K using kBT0 ≃ 3 meV for the width of the exponential tail and can also accurately describe SS(ID) within the whole subthreshold region. Our analysis allows a direct determination of the technology-dependent band-tail extension forming a crucial element in future compact modeling and design of cryogenic circuits. Show less

Extensive electrical characterization of ring oscillators (ROs) made in high-κ metal gate 28-nm fully depleted silicon-on-insulator technology is presented for a set of temperatures between 296 and 4.3 K. First, delay per stage (τ P ), static current (I STAT ), and dynamic current (I DYN ) are analyzed for the case of the increase of threshold voltage (V TH ) observed at low temperature. Then, the same analysis is performed by compensating V TH to a constant, temperature-independent value… Show more

Extensive electrical characterization of ring oscillators (ROs) made in high-κ metal gate 28-nm fully depleted silicon-on-insulator technology is presented for a set of temperatures between 296 and 4.3 K. First, delay per stage (τ P ), static current (I STAT ), and dynamic current (I DYN ) are analyzed for the case of the increase of threshold voltage (V TH ) observed at low temperature. Then, the same analysis is performed by compensating V TH to a constant, temperature-independent value through forward body biasing (FBB). Energy efficiency optimization is proposed for different supply voltages (V DD ) in order to find an optimal operating point combining both high RO frequencies and low-power dissipation. We show that the EnergyDelay product can be significantly reduced at low temperature by applying an FBB voltage (V FBB ). We demonstrate that outstanding performance of RO in terms of speed (τ P = 37 ps) and static current (7nA/stage) can be achieved at 4.3 K with V DD reduced down to 0.325 V. Show less