Naresh Soni

Methods, apparatuses and systems for performing hierarchical traffic differentiation and/or employing hierarchical traffic differentiation are provided. These methods, apparatuses and systems may be implemented to, for example, handle congestion and/or to manage user quality of experience (QoE). Performing the hierarchical traffic differentiation may include differentiating or otherwise classifying (collectively “differentiating”) traffic mapped to, or within, a bearer formed in accordance with… Show more

Methods, apparatuses and systems for performing hierarchical traffic differentiation and/or employing hierarchical traffic differentiation are provided. These methods, apparatuses and systems may be implemented to, for example, handle congestion and/or to manage user quality of experience (QoE). Performing the hierarchical traffic differentiation may include differentiating or otherwise classifying (collectively “differentiating”) traffic mapped to, or within, a bearer formed in accordance with a QoS class into multiple traffic sub-classes. Employing the hierarchical traffic differentiation may include scheduling and/or policing (e.g., filtering) the differentiated traffic for transmission based on a prioritization of, and/or policy for managing, the multiple traffic sub-classes.
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Described herein are methods and systems associated with viewing condition adaption of multimedia content. A method for receiving multimedia content with a device from a network may include determining a viewing parameter, transmitting a request for the multimedia content to the network, whereby the request may be based on the viewing parameter, and receiving the multimedia content from the network, whereby the multimedia content may be processed at a rate according to the viewing parameter… Show more

Described herein are methods and systems associated with viewing condition adaption of multimedia content. A method for receiving multimedia content with a device from a network may include determining a viewing parameter, transmitting a request for the multimedia content to the network, whereby the request may be based on the viewing parameter, and receiving the multimedia content from the network, whereby the multimedia content may be processed at a rate according to the viewing parameter. The viewing parameter may include at least one of: a user viewing parameter, a device viewing parameter, or a content viewing parameter. The method may further include receiving a multimedia presentation description (MPD) file from the network. The MPD file may include information relating to the rate of the multimedia content and information relating to the rate may include a descriptor relating to the viewing parameter, whereby the descriptor may be required or optional.
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The invention relates to a method for creating at least one piece of content to be rendered on a telecommunication terminal. According to the invention, the method comprises the step of associating at least one piece of optimization information with at least one predetermined portion of at least one of said pieces of content, said one or more pieces of optimization information indicating at least one operation condition of said terminal adapted to said content so that said terminal can adapt… Show more

The invention relates to a method for creating at least one piece of content to be rendered on a telecommunication terminal. According to the invention, the method comprises the step of associating at least one piece of optimization information with at least one predetermined portion of at least one of said pieces of content, said one or more pieces of optimization information indicating at least one operation condition of said terminal adapted to said content so that said terminal can adapt its operation based on said content during the rendering of said predetermined portion(s). Show less

A data processing system having a distributed reservation station is provided which stores basic blocks of code in the form of microprocessor instructions. The present invention is capable of distributing basic blocks of code to the various distributed reservation stations

A system and method is provided to reduce the latency associated with saving and restoring the state of the floating point registers in a microprocessor when switching tasks between floating point and MMX operations, or between tasks within the same context. The present invention maintains a secondary register file along with the primary floating point register file in the CPU. The primary register will keep the state of the floating point task “as is” upon the occurrence of a task switch to… Show more

A system and method is provided to reduce the latency associated with saving and restoring the state of the floating point registers in a microprocessor when switching tasks between floating point and MMX operations, or between tasks within the same context. The present invention maintains a secondary register file along with the primary floating point register file in the CPU. The primary register will keep the state of the floating point task “as is” upon the occurrence of a task switch to MMX, or another context. The address of the area where the FPU state is saved is maintained in a save area address register. The secondary register is then utilized by the other context to store intermediate results of executed instructions. In the majority of cases when a context switch back to floating point operations occurs, the previous state is restored from the primary register without incurring the latency of retrieving the instructions and data from the memory subsystem. In addition to the secondary register, a snooping mechanism will use the address of the state save area to determine if the state save area was modified. If the state save area is modified, then the floating point state must be restored from the memory subsystem in a conventional manner. However, the floating point save area will seldom be modified and the penalty for maintaining the floating point state in the CPU is negligible. Further, the present invention will allow the microprocessor to operate in a compatible manner with current operating systems and application software. Show less

The present invention utilizes a “virtual” condition code (VCC) which can control the instruction sequence in a microprocessor. The virtual condition code is stored in an internal, non-architected register that is not visible to the programmer, but is used by various microprocessor instructions.