Omkar Nageshkar

● Worked on multiple RO modules and support cells to remove DRC and LVS errors.
● Performed voltage threshold (VT) and gate length migration of RO modules and RO arrays from ULVT (ultra-low voltage) to LVT and SVT.
● Used SKILL scripting to automate layout modifications for multiple RO cells.
● Performed LPE and post layout simulations on all the migrated RO cells.

● Performed Layout Parasitic Extraction (LPE) on Ring Oscillator (RO) modules.
● Used the extracted files to perform post-layout simulations for different process corners for the RO modules.
● Used OCEAN scripting to automate the simulation process for different voltage corners.

● Explored different patterning technologies available and selected patterning technology for different layers of 7nm Standard Cells based on polygon size and complexity.
● Decomposed layers into different masks based on patterning technology selected.
● Modified the layout of standard cells to remove mask violations while making sure they remained DRC and LVS clean.
● Generated final layout by placing and routing the modified standard cells.
● Performed multiple iterations for… Show more

● Explored different patterning technologies available and selected patterning technology for different layers of 7nm Standard Cells based on polygon size and complexity.
● Decomposed layers into different masks based on patterning technology selected.
● Modified the layout of standard cells to remove mask violations while making sure they remained DRC and LVS clean.
● Generated final layout by placing and routing the modified standard cells.
● Performed multiple iterations for better area results. Show less

● Designed the functional blocks of the circuit for wiring channels of an FPGA, i.e. Switch Blocks, Connection Blocks, and Logic Blocks.
● Reported the delay, area and power performance.
● Minimized the delay, area and power by using different technologies for implementing the functionality of the blocks.

● Studied different IC technologies such as III-V, III-N devices and non volatile memory cells(NVM).
● Conducted a survey of different heterogeneous integration techniques implemented as a part of DARPA's COSMOS project.
● Studied the feasibility of integrating the different IC technologies on a single substrate.
● Proposed a design process to integrate GaN devices, InP DHBT, NVM and Si CMOS on single chip by taking into consideration the thermal budget, interconnection circuitry… Show more

● Studied different IC technologies such as III-V, III-N devices and non volatile memory cells(NVM).
● Conducted a survey of different heterogeneous integration techniques implemented as a part of DARPA's COSMOS project.
● Studied the feasibility of integrating the different IC technologies on a single substrate.
● Proposed a design process to integrate GaN devices, InP DHBT, NVM and Si CMOS on single chip by taking into consideration the thermal budget, interconnection circuitry, proximity and potential performance degradation.
● Developed a process flowchart for the proposed design process. Show less

● Designed and verified a Display Engine which receives several game objects with their types and coordinates and then displays the images on a 64x64 board in Verilog.
● Designed the functionality of the display engine and its interface with a frame buffer and 2 sprite ROMS.
● Verified the design to check if it was working according to specs provided.

● Designed and simulated a bulk NMOS transistor with gate length 18 nm to meet the ITRS specifications for ft (threshold frequency) and fmax (maximum frequency of oscillation) for the year 2015.
● Simulation of process steps was done using Synopsys TSUPREM and electrical simulation of the structure was done in Synopsys Medici.
● DC and RF characterization was performed and results were comparable to the target values.
● Results of simulated device were found comparable to target ITRS… Show more

● Designed and simulated a bulk NMOS transistor with gate length 18 nm to meet the ITRS specifications for ft (threshold frequency) and fmax (maximum frequency of oscillation) for the year 2015.
● Simulation of process steps was done using Synopsys TSUPREM and electrical simulation of the structure was done in Synopsys Medici.
● DC and RF characterization was performed and results were comparable to the target values.
● Results of simulated device were found comparable to target ITRS specifications for year 2015. Show less

■ Objective: Implementing circuits using multi-input gate MOSFETs to bring about reduction in transistor count and number of interconnections.
● Modelled MIFG MOSFET at device level and designed logic gates, combinational and sequential circuits using the model.
● Simulated circuits, performed power and delay analysis using T-Spice in Tanner EDA Tools.
● Designed layout of these circuits and calculated area in Tanner’s L-Edit.
● Compared performance and area with conventional MOS… Show more

■ Objective: Implementing circuits using multi-input gate MOSFETs to bring about reduction in transistor count and number of interconnections.
● Modelled MIFG MOSFET at device level and designed logic gates, combinational and sequential circuits using the model.
● Simulated circuits, performed power and delay analysis using T-Spice in Tanner EDA Tools.
● Designed layout of these circuits and calculated area in Tanner’s L-Edit.
● Compared performance and area with conventional MOS design.
● Results showed significant improvement in the number of transistors and area required for every logic gate and circuit designed as compared to their CMOS counterparts.
● Power dissipation also found to be better in MIFG based circuits.
● Designed 4-bit ALU with MIFG based circuits. Show less

● Designed logic gates, combinational circuits like ADC/DAC, multiplexers, multi-bit adders and multipliers, and sequential circuits like timers, counters and shift registers in Xilinx ISE using VHDL and Verilog .
● Implemented these designs on Spartan-3 FPGA development board using VLSI design flow.

● AVR ATmega1284 controller
● Sony Play Station-2 Controller interface
● Graphics LCD interface
● Game graphics and software development in Embedded C
(Snake Game, Road Rash, Flappy Bird)