Pedram Payandehnia

The design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator is presented. Using a customized digital integrator with inherent data-weighted averaging (DWA) at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad (SAB) structure in the loop filter, the number of op-amps is reduced, thus reducing the analog power consumption. Also, the… Show more

The design and implementation of a new blocker tolerant wideband continuous-time delta-sigma modulator is presented. Using a customized digital integrator with inherent data-weighted averaging (DWA) at the back-end of the modulator, the power consumption of the quantizer is reduced while the speed of operation is increased. Additionally, by using a single amplifier biquad (SAB) structure in the loop filter, the number of op-amps is reduced, thus reducing the analog power consumption. Also, the modulator robustness to the out-of-band blocker is improved by increasing the number of levels in the digital integrator and feedback DACs. The out-of-band blocker tolerance is improved by 3 dB compared to a conventional CIFF-B delta-sigma modulator with a minimal increase in the power consumption. The proposed architecture has been implemented in a 65-nm CMOS technology and operates at a 250 MHz sampling frequency. It achieves 73.5 dB SNR, 72.4 dB SNDR, and 92 dB SFDR over a 7 MHz bandwidth and a Walden Figure-of-Merit (FoM) of 341 fJ/conversion. Show less

A novel switched-capacitor low-pass filter architecture is presented. In the proposed scheme, a feedback path is added to a charge-rotating real-pole filter to implement
complex poles. The selectivity is enhanced, and the in-band loss is reduced compared with the real-pole filter. The output thermal noise level and the tuning range are both close to those of the real-pole filter. These features make the filter suitable for high speed, low
noise, and low power applications. A… Show more

A novel switched-capacitor low-pass filter architecture is presented. In the proposed scheme, a feedback path is added to a charge-rotating real-pole filter to implement
complex poles. The selectivity is enhanced, and the in-band loss is reduced compared with the real-pole filter. The output thermal noise level and the tuning range are both close to those of the real-pole filter. These features make the filter suitable for high speed, low
noise, and low power applications. A fourth-order filter prototype was implemented in a 180-nm CMOS technology. The measured in-band loss is reduced by 3.3 dB compared with that of a real-pole filter. The sampling rate of the filter is programmable from 65 to 300 MS/s with a constant dc gain. The 3-dB cut-off frequency of the filter can be tuned from 490 to 13.3 MHz with over 100-dB maximum stop-band rejection. The measured in-band third-order output intercept point is 28.7 dBm, and the averaged spot noise is 6.54 nV/√Hz. The filter consumes 4.3 mW from a 1.8 V supply. Show less

An opamp-free noise shaping successive-approximation register (SAR) ADC is proposed. Third-order noise shaping is achieved by implementing a second-order passive filter and a passive error feedback topology. In the proposed scheme, the SAR error signals (including quantisation noise, comparator thermal noise, DAC thermal noise and settling error) are subjected to third-order noise shaping. Therefore, the thermal noise specifications of the comparator can be relaxed. Also, since no active… Show more

An opamp-free noise shaping successive-approximation register (SAR) ADC is proposed. Third-order noise shaping is achieved by implementing a second-order passive filter and a passive error feedback topology. In the proposed scheme, the SAR error signals (including quantisation noise, comparator thermal noise, DAC thermal noise and settling error) are subjected to third-order noise shaping. Therefore, the thermal noise specifications of the comparator can be relaxed. Also, since no active element is used, the proposed scheme achieves a higher power efficiency than earlier SAR ADCs. Show less