Philipp Thomas

Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path, can be highly parallelized for higher sampling rates but are difficult to scale toward higher analog bandwidths. Thus, the hybrid integration of front-end circuits with the function of a bandwidth gearbox in other semiconductor technologies is an interesting research topic. In… Show more

Optical transceivers with more than 50 GBd are now being deployed, while the use of more than 100 GBd is currently under investigation. CMOS components, such as the analog-to-digital converter (ADC) in the receiver path, can be highly parallelized for higher sampling rates but are difficult to scale toward higher analog bandwidths. Thus, the hybrid integration of front-end circuits with the function of a bandwidth gearbox in other semiconductor technologies is an interesting research topic. In this article, we show an example of a time-interleaved analog demultiplexer (ADeMUX) with four track-and-hold (T/H) circuits based on switched emitter followers (SEFs) in a 90-nm silicon-germanium (SiGe)-Bipolar-CMOS (BiCMOS) technology for parallel operation of four CMOS ADCs. The 50% duty cycle of the clock signal facilitates its generation and can save power consumption in the clock path or enable higher sampling rates compared with the 25% duty-cycle clock of other ADeMUX architectures. We show that using switched preamplifiers in front of the SEFs can double the bandwidth of each T/H lane. Experimental verification shows up to 57-GHz input bandwidth while requiring only 16-GHz input bandwidth for each of the ADCs that can be connected to the four 32-GS/s output channels. The circuit achieves 3–6-bit accuracy and is suitable for 100-GBd signaling and beyond with pulse amplitude modulation. To demonstrate the capability of higher sampling rates, measurement results at 4 × 50 GS/s = 200 GS/s are provided as well although significant advancement of the measurement environment is needed for a complete evaluation. Show less

This paper presents the design and experimental results of a voltage mode analog demultiplexer (ADeMUX) that uses four time interleaved switched emitter follower track-and-hold (T/H) circuits. The preamplifiers and sampling cores are linearized for ultra-broadband operation. With the utilized 90-nm SiGe-BiCMOS technology offering 300 GHz fT and 480 GHz fmax, we are able to operate the ADeMUX with up to 4 x 50 GS/s = 200 GS/s – the highest reported sampling rate to date. Compared with the… Show more

This paper presents the design and experimental results of a voltage mode analog demultiplexer (ADeMUX) that uses four time interleaved switched emitter follower track-and-hold (T/H) circuits. The preamplifiers and sampling cores are linearized for ultra-broadband operation. With the utilized 90-nm SiGe-BiCMOS technology offering 300 GHz fT and 480 GHz fmax, we are able to operate the ADeMUX with up to 4 x 50 GS/s = 200 GS/s – the highest reported sampling rate to date. Compared with the state-of-the-art current mode ADeMUX circuits, the presented device offers an increase in sampling rate of more than 50%. At 128 GS/s, the chip shows the highest input bandwidth of more than 50 GHz and a linearity of more than 3 bit. This ultra-broadband analog time interleaver can be used to feed four analog-to-digital converters in CMOS technology, due to the reduced bandwidth requirement of only 16 GHz for operation at 128 GS/s or 25 GHz for 200 GS/s. Show less

Today’s ultra-wideband optical equipment enables fiber-based data links with up to 1.6 Tbit/s per wavelength at a symbol rate of 128 Gbaud. However, high input signal path losses need to be overcome in commercial products when the digitizers are integrated with the digital signal processor in a deep-submicrometer FinFET-CMOS transceiver application specific integrated circuit (ASIC). This currently limits the analog-to-digital converter (ADC) sampling rate and the detectable link symbol rate to… Show more

Today’s ultra-wideband optical equipment enables fiber-based data links with up to 1.6 Tbit/s per wavelength at a symbol rate of 128 Gbaud. However, high input signal path losses need to be overcome in commercial products when the digitizers are integrated with the digital signal processor in a deep-submicrometer FinFET-CMOS transceiver application specific integrated circuit (ASIC). This currently limits the analog-to-digital converter (ADC) sampling rate and the detectable link symbol rate to 97 GS/s and 66 Gbaud, respectively. Four of these bandwidth-limited ADCs can be time-interleaved with the presented analog 1-to-4 demultiplexer front end in a SiGe-BiCMOS technology that allows high bandwidths with transistor cutoff frequencies above 300 GHz. The sampling front end effectively divides the necessary ADC bandwidth by the time-interleaving factor, enabling the detection of ultra-high symbol rates of up to 128 Gbaud with only 16-GHz bandwidth requirement for the four ADCs. At these frequencies, subsequent circuits and chip interconnects exhibit significantly lower signal path losses than at 64 GHz—half the symbol rate—and therefore require only a reduced processing power for channel equalization in the analog and digital domain. We demonstrate sampling operation with a large-signal 3-dB bandwidth of 36 GHz and a 6-dB bandwidth of 50 GHz at 128 GS/s in an experimental testbed, as well as the reception of 128-Gbit/s NRZ/OOK and 256-Gbit/s PAM4 signals. The linearity reaches more than 3-bit effective number of bits (ENOB) with a sinusoidal input signal of 500 mV pp on each of the four output channels. The power consumption is equivalent to a sampling efficiency of 20 pJ/sample, narrowing the gap to slower CMOS solutions and enabling cost-efficient coherent optical links with up to 1 Tbit/s. Show less

Ultra-high speed and bandwidth ADCs are necessary for communication systems that apply spectral efficient modulation formats to achieve date rates of 100Gbit/s and beyond. These ADCs must have a high absolute input bandwidth, a high sampling speed and good linearity. A key component of these ADCs is the analog front-end section between the analog signal input and the quantizer. This contribution shows some different methods to implement such ultra-broadband ADC front-ends. The first method… Show more

Ultra-high speed and bandwidth ADCs are necessary for communication systems that apply spectral efficient modulation formats to achieve date rates of 100Gbit/s and beyond. These ADCs must have a high absolute input bandwidth, a high sampling speed and good linearity. A key component of these ADCs is the analog front-end section between the analog signal input and the quantizer. This contribution shows some different methods to implement such ultra-broadband ADC front-ends. The first method, suitable for medium-resolution ADCs, is to use a track-hold-less analog front-end with a high-bandwidth input transconductor and a travelling-wave structure for the comparators of the quantizer. This input structure ensures proper alignment between the signal and the clock at all comparators. The method is illustrated by a 40GS/s 4-bit single-core flash-type BiCMOS ADC. For higher resolution ADCs, a linear front-end track-hold circuit is necessary, which can be implemented using a voltage-mode or a current-mode approach. The voltage-mode approach is exemplified by a 12GS/s BiCMOS circuit with track-mode masking and high SFDR in the first and second Nyquist band. The current mode approach is shown by a 25GS/s BiCMOS circuit with a 1dB input bandwidth of 40GHz. To reach even higher sampling rates, the analog input samples can be de-interleaved to several quantizers by means of an analog demultiplexer (ADeMUX). This is illustrated by a current-mode 1-to-4 ADeMUX implemented in BiCMOS running at 112GS/s. Show less

Time-interleaving of energy-efficient data converter cores enables record symbol rates in electronic receivers. High-speed applications like optical data transmission or direct down-conversion in wireless mmWave receivers require ultra-high bandwidths and symbol rates, which CMOS data converters and especially their analog front ends cannot provide to date. We demonstrate a 64-GS/s track-and-hold circuit with a large-signal bandwidth of more than 61 GHz without any area-consuming peaking… Show more

Time-interleaving of energy-efficient data converter cores enables record symbol rates in electronic receivers. High-speed applications like optical data transmission or direct down-conversion in wireless mmWave receivers require ultra-high bandwidths and symbol rates, which CMOS data converters and especially their analog front ends cannot provide to date. We demonstrate a 64-GS/s track-and-hold circuit with a large-signal bandwidth of more than 61 GHz without any area-consuming peaking inductors, designed and manufactured in a 90-nm SiGe BiCMOS technology. The analog sampling front end exhibits a third harmonic distortion of -45 dBc to -32 dBc within the available frequency range of 50 GHz, which is better than the 5-bit requirement for 1.0-Vpp input signals. The ultra-high bandwidth of the circuit is twice as high as reported for CMOS data converters and in the range of broadband germanium photodiodes. This improves the bottleneck in hybrid integrated optoelectronic receiver front ends significantly. It is suited for time-interleaving of two channels with a doubled symbol rate of 128 GBaud, and the linearity allows to use it with 6–8-bit data converters. Show less

This paper presents a 116 GS/s analog demultiplexer front-end, sampling one differential input channel and routing it cyclically to 4 differential outputs at 29 GS/s each. With this topology, analog-to-digital converters can be time-interleaved to build a digitizing system with more than 100 GBaud, while keeping the necessary bandwidth under 15 GHz. Especially CMOS analog-to-digital converters benefit from this relaxed bandwidth requirement, which enables cost-efficient 116 GBaud silicon… Show more

This paper presents a 116 GS/s analog demultiplexer front-end, sampling one differential input channel and routing it cyclically to 4 differential outputs at 29 GS/s each. With this topology, analog-to-digital converters can be time-interleaved to build a digitizing system with more than 100 GBaud, while keeping the necessary bandwidth under 15 GHz. Especially CMOS analog-to-digital converters benefit from this relaxed bandwidth requirement, which enables cost-efficient 116 GBaud silicon receivers for optical communications and instrumentation. Show less

We demonstrate an ultra-wideband 32-GS/s SiGe track-and-hold amplifier with 58-GHz bandwidth and a compact footprint due to the inductorless design. The circuit achieves a third harmonic distortion of -64 dBc to -29 dBc at 1.0-Vpp differential input voltage swing thanks to a linearized switched preamplifier and switched emitter follower stage. It can be especially interesting for direct-conversion 5G mmWave and radar receivers, or systems with a time-interleaving factor of up to 4, as the… Show more

We demonstrate an ultra-wideband 32-GS/s SiGe track-and-hold amplifier with 58-GHz bandwidth and a compact footprint due to the inductorless design. The circuit achieves a third harmonic distortion of -64 dBc to -29 dBc at 1.0-Vpp differential input voltage swing thanks to a linearized switched preamplifier and switched emitter follower stage. It can be especially interesting for direct-conversion 5G mmWave and radar receivers, or systems with a time-interleaving factor of up to 4, as the ultra-high bandwidth spans almost 4 Nyquist bands and covers all designated 5G mmWave frequencies. Show less

Coherent optical transceivers cover multiple wavelengths to meet the growing request for ultra-wideband data links, e.g. from ultra-high definition video-on-demand. However, costs increase with the number of wavelengths per channel, so that higher baud rates are used to reduce the receiver’s complexity, while simultaneously increasing electrical bandwidth requirements. Especially sampling rate and analog input bandwidth between photodiode and data converters need to be improved. For that… Show more

Coherent optical transceivers cover multiple wavelengths to meet the growing request for ultra-wideband data links, e.g. from ultra-high definition video-on-demand. However, costs increase with the number of wavelengths per channel, so that higher baud rates are used to reduce the receiver’s complexity, while simultaneously increasing electrical bandwidth requirements. Especially sampling rate and analog input bandwidth between photodiode and data converters need to be improved. For that purpose, we present a 4-way time-interleaving analog demultiplexer in one of the most advanced
SiGe-BiCMOS technologies to date, operating at the highest reported sampling rate of 128 GS/s. The total harmonic distortion of -37 to -22 dB indicates an accuracy of 5.9–3.3 ENOB(THD) across the entire 36-GHz bandwidth of the sampled signal path and the signal-to-noise ratio of 28 dB at 2 GHz enables 4.4 ENOB(SNR). Each of the sampling front end’s four output paths can drive a 32-GS/s 6-bit analog-to-digital converter that can be connected to commercially available 32-Gbit/s digital interfaces. Combining an ultra-high symbol rate with medium accuracy allows for a data rate beyond 1 Tbit/s per wavelength with dual polarization and quadrature amplitude modulation in a cost-efficient coherent optical receiver. Show less

High-speed analog-to-digital (ADC) and digital-to-analog converters (DAC) are key components for the core data network. As network traffic is still growing at an enormous rate, ultra-broadband converters are of uttermost importance. Especially the analog front-end section of these converters, i.e. the analog input of ADCs and the analog output of DACs, imposes severe challenges on the circuit design. SiGe-BiCMOS the technology of choice for the implementation of the these analog front ends… Show more

High-speed analog-to-digital (ADC) and digital-to-analog converters (DAC) are key components for the core data network. As network traffic is still growing at an enormous rate, ultra-broadband converters are of uttermost importance. Especially the analog front-end section of these converters, i.e. the analog input of ADCs and the analog output of DACs, imposes severe challenges on the circuit design. SiGe-BiCMOS the technology of choice for the implementation of the these analog front ends, because SiGe bipolar transistors offer both extremely high cutoff frequencies needed for the converter bandwidth as well as large scale integration capability as needed for the complex converter circuitry. The EU/ECSEL project TARANTO does research on both the device speed enhancement as well as on advanced circuit topologies and designs for ultra-broadband analog front-end circuits for AD and DA conversion.
This presentation will present solutions for implementing ultra-broadband ADC and DAC front-ends and discuss the main challenges for the corresponding circuit design. We will show practical circuit designs realized in TARANTO by URM1, USTUTT, USAAR and MICRAM as well as a test setup from NOKIA. For the data link receiver, we present very broadband SiGe BiCMOS analog front-end circuits for synchronous (STI) and asynchronous (ATI) time interleaving of AD converters. The STI front-end applies current mode integrating samplers whereas the ATI front-end applies mixers and filters. For the data link transmitter, an ultra-high-speed single-core SiGe BiCMOS DAC core will be shown. Moreover, we introduce the concept of D/A time interleaving with analog multiplexer circuits. Finally, we present a testbed for the test of a STI ADC front-end. Show less

This paper presents a track-and-hold amplifier based on a switched emitter follower with demonstrated sampling rates from 6.4 GS/s to 32 GS/s and an analog bandwidth of up to 19 GHz in the hold-mode. Linearity measurements in the first Nyquist zone show 4.9 – 7.9 bits of accuracy for the highest sampling rate, more than 6 bits for up to 25.6 GS/s, more than 7 bits for up to 12.8 GS/s and a maximum of 8.9 bits at 6.4 GS/s, all calculated from the SNDR values. Most comparable circuits use only… Show more

This paper presents a track-and-hold amplifier based on a switched emitter follower with demonstrated sampling rates from 6.4 GS/s to 32 GS/s and an analog bandwidth of up to 19 GHz in the hold-mode. Linearity measurements in the first Nyquist zone show 4.9 – 7.9 bits of accuracy for the highest sampling rate, more than 6 bits for up to 25.6 GS/s, more than 7 bits for up to 12.8 GS/s and a maximum of 8.9 bits at 6.4 GS/s, all calculated from the SNDR values. Most comparable circuits use only the THD value to calculate ENOBs, since achieving high SNR is difficult for low signal power circuits. The measurement results of the proposed track-and-hold amplifier were obtained at a high differential input voltage swing of 2.0 Vpp while they can reach even higher values at 1.0 Vpp. The 1-dB compression point is even higher, at 18.9 dBm. This makes the circuit suitable for high signal or noise power applications that demand high data rates and high linearity at the same time, including radio frequency instrumentation and receivers in radar and satellite communications. Designed as the front-end of a folding ADC, an additional benefit is the track-mode masking, recovering the common-mode level of the outputs during the input track-mode, which can be important when working with high input voltages. The third-order intercept point of 27.4 dBm at 25.6 GS/s and up to 34.7 dBm at 6.4 GS/s shows the unique combination of high signal power and high linearity in a sampling circuit above 10 GHz. This is made possible by the modern 55 nm SiGe-BiCMOS technology with high-performance HBTs. Show less

A pipelined folding-interpolating analog-to-digital converter (ADC) with a distributed quantizer is presented. The mismatch-insensitive analog frontend provides excellent spurious-free dynamic range (SFDR) and signal-to-noise ratio without calibration or digital postprocessing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves an effective resolution of 7.3 b and an SFDR of 52.7 dBc in the second… Show more

A pipelined folding-interpolating analog-to-digital converter (ADC) with a distributed quantizer is presented. The mismatch-insensitive analog frontend provides excellent spurious-free dynamic range (SFDR) and signal-to-noise ratio without calibration or digital postprocessing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves an effective resolution of 7.3 b and an SFDR of 52.7 dBc in the second Nyquist band at 6 GS/s with an overall power consumption of 10.2 W. Show less

A pipelined folding-interpolating ADC with a distributed quantizer is presented. The low-mismatch analog frontend provides for excellent SFDR and SNDR without calibration or digital post processing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves 7.3 ENOB and a SFDR of 52.7 dBc in the 2nd Nyquist band at 6 GS/s with an overall power consumption of 10.2 W.