About
I’m a computer scientist and hardware engineer working for the AI chip company Groq in…
Articles by Satnam
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Abuse and Bullying in the Workplace: An Ad Hoc Personal Survival Guide
Abuse and Bullying in the Workplace: An Ad Hoc Personal Survival Guide
By Satnam Singh
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Why I loved my first in-person professional meeting in years
Why I loved my first in-person professional meeting in years
By Satnam Singh
Activity
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Optimizing ML models without compromising accuracy is hard! I'm excited to share recent research I've been involved in during my free time with…
Optimizing ML models without compromising accuracy is hard! I'm excited to share recent research I've been involved in during my free time with…
Liked by Satnam Singh
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We're thrilled to collaborate again with Stanford University on their LLM x Law Hackathon on Sept 8. As always, we'll be increasing rates for all…
We're thrilled to collaborate again with Stanford University on their LLM x Law Hackathon on Sept 8. As always, we'll be increasing rates for all…
Liked by Satnam Singh
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My first job out of Stanford was as a founding CEO of a small tech startup. It was an exciting time, we were building some world changing products…
My first job out of Stanford was as a founding CEO of a small tech startup. It was an exciting time, we were building some world changing products…
Liked by Satnam Singh
Experience
Education
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The University of Glasgow
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Non-standard interpretation of functional hardware descriptions (in Miranda) for testability analysis. Advisor: Mary Sheeran (now a professor at Chalmers).
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Subjects studied include physics, mathematics, computing and electrical engineering.
Licenses & Certifications
Publications
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Resource bounded multicore emulation using Beefarm
Journal of Microprocessors and Microsystems
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An Analysis of Programmer Productivity versus Performance for High Level Data Parallel Programming
Communicating Processor Architectures, Elsevier
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The RLOC is Dead -- Long Live the RLOC
ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2011), ACM
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Design and Verification of Peripheral Control Circuits in Esterel
Journal of Concurrency and Computation: Practice and Experience, Wiley, 2009
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Exploiting System-Level Concurrency Abstractions for Hardware Descriptions
Microsoft Technical Report number MSR-TR-2009-48
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A Bluespec Implementation of an FPGA-based Photoshop Plug-In
Hardware Design and Functional Languages 2009 (FDL)
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A Tutorial on Parallel and Concurrent Programming in Haskell
Advanced Functional Programming Summer School 2009. LNCS.
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Using C# Attributes to Describe Hardware Artefacts within Kiwi
Forum on Design Languages (FDL). 2008
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A Deterministic Multi-Way Rendezvous Library for Haskell
IEEE International Parallel and Distributed Processing Symposium (IPDPS 2008)
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New Parallel Programming Techniques for Hardware Design
WG 10.5 International Conference on Very Large Scale Integration
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Hardware/Software Synthesis and Verification using Esterel.
The 30th Communicating Process Architectures Conference, CPA 2007
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Declarative Programming Techniques for Many-Core Architecture
Hardware Design and Functional Languages (HDFL 2007).
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Integrating FPGAs in High-Performance Computing: Programming Models for Parallel Systems – The Programmer’s Perspective
CM/SIGA International Symposium on Field Programmable Gate Arrays (FPGA), ACM.
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Higher Order Combinators for Join Patterns using STM
irst ACM SIGPLAN Workshop on Languages, Compilers, and Hardware Support for Transactional Computing (TRANSCAT)
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An Asynchronous Messaging Library for C#
Synchronization and Coordination in Object Orientated Languages (OOPSLA workshop)
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A Demonstration of Co-Design and Co-Verification in a Synchronous Languages
Design, Automation and Test in Europe (DATE 2004). IEEE.
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System Level Design and Verification Using a Synchronous Language
The International Conference on Computer Aided Design (ICCAD 2003). IEEE
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Design and Verification of CoreConnect IP using Esterel
The 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME 2003), Springer-Verlag
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System Level Specification in Lava
Design, Automation and Test in Europe (DATE 2003), IEEE
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Types for Describing Dynamic Reconfiguration
The International Conference on Computer Aided Design (ICCAD 2002), IEEE.
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Checking safety properties using induction and a SAT-solver.
Formal Methods in Computer Aided Design (FMCAD 200). Springer-Verlag LNCS.
We take a fresh look at the problem of how to check safety properties of finite state machines. We are particularly interested in checking safety properties with the help of a SAT-solver. We describe some novel induction-based methods, and show how they are related to more standard fixpoint algorithms for invariance checking. We also present preliminary experimental results in the verification of FPGA cores. This demonstrates the practicality of combining a SAT-solver with induction for safety…
We take a fresh look at the problem of how to check safety properties of finite state machines. We are particularly interested in checking safety properties with the help of a SAT-solver. We describe some novel induction-based methods, and show how they are related to more standard fixpoint algorithms for invariance checking. We also present preliminary experimental results in the verification of FPGA cores. This demonstrates the practicality of combining a SAT-solver with induction for safety property checking of hardware in a real design flow.
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Photoshop Acceleration using Virtex
Field Programmable Logic 1999 (FPL'99). Springer-Verlag LNCS.
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Rendering PostScript™ Fonts on FPGAs
Field Programmable Logic 1999 (FPL'99). Springer-Verlag LNCS.
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Bezier Curve Rendering on Virtex™
Field-Programmable Custom Computing Machines (FCCM 1999). ACM
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Formal Verification of FPGA Cores
Nordic Journal of Computing. ACM
A formal verification technique is presented which is suitable for the verification of standard components (cores) for programmable hardware (FPGAs). This technique can be viewed as a suitable complement to traditional techniques, such as simulation. We describe the modeling and verification of combinational and sequential components using the formal verification tool NP-Tools, and report successful verification of real cores.
Other authorsSee publication -
Accelerating DTP with Reconfigurable Computing Engines
Field Programmable Logic 1998 (FPL 1998). Springer-Verlag LNCS.
This paper describes how a reconfigurable computing engine can be used to accelerate DTP functions. We show how PostScript rendering can be accelerated using a commercially available FPGA co-processor card. Our method relies on dynamically swapping in pre-computed circuits to accelerate the compute intensive portions of PostScript rendering.
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Dynamic Specialisation of XC6200 FPGAs by Partial Evaluation
Filed Programmable Logic (FPL 98). Springer-Verlag LNCS.
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Applications of Run-Time Specialisation for FPGAs
Field-Programmable Logic and Applications 1998 (FPL'98). Springer-Verlag LNCS.
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Accelerating Adobe Photoshop with Reconfigurable Logic
FPGAs for Custom Computing Machines, 1998 (FCCM '98). IEEE.
This paper presents the results of a project designed to produce a commercial application for reconfigurable logic. We describe how we took the popular image processing application Adobe Photoshop and used its plug-in technology to devise a set of FPGA-based filters to accelerate colour space conversion and image convolution operations. Some of the barriers that make it difficult to produce portable FPGA-based filters are explored.
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Dynamic Specialisation of XC6200 FPGAs by Partial Evaluation
FPGAs for Custom Computing Machines, 1998. IEEE
We describe preliminary results of dynamically specialising Xilinx XC6200 FPGA circuits using the partial evaluation method. This method provides a systematic way to manage the complexity of dynamic reconfiguration in the special case where a general circuit is specialised with respect to a slowly changing input. We describe how we address the verification and run-time support issues which are raised when one modifies a circuit at run-time.
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Partial Evaluation of Hardware
Partial Evaluation Summer School . Springer-Verlag LNCS.
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A Dynamic Reconfiguration Run-Time System
Filed Programmable Custom Computing Machines (FCCM 1997). IEEE Computer Society Press.
The feasibility of run-time reconfiguration of FPGAs has been established by a large number of case studies. However, these systems have typically involved an ad hoc combination of hardware and software. The software that manages the dynamic reconfiguration is typically specialized to one application and one hardware configuration. We present three different applications of dynamic reconfiguration, based on research activities at Glasgow University, and extract a set of common requirements. We…
The feasibility of run-time reconfiguration of FPGAs has been established by a large number of case studies. However, these systems have typically involved an ad hoc combination of hardware and software. The software that manages the dynamic reconfiguration is typically specialized to one application and one hardware configuration. We present three different applications of dynamic reconfiguration, based on research activities at Glasgow University, and extract a set of common requirements. We present the design of an extensible run-time system for managing the dynamic reconfiguration of FPGAs, motivated by these requirements. The system is called RAGE, and incorporates operating-system style services that permit sophisticated and high level operations on circuits.
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Expressing Dynamic Reconfiguration by Partial Evaluation
FPGAs for Custom Computing Machines (FCCM 1996). IEEE Computer Society Press.
Dynamic reconfiguration of FPGAs is a powerful technique for modifying a circuit as it executes. However, dynamic reconfiguration is inadequately supported by CAD tools and poorly understood in general. We present a specific class of dynamic reconfigurations that can be expressed in terms of a formalism called partial evaluation. This provides a systematic framework for understanding the effect of a dynamic reconfiguration, as well as providing guidance on how to complete specialised circuits…
Dynamic reconfiguration of FPGAs is a powerful technique for modifying a circuit as it executes. However, dynamic reconfiguration is inadequately supported by CAD tools and poorly understood in general. We present a specific class of dynamic reconfigurations that can be expressed in terms of a formalism called partial evaluation. This provides a systematic framework for understanding the effect of a dynamic reconfiguration, as well as providing guidance on how to complete specialised circuits. The primary advantages of this technique are circuits which are smaller and faster for a certain class of applications. We present one case study from the ATM field which benefits from this treatment.
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Ruby as a basis for Hardware/Software Co-Design
IEE Symposium on Hardware/Software Co-Design
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Architectural Descriptions for FPGAs
IEEE Symposium on FPGAs for Custom Computing Machines 1995
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Accelerating Graphics using FPGAs
Canadian Workshop on Field-Programmable Devices
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Designing Graphical User Interfaces for Haskell
Glasgow Functional Programming Workshop, Ayr. Springer-Verlag
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Hardware Synthesis Techniques for Algebraic HDLs
Synthesis And System Integration of Mixed Information technologies. SASIMI.
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Circuit Analysis by Non-Standard Interpretation
Second IFIP WG10.2/WG10.5 Workshop on Designing Correct Circuits, Springer-Verlag.
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An X11/XView Interpreter for Miranda
Glasgow Functional Programming Workshop, Portree. Springer-Verlag 1991.
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Analysis of Hardware Descriptions
University of Glasgow. 1991. PhD Thesis.
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Circuit Layout using NSI
Advanced Research Workshop on Correct Hardware Design Methodologies. Turin. North-Holland 1991
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Differentiating Strictness
Glasgow Functional Programming Workshop, Ullapool. Springer-Verlag 1990
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Application of Non-Standard Interpretation: Testability. Design of Correct VLSI Circuits
Proc. IFIP-IMEC Workshop, Belgium. North Holland 1989
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Implementation of a Non-Standard Interpretation System
Glasgow Functional Programming Workshop, Fraserburgh. Springer-Verlag
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Death of the RLOC?
Field-Programmable Custom Computing Machines, 2000 (FCCM 200). IEEE.
“RLOC” is the name given to a relational placement macro that is used to influence the layout of circuits that are realised on FPGAs using Xilinx's place and route software. This paper explores the thesis that modern FPGA architectures are powerful enough to no longer require the designer to provide a layout and that simulated annealing technology has advanced to the point that very good results can be obtained using no layout constraints at all. If this thesis is true then there is a profound…
“RLOC” is the name given to a relational placement macro that is used to influence the layout of circuits that are realised on FPGAs using Xilinx's place and route software. This paper explores the thesis that modern FPGA architectures are powerful enough to no longer require the designer to provide a layout and that simulated annealing technology has advanced to the point that very good results can be obtained using no layout constraints at all. If this thesis is true then there is a profound effect on custom computing machines which can be more easily targeted from high level specification languages like Handle-C and JHDL without requiring clumsy layout information to be accommodated at the language level.
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Debugging Techniques for Dynamically Reconfigurable Hardware
FPGAs for Custom Computing Machines (FCCM 1999). IEEE Computer Society.
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Formal Verification of Reconfigurable Cores
Field-Programmable Custom Computing Machines (FCCM 1999). IEEE
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Lava: Hardware Design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming (ICFP 1998). ACM.
Lava is a tool to assist circuit designers in specifying, designing, verifying and implementing hardware. It is a collection of Haskell modules. The system design exploits functional programming language features, such as monads and type classes, to provide multiple interpretations of circuit descriptions. These interpretations implement standard circuit analyses such as simulation, formal verification and the generation of code for the production of real circuits.Lava also uses polymorphism…
Lava is a tool to assist circuit designers in specifying, designing, verifying and implementing hardware. It is a collection of Haskell modules. The system design exploits functional programming language features, such as monads and type classes, to provide multiple interpretations of circuit descriptions. These interpretations implement standard circuit analyses such as simulation, formal verification and the generation of code for the production of real circuits.Lava also uses polymorphism and higher order functions to provide more abstract and general descriptions than are possible in traditional hardware description languages. Two Fast Fourier Transform circuit examples illustrate this.
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Virtual Hardware for Graphics Applications using FPGAs
FCCM'94. Napa, California. IEEE Computer Society Press
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Projects
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Lava: An embedded HDL for FPGA circuits with layout
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I developed an embedded hardware description language called Lava to help produce FPGA circuits where every component is deterministically placed by the HDL code. This permitted much more compact and faster circuits than was possible using other techniques. The system was implemented using the Haskell functional language. Examples of circuits implemented with Lava include constant coefficient multipliers, convolvers and network sorters (e.g. Batchers bitonic sorter). More information at…
I developed an embedded hardware description language called Lava to help produce FPGA circuits where every component is deterministically placed by the HDL code. This permitted much more compact and faster circuits than was possible using other techniques. The system was implemented using the Haskell functional language. Examples of circuits implemented with Lava include constant coefficient multipliers, convolvers and network sorters (e.g. Batchers bitonic sorter). More information at http://raintown.org/lava
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Teaching at the University of Glasgow
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In all my teaching activities I strive to excite students by relating the academic principals of computing science to real-world applications. When I taught the first year programming course at Glasgow, I developed a set of programming exercises that required students to generate drawings as PDF files that exploited the work in my FPGA/Postscript research project. Similarly, teaching the low level aspects of hardware interfacing in Ada in the Real-Time Systems 3 course led me to adopt Ada as…
In all my teaching activities I strive to excite students by relating the academic principals of computing science to real-world applications. When I taught the first year programming course at Glasgow, I developed a set of programming exercises that required students to generate drawings as PDF files that exploited the work in my FPGA/Postscript research project. Similarly, teaching the low level aspects of hardware interfacing in Ada in the Real-Time Systems 3 course led me to adopt Ada as the language for controlling FPGA hardware. I often find that not only does research feed into teaching, but teaching experience also feeds into research.
In the final year computer architecture course that I taught, I made extensive use of articles from Byte Magazine, Communications of the ACM and IEEE Computer that described the latest innovations e.g. new PCI graphics cards, the latest PowerPC processors or the new MMX technology for the Pentium series of microprocessors. This course required students to design hardware using the industry standard hardware description language VHDL.
I have taught a second year software engineering course to about 70 students which presented basic data structures like lists and trees as well as software engineering process principals such as testing and documentation. For this course I devised a challenging set of practical exercises e.g. a rudimentary system for translating English to French.
I am very concerned about developing the communication skills of students. The advanced courses I taught required students to read papers, and students were given an opportunity to present a paper to the entire class. I often asked students for technical information or their opinion of some language feature or algorithm during lectures. I am always seeking new ways to enhance the lecture mode of communication.
I taught a course on VLSI Testing at the University of Washington when I worked for Microsoft in Redmond. -
PhD Research
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My PhD research program was directed by Prof. Mary Sheeran and was in the area of software engineering methodologies for the development of VLSI Computer Aided Design (CAD) compilers and tools. This included the development of a semantics-driven framework for systematically deriving circuit analysis software from formal descriptions using a technique called non-standard interpretation. The technique allows complex circuit analyses to be systematically composed out of simpler analyses. One of…
My PhD research program was directed by Prof. Mary Sheeran and was in the area of software engineering methodologies for the development of VLSI Computer Aided Design (CAD) compilers and tools. This included the development of a semantics-driven framework for systematically deriving circuit analysis software from formal descriptions using a technique called non-standard interpretation. The technique allows complex circuit analyses to be systematically composed out of simpler analyses. One of the results of this technique was a software engineering methodology for developing VLSI CAD tools which reuses code in a controlled manner. Several circuit analyses were successfully implemented including circuit simulation, symbolic evaluation, circuit layout, testability analysis and test pattern generation.
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A Compiler for the Dynamic Synthesis of Correct Hardware
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This EPSRC project was funded in conjunction with the UK Defence Research Agency. Its duration was two years. We employed one research assistant and one masters student on this project. This project implemented a more sophisticated kind of dynamic reconfiguration where an existing circuit is modified at run- time by rippling through the effects of known inputs to simplify gates.
In this project we described circuits that are specialised at run-time when part of the input is known. For…This EPSRC project was funded in conjunction with the UK Defence Research Agency. Its duration was two years. We employed one research assistant and one masters student on this project. This project implemented a more sophisticated kind of dynamic reconfiguration where an existing circuit is modified at run- time by rippling through the effects of known inputs to simplify gates.
In this project we described circuits that are specialised at run-time when part of the input is known. For example, a general decryption circuit could be specialised to a decryption circuit for a particular key. This requires a run- time cost to calculate the specialised circuit from the general circuit once the key is known. However, the specialised circuit can be run much faster and takes up less room. If there is a large amount of data to decrypt then a substantial speed-up can be expected from the specialised circuit. I called this technique partial evaluation of hardware and this is a term which has become well known in the FPGA applications field. We researched and developed compiler technology for performing such optimizations in a dynamic hardware context and used a theorem prover to verify the correctness of the compilation process.
The results of this project can be deployed in actual communication systems like ATM switches, which have to service large amounts of data so any optimisation of the hardware is very worthwhile, or in software radio systems that require infrequent protocol modifications. -
A PostScript Compiler Engine based on FPGA Hardware
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This project was funded by EPSRC which is a UK research funding organization. It started on 1 June 1996 and its duration was 3 years. This project implemented dynamic reconfiguration where one sub-circuit is completely replaced by another sub-circuit. The deliverable of the project was an FPGA-based system to accelerate the rendering of PostScript jobs. The FPGA hardware performs the basic PostScript drawing operations. For output to a screen this may result in only modest speed-ups, but for…
This project was funded by EPSRC which is a UK research funding organization. It started on 1 June 1996 and its duration was 3 years. This project implemented dynamic reconfiguration where one sub-circuit is completely replaced by another sub-circuit. The deliverable of the project was an FPGA-based system to accelerate the rendering of PostScript jobs. The FPGA hardware performs the basic PostScript drawing operations. For output to a screen this may result in only modest speed-ups, but for full color production quality jobs at thousands of dots per inch we demonstrated a significant speed-up. By comparison, conventional approaches involve using a dedicated personal computer and often require many hours of processing to produce only a few pages.
The research results of the product involved the implementation and refinement of the virtual hardware concept that I first presented at the FCCM’94 conference for the implementation of 3D graphics algorithms on FPGAs. This technique allows circuits to be rapidly swapped into and out of FPGAs in a similar manner to that in which pages are swapped in a virtual memory system. This allows a large circuit to be realised on a small resource by only swapping in the portion of that circuit required at any particular instant. For example, when rendering lines, only the line rasteriser circuit needs to be realised on the FPGA. When a circle then needs to be drawn, the line circuit is over-written with a circle circuit. This method is essential for the realisation of a complex circuit for rasterising PostScript drawing operations on FPGAs which have very limited hardware resources. -
Professional Duties
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I have been the program chair, general chair and finance chair of several conferences including MEMOCODE, FPGA, FPL and FCCM. I have been a special edition editor of the Journal of Functional Programming and I am an associate editor of the ACM journal Transactions on Embedded Computing Systems. I have served on several NSF panels as I have also reviewed for EPSRC and the EU. I have been elected to the ACM SIGPLAN executive committee (from June 2015 for 3 years) which is ACM special interest…
I have been the program chair, general chair and finance chair of several conferences including MEMOCODE, FPGA, FPL and FCCM. I have been a special edition editor of the Journal of Functional Programming and I am an associate editor of the ACM journal Transactions on Embedded Computing Systems. I have served on several NSF panels as I have also reviewed for EPSRC and the EU. I have been elected to the ACM SIGPLAN executive committee (from June 2015 for 3 years) which is ACM special interest group in programming languages.
I have served on program committees for many conferences including ICFPT, FPGAs for Custom Computing Machines (FCCM), FPGA, Formal Methods for Computer Aided Design (FMCAD), FPL, FPT, MEMOCODE, HFL, DAMP, Designing Correct Circuits (DCC), The Haskell ACM Symposium and well as several other conferences and workshops. I have also served on the program committee for the Design Automation and Test in Europe (DATE) conference and the System-on-Chip conference and I chaired this track for three years. I currently serve on the PC for the DATE track on Architectural Synthesis. I have also reviewed many conference papers and journal articles. For example I have reviewed for the IEEE Transactions on VLSI, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the journal of Tools and Algorithms for the Construction and Analysis of Systems (TACAS), the Journal of Functional Programming, the Journal of VLSI Signal Processing on Reconfigurable Computing, the IEE Proceedings for Computers and Digital Techniques, the International Journal on Software Tools for Technology Transfer and the (British) Computer Journal.
Languages
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English
Native or bilingual proficiency
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Punjabi
Native or bilingual proficiency
Organizations
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ACM SIGPLAN (special interest group on programming languages)
Executive Member at Large
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ACM
Senior Member
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IEEE
Senior Member
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IET
Fellow
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IFIP WG.211 (Program Generation)
Elected Member
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IFIP WG2.8 (Functional Programming)
Elected Member
More activity by Satnam
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– Automated program repair and techniques presented in this thesis can help cut down the time we spend on debugging, making software development more…
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I have written a brief accessible introduction to the latest paper Marta Andronic and I have written, NeuraLUT, on hiding neural network complexity…
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You'd think from much of the buzzy tech-industry discussion that the future of programming is opaque machine-learning models writing whole programs…
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Mike's work on the VIPER processor verification was a huge early influence on me, a greatly inspiring researcher and a wonderful gentleman.
Mike's work on the VIPER processor verification was a huge early influence on me, a greatly inspiring researcher and a wonderful gentleman.
Shared by Satnam Singh
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One final BigQuery announcement for the time being. The time series functions and RANGE type are now GA. Curious to learn more? You can check out the…
One final BigQuery announcement for the time being. The time series functions and RANGE type are now GA. Curious to learn more? You can check out the…
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A great opportunity - bring the Best in British startups
A great opportunity - bring the Best in British startups
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Another day, another launch! This time it is a pair of helpful features for interacting with BigQuery's JSON type. First, we have JSON_KEYS…
Another day, another launch! This time it is a pair of helpful features for interacting with BigQuery's JSON type. First, we have JSON_KEYS…
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