Satnam Singh

I developed an embedded hardware description language called Lava to help produce FPGA circuits where every component is deterministically placed by the HDL code. This permitted much more compact and faster circuits than was possible using other techniques. The system was implemented using the Haskell functional language. Examples of circuits implemented with Lava include constant coefficient multipliers, convolvers and network sorters (e.g. Batchers bitonic sorter). More information at… Show more

I developed an embedded hardware description language called Lava to help produce FPGA circuits where every component is deterministically placed by the HDL code. This permitted much more compact and faster circuits than was possible using other techniques. The system was implemented using the Haskell functional language. Examples of circuits implemented with Lava include constant coefficient multipliers, convolvers and network sorters (e.g. Batchers bitonic sorter). More information at http://raintown.org/lava Show less

In all my teaching activities I strive to excite students by relating the academic principals of computing science to real-world applications. When I taught the first year programming course at Glasgow, I developed a set of programming exercises that required students to generate drawings as PDF files that exploited the work in my FPGA/Postscript research project. Similarly, teaching the low level aspects of hardware interfacing in Ada in the Real-Time Systems 3 course led me to adopt Ada as… Show more

In all my teaching activities I strive to excite students by relating the academic principals of computing science to real-world applications. When I taught the first year programming course at Glasgow, I developed a set of programming exercises that required students to generate drawings as PDF files that exploited the work in my FPGA/Postscript research project. Similarly, teaching the low level aspects of hardware interfacing in Ada in the Real-Time Systems 3 course led me to adopt Ada as the language for controlling FPGA hardware. I often find that not only does research feed into teaching, but teaching experience also feeds into research.
In the final year computer architecture course that I taught, I made extensive use of articles from Byte Magazine, Communications of the ACM and IEEE Computer that described the latest innovations e.g. new PCI graphics cards, the latest PowerPC processors or the new MMX technology for the Pentium series of microprocessors. This course required students to design hardware using the industry standard hardware description language VHDL.
I have taught a second year software engineering course to about 70 students which presented basic data structures like lists and trees as well as software engineering process principals such as testing and documentation. For this course I devised a challenging set of practical exercises e.g. a rudimentary system for translating English to French.
I am very concerned about developing the communication skills of students. The advanced courses I taught required students to read papers, and students were given an opportunity to present a paper to the entire class. I often asked students for technical information or their opinion of some language feature or algorithm during lectures. I am always seeking new ways to enhance the lecture mode of communication.
I taught a course on VLSI Testing at the University of Washington when I worked for Microsoft in Redmond. Show less

My PhD research program was directed by Prof. Mary Sheeran and was in the area of software engineering methodologies for the development of VLSI Computer Aided Design (CAD) compilers and tools. This included the development of a semantics-driven framework for systematically deriving circuit analysis software from formal descriptions using a technique called non-standard interpretation. The technique allows complex circuit analyses to be systematically composed out of simpler analyses. One of… Show more

My PhD research program was directed by Prof. Mary Sheeran and was in the area of software engineering methodologies for the development of VLSI Computer Aided Design (CAD) compilers and tools. This included the development of a semantics-driven framework for systematically deriving circuit analysis software from formal descriptions using a technique called non-standard interpretation. The technique allows complex circuit analyses to be systematically composed out of simpler analyses. One of the results of this technique was a software engineering methodology for developing VLSI CAD tools which reuses code in a controlled manner. Several circuit analyses were successfully implemented including circuit simulation, symbolic evaluation, circuit layout, testability analysis and test pattern generation. Show less

This EPSRC project was funded in conjunction with the UK Defence Research Agency. Its duration was two years. We employed one research assistant and one masters student on this project. This project implemented a more sophisticated kind of dynamic reconfiguration where an existing circuit is modified at run- time by rippling through the effects of known inputs to simplify gates.
In this project we described circuits that are specialised at run-time when part of the input is known. For… Show more

This EPSRC project was funded in conjunction with the UK Defence Research Agency. Its duration was two years. We employed one research assistant and one masters student on this project. This project implemented a more sophisticated kind of dynamic reconfiguration where an existing circuit is modified at run- time by rippling through the effects of known inputs to simplify gates.
In this project we described circuits that are specialised at run-time when part of the input is known. For example, a general decryption circuit could be specialised to a decryption circuit for a particular key. This requires a run- time cost to calculate the specialised circuit from the general circuit once the key is known. However, the specialised circuit can be run much faster and takes up less room. If there is a large amount of data to decrypt then a substantial speed-up can be expected from the specialised circuit. I called this technique partial evaluation of hardware and this is a term which has become well known in the FPGA applications field. We researched and developed compiler technology for performing such optimizations in a dynamic hardware context and used a theorem prover to verify the correctness of the compilation process.
The results of this project can be deployed in actual communication systems like ATM switches, which have to service large amounts of data so any optimisation of the hardware is very worthwhile, or in software radio systems that require infrequent protocol modifications. Show less

This project was funded by EPSRC which is a UK research funding organization. It started on 1 June 1996 and its duration was 3 years. This project implemented dynamic reconfiguration where one sub-circuit is completely replaced by another sub-circuit. The deliverable of the project was an FPGA-based system to accelerate the rendering of PostScript jobs. The FPGA hardware performs the basic PostScript drawing operations. For output to a screen this may result in only modest speed-ups, but for… Show more

This project was funded by EPSRC which is a UK research funding organization. It started on 1 June 1996 and its duration was 3 years. This project implemented dynamic reconfiguration where one sub-circuit is completely replaced by another sub-circuit. The deliverable of the project was an FPGA-based system to accelerate the rendering of PostScript jobs. The FPGA hardware performs the basic PostScript drawing operations. For output to a screen this may result in only modest speed-ups, but for full color production quality jobs at thousands of dots per inch we demonstrated a significant speed-up. By comparison, conventional approaches involve using a dedicated personal computer and often require many hours of processing to produce only a few pages.
The research results of the product involved the implementation and refinement of the virtual hardware concept that I first presented at the FCCM’94 conference for the implementation of 3D graphics algorithms on FPGAs. This technique allows circuits to be rapidly swapped into and out of FPGAs in a similar manner to that in which pages are swapped in a virtual memory system. This allows a large circuit to be realised on a small resource by only swapping in the portion of that circuit required at any particular instant. For example, when rendering lines, only the line rasteriser circuit needs to be realised on the FPGA. When a circle then needs to be drawn, the line circuit is over-written with a circle circuit. This method is essential for the realisation of a complex circuit for rasterising PostScript drawing operations on FPGAs which have very limited hardware resources. Show less

I have been the program chair, general chair and finance chair of several conferences including MEMOCODE, FPGA, FPL and FCCM. I have been a special edition editor of the Journal of Functional Programming and I am an associate editor of the ACM journal Transactions on Embedded Computing Systems. I have served on several NSF panels as I have also reviewed for EPSRC and the EU. I have been elected to the ACM SIGPLAN executive committee (from June 2015 for 3 years) which is ACM special interest… Show more

I have been the program chair, general chair and finance chair of several conferences including MEMOCODE, FPGA, FPL and FCCM. I have been a special edition editor of the Journal of Functional Programming and I am an associate editor of the ACM journal Transactions on Embedded Computing Systems. I have served on several NSF panels as I have also reviewed for EPSRC and the EU. I have been elected to the ACM SIGPLAN executive committee (from June 2015 for 3 years) which is ACM special interest group in programming languages.

I have served on program committees for many conferences including ICFPT, FPGAs for Custom Computing Machines (FCCM), FPGA, Formal Methods for Computer Aided Design (FMCAD), FPL, FPT, MEMOCODE, HFL, DAMP, Designing Correct Circuits (DCC), The Haskell ACM Symposium and well as several other conferences and workshops. I have also served on the program committee for the Design Automation and Test in Europe (DATE) conference and the System-on-Chip conference and I chaired this track for three years. I currently serve on the PC for the DATE track on Architectural Synthesis. I have also reviewed many conference papers and journal articles. For example I have reviewed for the IEEE Transactions on VLSI, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, the journal of Tools and Algorithms for the Construction and Analysis of Systems (TACAS), the Journal of Functional Programming, the Journal of VLSI Signal Processing on Reconfigurable Computing, the IEE Proceedings for Computers and Digital Techniques, the International Journal on Software Tools for Technology Transfer and the (British) Computer Journal. Show less