Scott Runner

Scott Runner

Carlsbad, California, United States
11K followers 500+ connections

About

An automotive and technology executive that combines software, semiconductor, cloud and…

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Activity

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Experience

  • Mobile-X.AI

    San Diego, California, United States

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    Mountain View, California, United States

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    San Diego Metropolitan Area

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    Paris, Île-de-France, France

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    Greater San Diego Area

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    Greater San Diego Area

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    San Diego, CA

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    San Diego, CA

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    San Diego, California

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    Greater San Diego Area

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    Newport Beach, CA

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    San Diego, CA

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    Beaverton, Oregon

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    Mt. View, California

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    San Jose, CA

Education

Volunteer Experience

  • Carlsbad Educational Foundation Graphic

    Chairman Of The Board

    Carlsbad Educational Foundation

    - 6 years 7 months

    Education

    The Carlsbad Educational Foundation funds programs in the areas of hands-on science, district-wide music and educational innovation that benefit over 11,000 K-12 students in the Carlsbad Unified School District. Programs such as Science Olympiad, Project Lead the Way, the Robotics programs, FIRST Lego League, the school music programs, BizTown, FIRST Tech Challenge, MY ACCESS, Kids Care, the iPad Project, the International Baccalaureate program and many other programs that would not happen…

    The Carlsbad Educational Foundation funds programs in the areas of hands-on science, district-wide music and educational innovation that benefit over 11,000 K-12 students in the Carlsbad Unified School District. Programs such as Science Olympiad, Project Lead the Way, the Robotics programs, FIRST Lego League, the school music programs, BizTown, FIRST Tech Challenge, MY ACCESS, Kids Care, the iPad Project, the International Baccalaureate program and many other programs that would not happen without the work of CEF.

  • Georgia Institute of Technology Graphic

    Board Member - ECE (Electrical & Computer Engineering) Advisory Board

    Georgia Institute of Technology

    - 2 years 4 months

    Education

    An outside perspective is essential to maintaining the relevancy of ECE programs to its alumni and corporate constituencies. The ECE Advisory Board, composed of mostly alumni industry representatives, provides this external assessment during its formal, biannual meetings and throughout the year. The Board is chaired by Steve W. Chaddick.

Publications

  • Deep as chips: the new microprocessors powering AI

    Engineering and Technology

    Artificial intelligence is appearing everywhere, but normal CPUs are not efficient platforms for the technology. Efficiency will only come with a new breed of microprocessors that are engineered specifically for the AI workload of the 2020s.

    See publication
  • The Internet of Transformation - Creating New Insights and Opportunities from IoT

    CIO Applications - Special Issue on IoT

    Those in IT and OT organizations have a unique opportunity to take advantage of the Internet of Things (IoT), or be threatened by it. In this article, I discuss methods to leverage "Data-as-a-Service" framework to help IT+OT organizations deliver new insights to enable new business models, scale efficiency and do more than just manage data, but help manage insights.

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  • Keynote – IEEE SoC Design Conference, 2015 Las Vegas

    IEEE

    “SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH”

    Mobile Applications are not only becoming more complex, but they are facing stiff constraints in power and quality & reliability. In the next decade, consumers are going to be treated to an array of new use case experiences in mobility that one can only dream of today. And new areas are emerging with exciting new user experiences in the car, with features known to many smartphone users making their way into the…

    “SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH”

    Mobile Applications are not only becoming more complex, but they are facing stiff constraints in power and quality & reliability. In the next decade, consumers are going to be treated to an array of new use case experiences in mobility that one can only dream of today. And new areas are emerging with exciting new user experiences in the car, with features known to many smartphone users making their way into the automobile, along with a myriad of other functions that drivers today cannot imagine. The HW and SW IP and systems integration that will enable these experiences are prodigious. Design and verification challenges which must be surmounted to enable such high levels of integration and functionality are daunting. And doing so in the timeframes required to satisfy the appetites of smartphone, tablet and automotive customers, while delivering to cost, power, performance and quality targets demands novel approaches. We will explore these challenges in the design of the most popular devices in the wireless world.

    See publication
  • Keynote – 50th Annual Design Automation Conference (DAC) 2014, Austin Texas

    Design Automation Conference

    Today’s advanced Systems on a Chip (SoC) for mobile applications are the confluence of high performance CPUs, DSPs, multiple air standard modems for WWAN, WLAN and WPAN, GPS, high end graphics, video and audio CODECs, a variety of peripherals, high speed memory and security and power management technologies on one SoC or SiP. Adding RF, PMIC and DDR memory and you truly have a complete system. Designing such devices marries multiple disciplines of digital and mixed signal HW, SW, systems…

    Today’s advanced Systems on a Chip (SoC) for mobile applications are the confluence of high performance CPUs, DSPs, multiple air standard modems for WWAN, WLAN and WPAN, GPS, high end graphics, video and audio CODECs, a variety of peripherals, high speed memory and security and power management technologies on one SoC or SiP. Adding RF, PMIC and DDR memory and you truly have a complete system. Designing such devices marries multiple disciplines of digital and mixed signal HW, SW, systems, design, verification, packaging, physical design engineers and many others. Doing so in the time frames required to satisfy the appetites of smartphone and tablet customers, while delivering to cost, power, performance and quality targets demands novel approaches in design methodology. We will explore methodologies to address HW-SW co-design, power and design verification and validation in the design of the most popular device in the wireless world.

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  • Hardware and Software: Verification and Testing: 9th International Haifa Verification Conference, HVC 2013, Haifa, Israel, November 5-7, 2013, Proceedings

    Springer

    This book constitutes the refereed proceedings of the 9th International Haifa Verification Conference, HVC 2013, held in Haifa, Israel in November 2013. The papers are organized in topical sections on SAT and SMT-based verification, software testing, supporting dynamic verification, specification and coverage, abstraction and model presentation.

    See publication
  • 22 Papers and Articles authored

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  • ARM System Developer's Guide: Designing and Optimizing System Software

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    Contributed solutions for power optimization and HW implementation and integration aspects into mobile devices

    See publication

Patents

  • SYSTEM AND METHOD FOR PEAK CURRENT MANAGEMENT TO A SYSTEM ON A CHIP

    Filed US 2346863

    Various embodiments of methods and systems for managing current
    consumption in a portable computing device (“PCD”) or its equivalent are disclosed.
    An exemplary method for managing current consumption in a PCD comprises dividing
    a duration of time associated with a maximum allowable current consumption through a
    voltage regulator into a plurality of N sub-durations. The current consumption for each
    sub-duration is monitored and a moving sum of current consumption is calculated…

    Various embodiments of methods and systems for managing current
    consumption in a portable computing device (“PCD”) or its equivalent are disclosed.
    An exemplary method for managing current consumption in a PCD comprises dividing
    a duration of time associated with a maximum allowable current consumption through a
    voltage regulator into a plurality of N sub-durations. The current consumption for each
    sub-duration is monitored and a moving sum of current consumption is calculated for a
    plurality of past sub-durations. Using the sum of current consumption, the method may
    determine a current budget for a next sub-duration or next set of consecutive subdurations.
    Subsequently, throttling levels of power consuming processing components
    may be adjusted such that a maximum allowable current consumption over consecutive
    N sub-durations may be maintained beneath a peak current threshold without
    unnecessarily sacrificing processing capacity of the processing components. Throttling
    levels may be adjusted in some embodiments based on active dynamic current
    consumption levels of processing components deduced from operating temperatures of
    the processing components.

Organizations

  • IEEE

    Senior Member

    - Present

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