Saransh Jain

Performed Differential Power Analysis on power traces taken from AES-ECB execution using python
Extracted 128-bit secret AES key via pearson's correlation

Implemented profiler for dynamic workload characterization of workload based on instruction-issue pattern for GPGPU workloads
Integrated logic for runtime selection of warp-scheduling policy based on profiler inputs

Designed a simulator modelling super-scalar out-of-order processor with user-defined instruction window.
Implemented register renaming and reservation stations to model Tomasulo algorithm.
Integrated previously implemented cache-hierarchy simulator to model memory access latencies

Implemented bus-based and directory-based cache coherence protocols such as MESI, MOESI etc on a trace driven Distributed Share Machine(DSM) simulator
Evaluated and contrasted performance metrics across various coherence protocols

Developed simulator for 2-bit branch predictor with global branch history implementation.
Integrated previously implemented cache-hierarchy simulator to model branch target buffer structure

Developed a highly configurable cache and memory hierarchy simulator. Cache-models developed in this project are capable of modelling different replacement policies,write policies, associativity , size etc.
Also modelled the typical memory hierarchy structure seen in modern day processors to help analyze the impact of cache design on system performance(impact of cache misses).

Designed and simulated a Razor Flip-Flop for detecting errors from dynamically varying logic delays. The circuit was developed using Cadence Virtuoso and Mentor Graphics Calibre tools.

Designed and simulated a Razor Flip-Flop for detecting errors from dynamically varying logic delays. The circuit was developed using Cadence Virtuoso and Mentor Graphics Calibre tools.

Participated in Shastra 2010(Techfest hosted by IIT-Madras). Modeled a fully mechanical powered vehicle using clock spring. The machine was made capable of vertical climbing, traversing on a horizontal rope and shooting projectiles

Extracted last-n load values for multiple benchmarks compiled for RISC-V
Pre-Processed Data for creating balanced input to neural network
Implemented a feed-forward neural-network based selector for last-n value predictor
Demonstrated accuracy of over 81% for with last 4 values

Modified Xinu OS source code for multiple projects
Enabled virtualization of memory for x86 using paging support. Installed page-tables for existing code. Implemented on-demand paging for heap.
Implemented spin-lock, guard-lock and and priority-inheritance based lock. Also implemented deadlock detection mechanism.
Implemented Lottery and Multi-Level Feedback Queue scheduling policies.

Designed decryption block for Ring-Binary-Learning-with-Errors encryption scheme for maximizing throughput
Implemented synthesizable hardware for the same using verilog. Synthesized design on a Spartan-6 FPGA using ISE WebPack.
Performed side-channel attack(using power analysis) to break the same block and extracted protected key

Implemented a hybrid address/data stride predictor with a confidence estimator on an OOO RISC-V simulator.
Analyzed bottlenecks for various workloads to tune configurable predictor towards overall performance.
Demonstrated gains of upto 37% on certain workloads often outperforming similar sized cache structures.

Designed hardware for a Convolutional Neural Network with major constraints on I/O bandwidth.
Extensively used hierarchical module design in verilog to implemented a synthesizable version for the same design.
Implemented highly parameterized Address Generation unit to enable reuse across module saving considerable verification effort.

● As the Technical Team Leader, designed the electrical subsystem for a prototype fuel efficient gasoline powered car
● Achieved a mileage of 70 kmpl as the primary on-track driver for ‘Team BITS

Designed an x86 based system to measure lap-time of participants in a race with the help of sensors counters, LEDs and a seven segment display.