“Ujjwal is a reliable, diligent, and fast-learning engineer and a wonderful work colleague. I have worked closely with Ujjwal for over a year on the functional, post-silicon validation of Discrete Gfx (DG) products. In the past year that I have worked with him, he has learned and mastered the RAS-based knowledge/skills required to facilitate several debug flows during the post-silicon validation. Despite being one of the few members aware of cross-IP RAS flows and thus, having a packed schedule, he has also managed to help other team members including me with any RAS-based questions/concerns we'd pose. Ujjwal's willingness to help other teams in the validation for their test cases such as the Memory team, while reliably fulfilling his own responsibilities for RAS demonstrates his strong work ethic and value for teamwork. Last but not least, I admire his curious nature; he is always willing to learn from team members about topics that might not be directly related to his area of expertise. Above all, I am impressed with Ujjwal's ability to remain calm even during taskforce debugs that are usually quite intense. Ujjwal is definitely going to serve as an asset for any team he works in and thus, I recommend him :)”
About
Programming Languages: Perl, Verilog, System-Verilog, C++.
ASIC Flow: RTL Design,…
Experience
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Education
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San Jose State University
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Activities and Societies: SJSU Badminton club. Won Gold medal representing San Jose State University in Sun God Badminton tournament hosted by University of California, San Diego in MAY 2014.
I was enrolled at SJSU as a graduate student, pursuing MS in Electrical Engineering with Digital System and Logic Design as my specialization.
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Activities and Societies: Badminton Club: Won National Inter College Badminton Tournament representing my college in Year 2008, 2010 & 2011.
I studied my Bachelor of Technology from Rajasthan Technical University in Electronics and Communication Engineering.
Licenses & Certifications
Courses
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ASIC CMOS Design
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Advance Computer Architecture
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Advanced Digital System Design and Synthesis(Audit)
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Digital Communication
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Digital Design
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Digital Design for DSP & Communication
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Discrete Signal Processing
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Electronic Device & Circuits
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FPGA
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High Speed CMOS Circuits
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Perl
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Semiconductor Devices
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SoC Design & Verification with System Verilog
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Static Timing Analysis
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System Verilog
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VERILOG
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VLSI Design
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Projects
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Bit Error Rate of BPSK in AWGN channel
Successfully implemented bit error rate of binary phase shift keying in Additive White Gaussian Noise channel using MATLAB.
Successfully implemented AWGN on Verilog. Verified the code withe the MATLAB model by sending different stimulus.
Tools used: MATLAB, Xilinx ISE.
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Electronic Voting Machine on digilent Spartan 3E FPGA board
• Successfully designed & implemented electronic voting machine for polling of two parties using Digilent Spartan 3E FPGA board having arrangement of avoiding multiple voting and booth capturing situations.
• Tools used: Verilog, Xilinx ISE, Digilent Adept
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5 Stage MIPS pipe-lined Processor
• Designed and Implemented 32-bit MIPS (Microprocessor without interlocked pipe-lining stages ) processor using verilog.
• Design includes Forwarding unit, stalling of the pipeline, hazard detection unit, and smart scheduler(out of order).
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DMA Controller
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1. Designed DMA Controller, that can handle peripheral device through a low speed bus in Verilog
2. Project involves simulation and synthesis using Design Compiler, VCS, NC Verilog and I VerilogOther creators -
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Radix- 8 Montgomery Multiplier
• Designed a 32 bit Radix- 8 Montgomery Multiplier using 45nm CMOS process with a team of four.
• Blocks used were Decoder, 32-bit Carry Save Adder, 32-bit Multiplexer, Buffers and logic family used were Transmission and Static gates
• Responsible for implementation of 32-bit Multiplexer, 32-bit Ripple Carry Adder, and integration of all blocks to form one Montgomery cell
• Number of transistors implemented in one MM cell was 5992.
Tool Used: Cadence Virtuoso.
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Class Based Verification of Arbiter.
• The main aim of this project was to build a complete class based verification environment for 4-bit round robin Arbiter
• Used constrained randomization technique.
• Technology used: System Verilog, QUESTA SIM.Other creators -
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Universal Asynchronous Receiver and Transmitter (UART)
• Designed transmitter and receiver blocks using VERILOG. It exchanges information and interacts via serial data channels
• Transmitter consists of a Controller, Data Register, Data Shift Register and Status Register to count the transmitted bits
• Technology used: Verilog 2001, Xilinx ISE 13.4.
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Mini Reduced Instruction Set Computing (RISC) Processor
• Designed a 16-bit RISC processor using VERILOG where control dominated and data dominated units were implemented separately
• The Data dominated unit consists of RAM, ALU, Adder, Concatenate Block, Multiplexer, Instruction memory, Instruction Decoder, Program Counter, and Registers. Instruction set implements ALU, immediate, load- store, and branch instructions
• Tool used: Verilog 2001, Xilinx ISE 13.4.
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Organizations
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intel
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Recommendations received
7 people have recommended Ujjwal
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