Urvashi Dhoot

-Implemented PODEM algorithm to design a set of test vectors for finding faults in given circuit, achieving an average fault coverage of 98%. The algorithm takes fault list generated after fault collapsing by equivalence and dominance.

-Designed and implemented a 32-bit address, 32 bit data Tomasulo OoO Processor with speculative fetching for branch and jump instructions on the Xilinx Spartan 6 FPGA using Digilent Adept System.
-Designed a Copy Free Check pointing mechanism along with Reorder Buffer, Physical Register File, Free Register List, Issue unit and Dispatch Unit using VHDL.

-Used clock gating and Data gating techniques for power optimization. Custom D-Flip Flop design for register file.
-Implemented instruction fetching and decoding using Perl scripting with automated result verification.

-Designed SRAM memory block and optimized logic and area along with delay minimization by applying various optimization techniques studied through the course
-Designed universal logic gates using Finfet technology and verification and simulation using Perl and Hspice

LED's structure was studied in depth and analysed using quantum mechanics. The possible transitions were calculated and thereafter the associated wavelengths and colours were analysed.
The calculations and mathematics involved was done in "MATHEMATICA" and the project was complied using "LATEX" . The literature study was appreciated and we have further been advised to write a paper for our work.

A circuit for detecting fire was developed using processors ( 8051 ) and sensors for temperature. whenever the temperature rise above a certain value known to the controller it turns the fan ON.

- Designed a DDR3 Memory (IP by DENALI) controller to perform scaler/block/atomic read/write operations at 625Mhz
- Interfaced the design with the memory using SSTL interface. Also converted the RTL into Gate level netlist using deign compiler and performed APR using Cadence Encounter
- Performed STA and timing closure using Primetime Synopsys

-Designed ALU for performing logical and arithmetic logic
-Designed special convertible FIFO which allows data flow between NetFPGA and processor with packet filtering mechanism

-Built a 5 stage pipeline with fully customized ISA based on MIPS ISA on NetFPGA (Virtex II Pro)
-Implemented C based custom ISA assembly code translator
-Designed a Perl based transmission monitoring system with memory R/W operations, and base module using schematics, IP Cores and Verilog.
-Pattern match based network monitoring incorporated in the pipelined processor.

*Created schematics and layout for the above design
*Minimized the area and delay product using sizing and optimizing the logic for the design

*studied about fractals and found ways to measure fractal dimensions
*learnt about the box counting method and how it is used to find fractal dimension
*implemented the ellipse counting method on the cell images to find out the fractal dimension
*Coded and simulated in MATLAB

•Layout implementation of MOS gates (INV, NAND, NOR, XOR), MUX, 4-bit adder in 200nm CMOS technology using Cadence Virtuoso layout editor.
• Minimized the propagation delay through sizing of the transistors.