About
Data leader with technical depth and breadth of experience from hands-on building and…
Articles by Vijay
Activity
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Want to work with LLMs and the edge of NLU? Come work with Felicia and her team!
Want to work with LLMs and the edge of NLU? Come work with Felicia and her team!
Liked by Vijay Sathish
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"Hunters is recognized as a Fast Moving Leader that removes false positives and excessive alerts, reduces redundant triage efforts, and provides a…
"Hunters is recognized as a Fast Moving Leader that removes false positives and excessive alerts, reduces redundant triage efforts, and provides a…
Liked by Vijay Sathish
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Managing Operational workforces and workflows is a necessary part of running a business, but is manually intensive, repetitive and costly for the…
Managing Operational workforces and workflows is a necessary part of running a business, but is manually intensive, repetitive and costly for the…
Shared by Vijay Sathish
Experience
Education
Licenses & Certifications
Publications
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Lossless and Lossy Memory I/O Link Compression for Improving Performance of GPGPU Workloads
To Appear in Proceedings of 21st IEEE conf. on Parallel Architecture and Compilation Techniques (PACT); Acceptance Rate: 19%
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Improving the Throughput of Power-Constrained GPUs through Adaptive Voltage, Frequency, and Core Scaling
In Proceedings of 20th IEEE conf. on Parallel Architecture and Compilation Techniques (PACT); Acceptance Rate: 16%
Patents
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Hardware stream prefetcher with dynamically adjustable stride
Issued US 9280476
An apparatus may include a first memory, a control circuit, a first address comparator and a second address comparator. The first memory may store a table, which may include an expected address of a next memory access and an offset to increment a value of the expected address. The control circuit may read data at a predicted address in a second memory and store the read data in a cache. The first and second address comparators may determine if a value of a received address is between the value…
An apparatus may include a first memory, a control circuit, a first address comparator and a second address comparator. The first memory may store a table, which may include an expected address of a next memory access and an offset to increment a value of the expected address. The control circuit may read data at a predicted address in a second memory and store the read data in a cache. The first and second address comparators may determine if a value of a received address is between the value of the expected address and the value of the expected address minus a value of the offset. The control circuit may also modify the value of the offset responsive to determining the value of the received address is between the value of the expected address and the value of the expected address minus the value of the offset.
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Dynamically adjusting the hardware stream prefetcher prefetch ahead distance
Issued US 9,256,541
An apparatus for prefetching data for a processor is presented. The apparatus may include a memory, a first counter, a second counter, and a control circuit. The memory may include a table with at least one entry in which the at least one entry may include an expected address of a next memory access and a next address from which to fetch data, wherein the next address is an offset value different from the expected address. The at least one entry may also include a maximum limit for the offset…
An apparatus for prefetching data for a processor is presented. The apparatus may include a memory, a first counter, a second counter, and a control circuit. The memory may include a table with at least one entry in which the at least one entry may include an expected address of a next memory access and a next address from which to fetch data, wherein the next address is an offset value different from the expected address. The at least one entry may also include a maximum limit for the offset value. The first counter may increment responsive to an address of a memory access matching the expected address. The second counter may increment responsive to the address of the memory access resulting in a cache miss. The control circuitry may be configured to increment the maximum value of the offset value dependent upon a value of the second counter.
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Courses
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A/B Testing
By Google
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Advanced Computer Architecture
CS 752
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Compilers
CS 536
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Computer Systems Architecture
EE 282
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Data Wrangling with MongoDB
By MongoDB
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Databases
CS 564
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Descriptive Statistics
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Design and Analysis of Algorithms
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Digital Circuits and Components
ECE 555
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Exploratory Data Analysis
By Facebook
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Inferential Statistics
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Introduction to Artificial Intelligence
By Thrun and Norvig
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Machine Learning
By Sebastian Thrun
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Operating Systems
CS 537
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Parallel Computer Architecture
CS 757
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Real Time Embedded Systems
ECE 750
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Special Topics (Building Microprocessors)
CS 758
Projects
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Kaggle - Caterpillar Tube Assembly Pricing Prediction
- Placed 133/1323 (top 10%) in the competition
- Caterpillar relies on a variety of suppliers to manufacture tube assemblies, with each supplier having their own unique pricing model. The objective of this competition sponsored by Caterpillar was to predict the supplier price quote for a tube assembly given the detailed tube, component, and annual volume data. -
Kaggle - Liberty Mutual Group - Property Inspection Prediction
- Placed 145/2236 (top 6.5%) in the competition
- In this challenge, the task was to predict a hazard score for properties using a dataset of property information.
- To ensure that Liberty Mutual’s portfolio of home insurance policies aligns with their business goals, many newly insured properties receive a home inspection. The results of an inspection help Liberty Mutual determine if the property is one they want to insure.
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Our Org has traditionally leveraged ML to detect financial crimes on the Cash App platform and generate cases for human review. We rely on hundreds…
Our Org has traditionally leveraged ML to detect financial crimes on the Cash App platform and generate cases for human review. We rely on hundreds…
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