About
• Broad experience in modern C++, Python, and Ruby
• Deep familiarity with CPU…
Activity
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I'm excited to share how senders is solving real asynchronous concurrency problems for us. Who knows ... maybe I'll even share some insights on…
I'm excited to share how senders is solving real asynchronous concurrency problems for us. Who knows ... maybe I'll even share some insights on…
Liked by Yury Bayda
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To the 18,000 Intel employees who are being laid off, I'd like to help. If you need assistance with improving your communication skills for…
To the 18,000 Intel employees who are being laid off, I'd like to help. If you need assistance with improving your communication skills for…
Liked by Yury Bayda
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View my verified achievement from Ford Motor Company.
View my verified achievement from Ford Motor Company.
Liked by Yury Bayda
Experience
Education
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Moscow Institute of Physics and Technology (State University) (MIPT)
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Dissertation title: “Methods for development and testing of FPGA-based cycle-accurate microprocessor simulators”.
MIPT is one of the Top-3 universities in Russia and 45-300 in international ratings (https://mipt.ru/english/about/ranking/). -
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• Elected to the Student Government
• Holder of the “Development” foundation academic scholarship
Licenses & Certifications
Volunteer Experience
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Senior Lecturer
Moscow Institute of Physics and Technology (State University) - MIPT, Phystech
- 10 months
Education
Delivered CPU microarchitecture lectures to undergraduate students at Intel Student Lab. Recruited and interviewed students for internships at Intel.
Publications
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Field-programmable gate arrays usage features for microprocessor simulation
Innovations and investments
Developing a new microprocessor architecture requires making a lot of decisions based on simulation results. Architects need to analyze pa-rameters such as performance, power, etc. Modern FPGAs can provide a cost effective solution with up to 2-3 orders higher, cycle-accurate simulation speed than conventional software simulators without loss of results accuracy. Unfortunately, FPGA-based models require much higher development effort due to low abstraction level of conventional hardware…
Developing a new microprocessor architecture requires making a lot of decisions based on simulation results. Architects need to analyze pa-rameters such as performance, power, etc. Modern FPGAs can provide a cost effective solution with up to 2-3 orders higher, cycle-accurate simulation speed than conventional software simulators without loss of results accuracy. Unfortunately, FPGA-based models require much higher development effort due to low abstraction level of conventional hardware description languages, much longer development cycle and limited logic capacity of modern FPGAs. In this paper, we consider features of FPGA usage for microprocessor simulation, which helps to reduce design effort in comparison with development of an FPGA-based prototype. We first show benefits of decoupling FPGA and model clocks, then we introduce an efficient model representation in a form of oriented weighted graph which also provides a convenient way to describe both hardware and software performance models. And finally we discuss the Bluespec SystemVerilog high-level hardware description language
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Method and system for automated unit-level testing of FPGA-based cycle-accurate microprocessor simulator using software simulator as a golden model
Computer Science and Engineering
For new hardware/software co-designed CPU architectures there is a need for fast and flexible performance simulation to perform extensive design space exploration in both software and hardware domains. To confirm reliability of design decisions, the simulator should also be accurate, which is usually achieved at the cost of reduced simulation speed. Although FPGA-accelerated simulators have dramatically higher speed than software simulators, such models require much higher development effort…
For new hardware/software co-designed CPU architectures there is a need for fast and flexible performance simulation to perform extensive design space exploration in both software and hardware domains. To confirm reliability of design decisions, the simulator should also be accurate, which is usually achieved at the cost of reduced simulation speed. Although FPGA-accelerated simulators have dramatically higher speed than software simulators, such models require much higher development effort. An FPGA-based model generally assumes a top-down design flow, where the system can be tested only after all units have been developed. The paper describes a method and system for bottom-up development and automated unit-level testing of FPGA-based cycle-accurate simulator leveraging functionality of existing software simulator.
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Method of converting a microprocessor software performance model to FPGA-based hardware simulator
Computer Science and Engineering
To maintain low simulation time as continuous improvements are made to the performance model accuracy, FPGAs can provide a cost-effective option to achieve the goal of fast simulation. In this paper, we describe a novel method for converting a software model to an FPGA-based model. It allows developing the fast FPGA-based simulator during the architecture research stage with small effort by leveraging existing software simulator design. We also evaluate and enhance the FPGA-based HAsim…
To maintain low simulation time as continuous improvements are made to the performance model accuracy, FPGAs can provide a cost-effective option to achieve the goal of fast simulation. In this paper, we describe a novel method for converting a software model to an FPGA-based model. It allows developing the fast FPGA-based simulator during the architecture research stage with small effort by leveraging existing software simulator design. We also evaluate and enhance the FPGA-based HAsim microarchitectural simulation framework.
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Solutions for increasing software cycle-accurate microprocessor simulator speed problem
Contemporary problems of liberal and natural sciences
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Converting of microprocessor software performance model to hardware simulator based on field programmable logic arrays
Proceeding of Moscow Institute of Physics and Technology
Developing of new microprocessor architecture requires making a lot of decisions based on performance modeling. FPGAs can provide a cost effective solution with up to 3 orders higher simulation speed than conventional software simulators. In this paper, we describe a novel methodology for converting of existing software cycle-accurate simulator to FPGA-based hardware model.
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Converting of microprocessor software performance model to FPGA-based cycle-accurate simulator
XI International conference “Fundamental and applied research, development and application of high technology in industry”.
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Implementation of an FPGA-based out-of-order microprocessor cycle-accurate simulator
ХХХVIII International Gagarin Scientific Conference
Development of a new microprocessor architecture requires a lot of decisions to be made depending on the results of performance modelling of the future microprocessor. In most cases such models (performance simulators) are implemented using high-level programming languages like C/C++ or specialized libraries like SystemC.
These conventional software tools dramatically simplify the development process, but the simulation speed of modern complex microprocessors doesn’t exceed tens of…Development of a new microprocessor architecture requires a lot of decisions to be made depending on the results of performance modelling of the future microprocessor. In most cases such models (performance simulators) are implemented using high-level programming languages like C/C++ or specialized libraries like SystemC.
These conventional software tools dramatically simplify the development process, but the simulation speed of modern complex microprocessors doesn’t exceed tens of kilohertz. This simulation speed means that a simulation of 2 minutes of the target microprocessor will take about a year, thus making performance research of long workloads impossible (such as required for branch prediction algorithm selection).
Recently large manufactures of field-programmable gate arrays (FPGA) have included the ability to connect to general purpose computers, attracting the community to use them as simulation accelerators. -
Usage of software cycle-accurate microprocessor simulator in developing of FPGA-based hybrid performance model
ХХХVII International Gagarin Scientific Conference
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Methodology for converting a performance model from Asim to FPGA-based HAsim
Design & Test Technology Conference
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Hardware-software FPGA-based simulator of processor with a vector of instruction pointers
Proceedings of 53rd MIPT Conference
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Indirect branches target addresses translation cache optimization
Proceedings of 51st MIPT Conference
Patents
Courses
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Project Management (PMBOK)
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Rapid Software Testing
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Projects
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Functional and performance simulation of a Multimedia Digital Signal Processor (MDSP)
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Purpose of the project is to create light version of functional and clock-precise simulators of a microprocessor optimized for digital signal processing (DSP). The project was developed by a group of students under the guidance of Intel employees.
Other creatorsSee project
Languages
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English
Full professional proficiency
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Russian
Native or bilingual proficiency
More activity by Yury
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I am happy to share that I am now certified by ATA (American #Translators Association) in English to Russian language pair! The #ATA #certification…
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Accellera invites you to attend the first meeting of the Federated Simulation User Group! This meeting is open to all interested parties, including…
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I had a wonderful time presenting to Ford Digital. A great interactive group.
I had a wonderful time presenting to Ford Digital. A great interactive group.
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On June 26th, join us for a free webinar presented by SAE International, Synopsys, and NXP on Accelerated SDV Development: Virtual Prototypes of…
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I am excited to share my experience from DVCon U.S. 2024! We discussed the Federated Simulation Standard and its impact on the future of automotive…
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A very interesting read “Simulating the Whole Car with Multi-Domain Simulation” by Bernard Murphy, SemiWiki.com. He attended the Accellera-sponsored…
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Today it was a great chance to hear from #Intel's CEO - Pat Gelsinger and each member of the executive team in person! Their enthusiasm and…
Today it was a great chance to hear from #Intel's CEO - Pat Gelsinger and each member of the executive team in person! Their enthusiasm and…
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Ford are recruiting more talent in embedded DevOps experts; especially in the Ford Ottawa Office, Canada and in the US. Check out the role, and refer…
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I am building a Software team at Ford. If you are looking for your next challenge as a software developer, go ahead and apply. We want to talk to…
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