Yury Bayda

Developing a new microprocessor architecture requires making a lot of decisions based on simulation results. Architects need to analyze pa-rameters such as performance, power, etc. Modern FPGAs can provide a cost effective solution with up to 2-3 orders higher, cycle-accurate simulation speed than conventional software simulators without loss of results accuracy. Unfortunately, FPGA-based models require much higher development effort due to low abstraction level of conventional hardware… Show more

Developing a new microprocessor architecture requires making a lot of decisions based on simulation results. Architects need to analyze pa-rameters such as performance, power, etc. Modern FPGAs can provide a cost effective solution with up to 2-3 orders higher, cycle-accurate simulation speed than conventional software simulators without loss of results accuracy. Unfortunately, FPGA-based models require much higher development effort due to low abstraction level of conventional hardware description languages, much longer development cycle and limited logic capacity of modern FPGAs. In this paper, we consider features of FPGA usage for microprocessor simulation, which helps to reduce design effort in comparison with development of an FPGA-based prototype. We first show benefits of decoupling FPGA and model clocks, then we introduce an efficient model representation in a form of oriented weighted graph which also provides a convenient way to describe both hardware and software performance models. And finally we discuss the Bluespec SystemVerilog high-level hardware description language Show less

For new hardware/software co-designed CPU architectures there is a need for fast and flexible performance simulation to perform extensive design space exploration in both software and hardware domains. To confirm reliability of design decisions, the simulator should also be accurate, which is usually achieved at the cost of reduced simulation speed. Although FPGA-accelerated simulators have dramatically higher speed than software simulators, such models require much higher development effort… Show more

For new hardware/software co-designed CPU architectures there is a need for fast and flexible performance simulation to perform extensive design space exploration in both software and hardware domains. To confirm reliability of design decisions, the simulator should also be accurate, which is usually achieved at the cost of reduced simulation speed. Although FPGA-accelerated simulators have dramatically higher speed than software simulators, such models require much higher development effort. An FPGA-based model generally assumes a top-down design flow, where the system can be tested only after all units have been developed. The paper describes a method and system for bottom-up development and automated unit-level testing of FPGA-based cycle-accurate simulator leveraging functionality of existing software simulator. Show less

To maintain low simulation time as continuous improvements are made to the performance model accuracy, FPGAs can provide a cost-effective option to achieve the goal of fast simulation. In this paper, we describe a novel method for converting a software model to an FPGA-based model. It allows developing the fast FPGA-based simulator during the architecture research stage with small effort by leveraging existing software simulator design. We also evaluate and enhance the FPGA-based HAsim… Show more

To maintain low simulation time as continuous improvements are made to the performance model accuracy, FPGAs can provide a cost-effective option to achieve the goal of fast simulation. In this paper, we describe a novel method for converting a software model to an FPGA-based model. It allows developing the fast FPGA-based simulator during the architecture research stage with small effort by leveraging existing software simulator design. We also evaluate and enhance the FPGA-based HAsim microarchitectural simulation framework. Show less

Developing of new microprocessor architecture requires making a lot of decisions based on performance modeling. FPGAs can provide a cost effective solution with up to 3 orders higher simulation speed than conventional software simulators. In this paper, we describe a novel methodology for converting of existing software cycle-accurate simulator to FPGA-based hardware model.

Development of a new microprocessor architecture requires a lot of decisions to be made depending on the results of performance modelling of the future microprocessor. In most cases such models (performance simulators) are implemented using high-level programming languages like C/C++ or specialized libraries like SystemC.
These conventional software tools dramatically simplify the development process, but the simulation speed of modern complex microprocessors doesn’t exceed tens of… Show more

Development of a new microprocessor architecture requires a lot of decisions to be made depending on the results of performance modelling of the future microprocessor. In most cases such models (performance simulators) are implemented using high-level programming languages like C/C++ or specialized libraries like SystemC.
These conventional software tools dramatically simplify the development process, but the simulation speed of modern complex microprocessors doesn’t exceed tens of kilohertz. This simulation speed means that a simulation of 2 minutes of the target microprocessor will take about a year, thus making performance research of long workloads impossible (such as required for branch prediction algorithm selection).
Recently large manufactures of field-programmable gate arrays (FPGA) have included the ability to connect to general purpose computers, attracting the community to use them as simulation accelerators. Show less