Efficiently laying out sensitive RF, Analog and Mixed-Signal circuits conforming to all physical design verification (PDV) requirements while balancing demanding area, performance, and power specifications
Identifying quality and reliability improvements in IC circuit and layout design
Supporting or performing design verification from sub-block up through top-level
Collaborating effectively with local and remote team members
Developing accurate layout design schedules and resource estimates
Proactively looking for continuous improvement opportunities in the flow, layout and design methodologies
Delivering on project assignments with integrity, commitment, and excellence
Requirements
3+ years of experience in layout and verification tools and methodologies for RF/Analog/Mixed-Signal ICs
3+ years of experience in Cadence layout (Virtuoso, VXL) and Calibre verification (ERC, DRC, LVS)
Demonstrated success in delivering quality work product
FinFET preferred
Strong communication, debugging and analytical skills with complex technical concepts
Experience in DFM hierarchical layout construction for efficient verification and integration
Comprehensive understanding of the target process to balance layout and design needs, e.g. crosstalk, RC delay, electro-migration, IR drop, self-heating, shielding, matching, guard rings and latch up