Eliyan Corporation’s Post

UCIe Consortium Chairman Debendra Das Sharma recently co-authored the “Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications” article to explore the many drivers for on-package integration of chiplets including overcoming reticle limitations to deliver performance, functionality, and yield tradeoff with larger dies. Read the full article via IEEE Computer Society to learn more: https://bit.ly/4aXfPA8 #UCIe #UCIeConsortium #chiplets

We're happy to share our recent work "Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips", accepted at #DSN2024. We've also released the source code! Paper on arXiv: https://lnkd.in/e8EbY9Se Source code on Github: https://lnkd.in/ehqH4bTP Authors: Ataberk Olgun, Majd Osseiran, Abdullah Giray Yağlıkçı, Yahya Can Tuğrul, Haocong Luo, Steve Rhyner, Behzad Salami, Juan Gómez Luna, Onur Mutlu We experimentally demonstrate the effects of read disturbance (RowHammer and RowPress) and uncover the inner workings of undocumented read disturbance defense mechanisms in High Bandwidth Memory (HBM), resulting in 23 observations and 8 takeaways with important implications for future read disturbance attacks and defenses. Read our paper and visit our talk at #DSN2024 to learn more! ETH Zurich, Department of Information Technology and Electrical Engineering #RowHammer #RowPress #computing #hardware #software #design #paradigms #innovation #research #computerarchitecture #security #reliability #RowHammer #FPGAs #memory #DRAM #HBM

This letter presents a #dual-#polarization #beamformer #chip for #fifth-#generation (#5G) applications. The chip leverages a #vector-#sum #phase #shifter (#VSPS) approach and single-ended design, allowing a reduced control circuitry complexity. The use of the VSPS translates in both phase shift and gain control, as shown in the system analysis. This beamformer is suitable for four dual-polarized antennas, achieving high gain control for each element. The performance can be summarized as a 1-dB compression point of 11dBm, while having an rms phase and amplitude error lower than 0.5° and 0.4 dB, respectively, at the maximum constant magnitude gain circle. ---- Aniello Franzese, Nebojsa Maletic, Mohamed Eissa, Renato Negra, Andrea Malignaggi More details can be found at this link: https://lnkd.in/eA2SW7Bc

During SNIA’s #SDC23, #NVMExpress shared an overview of Computational Storage, including the new capabilities and overall system improvements the feature enables for #NVMe devices. View the presentation to learn more about NVM Express’ Computational Storage and for insights into the enhanced functionality the feature enables for NVMe technology: https://bit.ly/46Ophn2

What are #Chiplets and how they Assemble Into the Most Advanced SoCs https://lnkd.in/eJUbGZBw

As we celebrate 20 years of Acenet, it left us wondering... What was the first supercomputer in the world like? Designed by physicist John Mauchly and electrical engineer J. Presper Eckert in Philadelphia, the ENIAC (Electronic Numerical Integrator and Computer) weighed 30 tons and filling a 30-by-50-foot room, managed and operated by a staff of men and women. ENIAC was a decimal computer, performing its calculations in decimals, where modern supercomputers now use binary computation. Read more about the fascinating innovations of a 75+ year old supercomputer: https://lnkd.in/grsnYbGG

[Optic] - Ultrafast switching of an optical bit Computers process information based on arrays of so-called bits. Each bit can take the values of one or zero... https://lnkd.in/eVEFXqGk #Optic #CodexInternational

[Optic] - Ultrafast switching of an optical bit Computers process information based on arrays of so-called bits. Each bit can take the values of one or zero... https://lnkd.in/eVEFXqGk #Optic #CodexInternational

Beamforming (Codebook based): A step by step approach: 1. Generation of Resource Grid (RG) 2. load Precoded PDSCH over RG (3gpp) 3. load csi-rs signal over over RG (3gpp) 4. load dmrs signal over RG (3gpp) final RG contains :=(pdsch,dmrs, csi-rs) 5. take ifft plus cp addition 6. convolution through channel 7. noise addition 8. Time synchronization 9. cropping received sample based on (8) 10. fft plus cp removal 11. csi-rs based channel estimation for collecting feedback (i1,i2) 12. pass this (i1,i2) for use in step 2. 13. dmrs based channel estimation for pdsch data decoding That's all. Just you have to build the codebook type as per 3gpp specifications. Integrate all the functionality in order and see the fun😊 #5G #NR #Codebook #Beamforming #3GPP #OFDM #PMIselection

In this article, the authors demonstrate experimentally the first 16-bit photonic cache memory hardware prototype, organized in four addressable cache lines with a 4-bit #wavelength-#division #multiplexing (#WDM)-optical Data Word stored per line, capable of performing at a 20 Gb/s memory-throughput. The proposed optical cache layout combines a WDM-enabled optical #random-#access #memory (#RAM) bank and a complete set of cache peripherals, implementing for the first time all cache functionalities directly in the optical domain. ---- Christos Pappas, Theodoros Moschos, Theoni Alexoudi, Chris Vagionas, Nikos Pleros More details can be found at this link: https://lnkd.in/eZcPVzmf