Gowin Semiconductor Corp’s Post

#STM32L031F6P6 The ultra-low-power STM32L031x4/6 family includes devices in 6 different packages from 20 to 48 pins. The description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L031x4/6 microcontrollers suitable for a wide range of applications: • Gas/water meters and industrial sensors • Healthcare and fitness equipment • Remote control and user interface • PC peripherals, gaming, GPS equipment • Alarm system, wired and wireless sensors, video intercom This STM32L031x4/6 datasheet must be read in conjunction with the STM32L0x1 reference manual (RM0377). The access line ultra-low-power STM32L031x4/6 family incorporates the high-performance Arm® Cortex®-M0+ 32-bit RISC core operating at a 32 MHz frequency, high-speed embedded memories (up to 32 Kbytes of Flash program memory, 1 Kbytes of data EEPROM and 8 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals. The STM32L031x4/6 devices provide high power efficiency for a wide range of performance. It is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes. The STM32L031x4/6 devices offer several analog features, one 12-bit ADC with hardware oversampling, two ultra-low-power comparators, several timers, one low-power timer (LPTIM), three general-purpose 16-bit timers, one RTC and one SysTick which can be used as timebases. They also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock. Moreover, the STM32L031x4/6 devices embed standard and advanced communication interfaces: one I2C, one SPI, one USART, and a low-power UART (LPUART). The STM32L031x4/6 also include a real-time clock and a set of backup registers that remain powered in Standby mode. The ultra-low-power STM32L031x4/6 devices operate from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications.

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A system on Chip is an integrated circuit (IC) that integrates all or most components of a computer system or digital electronic system onto a single chip. This includes the central processing unit (CPU), memory, peripherals, and often other components such as the graphics processing unit (GPU), communications interfaces, and sensors. SOCs are becoming increasingly common as they offer several advantages over traditional systems that use discrete components. These advantages include: Smaller size and lower power consumption Reduced cost Improved performance Increased flexibility Reduced complexity Major SOC Advancements: • Increased transistor density • Heterogeneous integration • Artificial intelligence (AI) acceleration • Increased energy efficiency • New and innovative applications #SOC #SoC_testing #soc_verification #soc_design

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Do you know about Portwell's PCOM-B658VGL COM Express Type 6 Module? It features 13th/12th Gen Intel® Core™ Processors (formerly Raptor Lake-P/Alder Lake-P) and is specifically designed for applications in Medical Devices, Industrial Control, and Edge Computing Solutions. This remarkable solution offers a perfect blend of scalability, high performance, and reliability, all built upon the well-established COM Express standard. Key Specifications are: • Blazing-fast DDR5 memory (up to 96GB) for seamless multitasking  • Versatile I/O including USB4, SATA III, and dual Ethernet for flexible connectivity  • Dual display support with options for 8K resolution ️ • Supports AI acceleration for next-level edge computing capabilities This advanced solution is tailored to meet the needs of various industries, including #medicaltechnology, industrial control, and digital #transformation. It's a testament to Portwell's commitment to delivering cutting-edge technology that balances cost, features, and performance. For more details, visit: https://lnkd.in/e3bwb_fD or contact us at [email protected] #Portwell #COM #Industries #Applications #Efficiency #Network #MedicalTechnology #MedicalDevices #Computing #ComputingSolutions #EdgeComputing #IndustrialControl #Industrial #COMExpress #Embedded #DigitalTransformation #Intel #Intel7

Samsung plans to use the second-generation 3-nanometer (SF3) process and the performance-enhanced version 4-nanometer (SF4X) to produce chips in the second half of 2024, aiming to significantly improve their competitiveness and OEM new products for major customers. The second-generation 3nm (SF3) process is a major upgrade from the first-generation 3nm (SF3E) and offers more functionality. It provides different gate all-around (GAA) for the same unit type, allowing for a wider transistor nanosheet channel width. The second generation 3nm offers better performance and efficiency compared to the 4nm (4LPP) process. It increases execution performance by 22% with the same power and complexity or reduces power consumption by 34% with the same number of clocks and transistors. It also reduces the chip area by 21%. The second-generation 3nm process has better complex design choices compared to its predecessor. Samsung is also developing an enhanced version of the 4nm process called SF4X, specifically designed for high-performance CPUs and GPUs in data centers. This enhanced version is expected to increase performance by 10% and reduce power consumption by 23%. It incorporates advanced transistor-level design technology for optimal synergy and aims to achieve stable high voltage operation and improved SRAM control. #Samsung #ChipTechnology #3nmProcess #4nmProcess #SF3 #SF4X #TransistorTechnology #DataCenters #PowerEfficiency #3nm #4nm #CPU #GPU #transistor #chip #GAA

SK hynix to Kick off Mass Production for #GDDR7 in Q4 2024 #SKhynix, as the market leader in #HBM, targets to begin mass production of its GDDR7 chips in the fourth quarter of 2024, the company said on 13th June. In the meantime, Micron Technology also announced the launch of its GDDR7 graphics #memory at COMPUTEX TAIPEI, which is currently being sampled. According to AnandTech, Micron not only plans to start mass production for GDDR7 this year, but also aims to do so early enough for some customers to ship finished products by year-end, with major applications range from AI and gaming to high-performance computing. Samsung Electronics, on the other hand, is the first among the Big Three to present its GDDR7 products. According to its press release, #Samsung has completed development of the industry’s first GDDR7 #DRAM in July, 2023, a 16-gigabit product, after its development of the industry’s first 24Gbps GDDR6 DRAM in 2022. According to AnandTech, #Samsung is already sampling GDDR7 memory with the aim of launching it in 2024. According to a report from AnandTech, SK hynix already has sample chips available for partners to test. Currently, the company plans to produce both 16Gbit and 24Gbit chips, with data transfer rates of up to 40 GT/s. As Samsung and Micron both expect to begin with 16Gbit chips running at 32 GT/s for their GDDR7 products, whether SK hynix could win customers’ favor by its faster speed attracts attention, AnandTech noted. https://lnkd.in/ebWjub3q #embedded #embeddedsystems #IIOT #industry40 #SSD #storage #memory #NAND #flashmemory #DRAM #electronics #technology #semiconductor #datacenter

Interrupts in the ARM Cortex-M3 processor are crucial for responsive and efficient embedded system design. They enable the processor to respond quickly to external events or internal conditions by temporarily halting the normal program flow and executing a specific interrupt service routine (ISR). Here’s a detailed overview of interrupts in the Cortex-M3: ### Overview of Interrupts The Cortex-M3 processor supports two types of interrupts: 1. **System Exceptions**: Predefined by ARM, these include Reset, NMI, HardFault, MemManage, BusFault, UsageFault, SVCall, DebugMonitor, PendSV, and SysTick. 2. **External Interrupts**: Triggered by external hardware events or peripherals. ### Nested Vectored Interrupt Controller (NVIC) The NVIC manages all interrupts and exceptions, providing: - **Vector Table**: Holds the addresses of ISRs. - **Priority Grouping**: Allows grouping of interrupts into priority levels. - **Interrupt Enabling/Disabling**: Each interrupt can be individually enabled or disabled. - **Preemption**: Supports nested interrupts where higher-priority interrupts can preempt lower-priority ones. ### Interrupt Priorities - **Priority Levels**: Cortex-M3 supports up to 256 priority levels, but typically only a subset is implemented (e.g., 16 levels with 4 bits). - **Grouping**: Priority levels are divided into preemption priority and subpriority to control the nesting and ordering of interrupts. ### Configuring Interrupts To configure and handle interrupts, follow these steps: 1. **Define the ISR**: Write the interrupt service routine. 2. **Enable the Interrupt**: Enable the specific interrupt in the NVIC. 3. **Set the Priority**: Optionally, set the interrupt priority. ### Example: Configuring an External Interrupt Here's an example of configuring and handling an external interrupt on an LPC17xx microcontroller using a GPIO pin: #### Step 1: Define the ISR ```c #include "LPC17xx.h" void EINT3_IRQHandler(void) {   // Clear the interrupt flag (example for GPIO pin interrupt)   if (LPC_GPIOINT->IO2IntStatF & (1 << 10)) {     LPC_GPIOINT->IO2IntClr = (1 << 10); // Clear interrupt flag for P2.10     // Handle the interrupt (toggle an LED or process the event)   } } ``` ### Conclusion Interrupts are a fundamental feature of the ARM Cortex-M3 processor, enabling responsive and efficient handling of events. By understanding how to configure and manage interrupts using the NVIC and CMSIS, developers can create robust embedded systems capable of handling multiple asynchronous events efficiently. Proper priority management and clear interrupt service routines ensure that critical tasks are handled promptly while maintaining overall system stability and performance.

📈AMD recently issued a product discontinuation notice, stating that it will no longer provide Xilinx brand CoolRunner and CoolRunner CPLD chips, as well as Spartan II and Spartan 3 FPGA chips. The specific series mentioned in the notice include commercial/industrial grade products of XC9500XL, CoolRunner, XPLA 3, CoolRunner II, Spartan II, and Spartan 3, 3A, 3AN, 3E, 3ADS. 📈AMD made it clear in the notice that after cutting off the existing CPLD or FPGA core, it will not provide any direct replacement products. If AMD chooses not to follow up and replace it in the future, it means that AMD will give up its old FPGA chips and completely end CPLD products. #integratedcircuit #EMS #SMT #AI #5G #Semiconductor #Infineon #NXP #MICROCHIP #ADI #TexasInstruments #Xilinx #Renesas #ONSEMI #STMicroelectronics #Intel #Electroniccomponents #Electronics

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