Hugh O'Keeffe’s Post

"Utilizing advanced silicon deprocessing and netlist extraction techniques, IOActive hopes to refine methodologies for extracting the configured AES keys required to decrypt the bitstream that drives the Spartan 6 FPGA." Check out our latest blog, 'Field-Programmable Chips (FPGAs) in Critical Applications – What are the Risks?' https://lnkd.in/g3Tk__bw

What’s involved in simulation of a complex SoC FPGA like Versal ACAP? #embeddededge #embedded

Learn how to get started with Signaloid's C0-microSD, a new FPGA system-on-module based on the Lattice Semiconductor iCE40 in a microSD form factor.

ICYMI: Check out one of our latest blogs, 'Field-Programmable Chips (FPGAs) in Critical Applications – What are the Risks?' Learn more on FPGAs and the risks that come along with using them. https://lnkd.in/g3Tk__bw

Introduction: AMD MicroBlaze™ V Processor The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD adaptive SoCs and FPGAs. The MicroBlaze V processor is based on a 32-bit RISC-V instruction set architecture (ISA). It allows developers to leverage the open-source RISC-V software ecosystem, is hardware compatible with the classic MicroBlaze processor, and is fully integrated in the Vivado™ and Vitis™ tools design flow. The MicroBlaze V processor is designed to be highly modular with a configurable architecture suitable for embedded systems applications. Developers can target the MicroBlaze V processor to any AMD adaptive SoC or FPGA device supported by the Vivado Design Suite at no extra cost. More information: https://lnkd.in/gXQW_iD2 Link for Microblaze: https://lnkd.in/gqjm4TMT #amd #xilinx #processor #riscv #fpga #soc #introduction #microblaze #softcore #configurable #vivado #vitis #designsuite #developers #softwaredevelopment #adaptive

What’s involved in the simulation of a complex SoC FPGA like Versal ACAP? AMD’s Versal Adaptive Compute Acceleration Platform (#ACAP) is a system-on-chip (#SoC) that that comprises different types of system blocks, each requiring an appropriate method of simulation. For example, the device’s architecture includes three groups of engines – Scalar, Adaptable and Intelligent – and many domain-specific IPs, such as PCIe gen 5, CCIX HBM and 600G cores. In addition, the Versal ACAP is the first AMD SoC FPGA to have a programmable network on chip (#NoC). Thankfully, a full system simulation environment can be created using #RivieraPRO and #QEMU that simulates #Versal ACAP’s programmable logic (PL), programmable software (PS), and #AI engines; all without physical/target hardware present. To learn about this full system simulation environment, you can: Watch our webinar: https://lnkd.in/eayX9PcU Read our blog: https://lnkd.in/dGnmgkfm Read an article we wrote for embedded.com: https://lnkd.in/e9Az4P9b Also, if you’re not currently using Riviera-PRO but would like to put the tool through its paces, you can request a free evaluation license for a fully functional version here: https://lnkd.in/eZMXdZKg #EDA #artificialintelligence #CoSimulation #DesignVerification #FPGA #FPGAdesign #FPGAdevelopment #FPGAsimulation #HeterogeneousComputing #SoCFPGA #versalacap

In this project, Adam Taylor demonstrates how you can create a simple health and usage monitoring system using a small AMD Spartan 7 FPGA and MicroBlaze V processor.

AMD has announced an FPGA-based accelerator card with ultra-low-latency Ethernet ports, specifically designed for high-frequency financial trading. Like all such cards, the Alveo UL3524 accelerator card pairs an FPGA with several high-speed, low-latency Ethernet ports, which terminate in four QSFP-DD cages. Each QSFP-DD cage is driven by eight GTF TX/RX transceiver pairs that terminate in the FPGA. The important specification for this card is the low Ethernet transceiver latency, which AMD claims is less than 3ns, which AMD claims is seven times better latency performance than “previous FPGA technology.” In financial technology (fintech) applications like high-speed trading, every added nanosecond of latency translates into profit losses. Big ones. #ultralowlatency #fpga https://lnkd.in/grCPR33G

Where is the Xilinx #Transformer / #Mamba implementation? The fact that Xilinx devices perform fewer TOPS than flagship NVIDIA GPU is made irrelevant by the fact that almost all DL tasks are memory bound. Correct me if I'm wrong, but my intuition tells me that implementing the KV-cache/Mamba Memory Hierarchy on FPGA is natural. The resulting model might be limited to small context length, but that shouldn't matter if it is more power and cost efficient. Low cost and power consumption are precisely what will bring ML into portable devices. Embedded ML deserves much more focus than it is receiving. I sense an FPGA Transformer / FPGA Mamba paper in our future 👀 Tri Dao #MLSys #EmbeddedML

“Adaptive Compute” with versal. Much more than an FPGA!