Intel Foundry has made significant strides over the past year as we continue to deliver on our goal of building a world-class systems foundry. Our ecosystem partners are critical to the success of Intel Foundry, so we’re continuing to work closely with all the key EDA and IP partners to enable customers to leverage our groundbreaking technology as they realize their AI ambitions. As part of these efforts, we just hit a new milestone with Ansys, Cadence Design Systems, Siemens, and Synopsys Inc announcing the availability of reference flows for Intel’s embedded multi-die interconnect bridge (EMIB) advanced packaging technology. EMIB technology is a key part of Intel Foundry’s approach to extending Moore’s Law, allowing us to cost-effectively scale to a larger silicon area by connecting multiple die in a single package. This news follows the momentum we announced at Direct Connect, with our ecosystem partners declaring readiness for Intel 18A designs. If you’re attending DAC 2024 this week in San Francisco, make sure to check out the Intel Foundry booth #2337 on the 2nd floor to see demos from four of our ecosystem partners. Learn more about how we’re building out Intel Foundry’s ecosystem: https://intel.ly/4cBl9cs
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Financial Cultural Operational and Technical Consultant - Alpha Sense Financial Consulting
1wWhen do you expect to reach parity in terms of yields. Ireland is reporting Intel 4 and 3 aren't ready for primetime. TSMC is at an average weekly ISO of 670. For a 12mm x 12mm die this translates to 120% more good die on 3nm. The process isn't well characterized and the TSMC folks say your at a local maximum They've comprehensively examined the response surface and feel they are near a global maximum and have better control of the E-test parameter and each layers critical dimensions have 6 sigma control. We reckon that you're at 4.2 for the 3nm, and haven't optimized the target CD's especially on the critical gate layer and ultra fine pitch metal layers. Also registration between layers with stacked tolerance is a big limiting factor to better CD's. What's the recovery plan to get economicallly viable utilization and yields. With equipment utilization at sub 50% and yields less than 45% your true over all productivity is less than 25%. TSMC has 90% utilization and approximately 85% yields they are realizing roughly 80% productivity in their 3nm factories. Our models show Foundry losses growing 12% Moreover your transistor density on 3nm is 25 to 30% lower and consumes 2.2x the power/transistor.