Exciting highlights from #DAC2024! We had a packed auditorium for Dr. Gary Patton’s keynote, "Systems Foundry—A Journey from 'System on a Chip' to 'System of Chips,'" reinforcing our message as the first systems foundry for the AI era. Also, on Monday, the team spoke about our silicon technology advantages and extended process technology roadmap. On Tuesday, we explored EMIB and Foveros technologies, highlighting their unique advantages. We’re proud of our team’s impactful presentations and looking forward to more innovations! Learn more about Intel Foundry here: https://intel.ly/3L1EpEd #61DAC #TechLeadership
When do you expect to reach parity in terms of ISO yields. Ireland is reporting Intel 4 and 3 aren't ready for primetime. TSMC is at an average weekly ISO of 670. For a 12mm x 12mm die this translates to 120% more good die on 3nm. The process isn't well characterized and the TSMC folks say your at a local maximum They've comprehensively examined the response surface and feel they are near a global maximum and have better control of the E-test parameter and each layers critical dimensions have 6 sigma control. We reckon that you're at 4.2 for the 3nm, and haven't optimized the target CD's especially on the critical gate layer and ultra fine pitch metal layers. Also registration between layers with stacked tolerance is a big limiting factor to better CD's. What's the recovery plan to get economicallly viable utilization and yields. With equipment utilization at sub 50% and yields less than 45% your true over all productivity is less than 25%. TSMC has 90% utilization and approximately 85% yields they are realizing roughly 80% productivity in their 3nm factories. Our models show Foundry losses growing 12% Moreover your transistor density on 3nm is 25 to 30% lower and consumes 2.2x the power/transistor.
Great to see you this week Gary and see all the incredible news coming out of Intel Foundry!
Hi Gary, Great job for wonderful presentation and incredible progress!
Corporate Vice President - General Manager, Design Enablement & General Manager, Components Research at Intel Corporation
2wVery proud to represent Intel Foundry and share how we are enabling the future through continued innovations.