International Symposium on Field-Programmable Gate Arrays (ISFPGA)’s Post

Reposting the call for participation for FPGA'24 (March 3-5 at Monterey, CA). On March 3, my student Hanchen Ye and I will give a tutorial to introduce 🎉 ScaleHLS-HIDA 🎉[HPCA’22, DAC’22, DAC’23, TRETS’23, ISPD’23, ASPLOS’24], a MLIR-based open-source HLS framework, which can compile HLS C/C++ or PyTorch model to optimized HLS C/C++ in order to generate high-efficiency RTL designs using downstream tools, such as Vitis HLS. Despite being fully automated and able to handle various applications, ScaleHLS-HIDA achieves a 1.29x higher throughput over a state-of-the-art RTL-based neural network accelerator on FPGAs. ScaleHLS-HIDA has been downloaded for >3000 times since 2022 from researchers around the world. This tutorial aims to enable attendees to use this tool and participate in its development. The system is open sourced at: https://lnkd.in/gpgFXxKK.

Some very interesting papers here. Tutorials on Neuromorphics, Intel and. AMD #AIML toolkits, and Spatial ML. The #ML papers include FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs from Tshinghua university. Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic from the institute of high performance computing in Singapore.

Our FPGA 2024 work SSR explores 𝐥𝐚𝐭𝐞𝐧𝐜𝐲 𝐯𝐬 𝐭𝐡𝐫𝐨𝐮𝐠𝐡𝐩𝐮𝐭 in transformer acceleration and achieves 3x latency improvement over SOTA low-batch transformer inference on GPUs. SSR Paper Link: https://lnkd.in/eVCYkEzu

One month ago, I had the chance of presenting my work on mixed-signal convolutional image sensors at the Custom Integrated Circuits Conference (CICC) organized by the IEEE Solid-State Circuits Society in Denver ! 😀 This work was conducted with my supervisor Prof. David Bol. In this paper, we present a convolutional image processor located next to the pixel array and based on mixed-signal computing. The two main novelties in terms of circuits are : 1. A circuit combining double sampling, to mitigate the effect of mismatch in the pixel array, image downsampling, to process the image at multiple scales, and voltage downshifting, to reduce the supply voltage from the pixel array to the processor 2. A switched-cap circuit calculating multiply-and-accumulate (MAC) operations in the charge domain, providing energy-efficient operations which are also accurate as they are robust to noise, mismatch, and process variations Interested ? 😀 Do not hesitate to check the paper on IEEEXplore (https://lnkd.in/e-dJU-6Q) or to contact me directly ! 😉

CPES Researchers win the 2023 IEEE EDS George E. Smith Award! Ming Xiao is lead author on the paper which won the George E. Smith Award - https://lnkd.in/gyvrTf8. “Robust Avalanche in 1.7 kV Vertical GaN Diodes with a Single-Implant Bevel Edge Termination” is available through IEEE - https://lnkd.in/egCR6k58. The article appeared in the October 2023 issue of Electron Device Letters (EDL) and was selected by the IEEE Electron Devices Society from almost 500 papers published in the journal in 2023. This prestigious award signifies a strong endorsement of the high quality of the research being reported. Co-authors are Yifan Wang, Ruizhe Zhang, Qihao Song, Matthew Porter, Eric Carlson, Kai Cheng, Khai Ngo and Yuhao Zhang. The award will be presented at the IEEE International Electron Devices Meeting (IEDM) in San Francisco, CA. Congratulations to all authors! #CPES #galliumnitride #GaN #semiconductordiodes #junctionterminationextension

Very nice work out from collaborators at the University of Wisconsin-Madison demonstrating the utility of modulated longitudinal coupling for reading out solid-state qubits. Check it out👇. https://lnkd.in/eCFr58eA We’ve been working on these concepts since at least 2016 so nice to see the ideas validated in real life. This approach to readout not only promises to enhance readout speed and fidelity but allows you to design quantum computer architectures where the qubit has a very small frequency relative to the readout circuit (or vice versa!) which is really important for new types of protected qubits headed your way. https://lnkd.in/e35MBH4K https://lnkd.in/ehsTBqZV https://lnkd.in/eT88P_i5

Our paper, "NOVELLA: Non-Volatile Last-Level Cache Bypass for Optimizing Off-chip Memory Energy," has been accepted at CASES 2024, part of the Embedded Systems Week (ESWEEK). ESWEEK is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. Additionally, we have the unique opportunity to publish our paper in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). Cheers to my co-authors, Ohm Rishabh and Preeti Ranjan Panda! In this work, we investigate how bypass policies for NVM LLCs, aimed at enhancing overall system throughput, can negatively impact off-chip memory energy consumption—a critical bottleneck in modern SoCs. NOVELLA effectively exploits the trade-off between LLC contention and reuse to optimize overall consumption of off-chip memory energy by creating a balance across its different energy components. We look forward to sharing our findings and engaging with fellow researchers at ESWEEK!

Just published: a multigrid method to accelerate electromagnetic solvers based on the MoM/integral equations. Yongzhong Li and Damian Marek demonstrate 16x CPU time savings compared to AIM for a real bus from a commercial IC. https://lnkd.in/g-_wn_E3 Thanks to AMD, Natural Sciences and Engineering Research Council of Canada (NSERC), CMC Microsystems for their support. IEEE Transactions on Antennas and Propagation

Excited to share that our paper titled "QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding" is now available for Early Access at IEEE TCAD. This is the first work that demonstrates Quantum Equivalence Checking with Quantum Error Correction Embeddings. https://lnkd.in/dMwAB8ud

I am thrilled to share that our paper titled "Joint Delay-Doppler Index Modulation for Orthogonal Time Frequency Space Modulation" has been accepted for publication in the prestigious journal IEEE Transactions on Communications! In this work, we have proposed a subframe-based index modulation technique for OTFS modulation. Our aim is to design a block-wise IM scheme to extend the activation strategy to both delay and Doppler bins (active resource blocks) within a subframe for an OTFS frame. The proposed OTFS frame can simultaneously contain subblocks that convey information symbols in delay or Doppler bins. This innovative approach allows us to transmit an additional bit by leveraging the dimensionality of active resource blocks. I would like to extend thanks to my dear advisor, Prof. Dr. Ertugrul Basar, for his guidance and support. The Early Access version: https://lnkd.in/dgSaiEpJ #ieee #comsoc #wirelesscommunications #otfs #5G #6G IEEE Communications Society #WirelessNetworks