John Round’s Post

Having used Imperas tools on two or three RISC-V designs, I can say it was clunky and somewhat dysfunctional - I was voting for a tighter coupling with RTL simulation rather than hand-crafting models of ISA extensions in C (which gives you twice as much to verify). Having worked at Synopsys on VCS related things, I would say the chance of seeing that integration is now zero. If you want an Imperas replacement tool environment that's mostly open-source for doing ARM, X86 or RISC-V processer extensions, I can do that for you. I might even throw in RF modeling for end-to-end wireless verification ;-) #RISCV #EDA #Verilator #Chiplets https://lnkd.in/gm7vCQn5

Exciting Times for Embedded Engineers in the USA! 🚀 RISC-V Gains Momentum with Companies Like Synopsys Embracing the Open Standard. Discover the Benefits and Innovations Unveiled at the North America RISC-V Summit. #EmbeddedSystems #RISCV #Innovation"

A Brave New World of Emulation and Software Prototyping https://lnkd.in/en2RfV5x The guys and gals at Siemens have just announced not one, not two, but three new families of congruent ASIC/SoC emulation and software prototyping solutions that bring tears of joy to my eyes.

https://lnkd.in/gXcvPFSN RISC-V experts discuss the corrective actions required in current RISC-V chip verification process. In my multifacted roles with both hardware and software stacks, minor issues can have a snowball effect increasing cost and time over the full product development lifecycle. #chip #chipverifications #riscv #risc #RTL #simulation #emulation #PreSiliconValidation #postsiliconvaldation

Introducing global assertion control in runtime to #Verilator. Find out how it can simplify your verification test suites and read about future considerations for more granular control: https://lnkd.in/dC2WY_Sb CHIPS Alliance #ASIC #FPGA

I've just uploaded a new article on C++ modelling of SoC systems (https://lnkd.in/ea3PZyjm). This is part 1 of a set of 2. In this article I introduce the subject and then look at methods for modelling the "processing element" on which embedded code can run. This might take the form of a virtual generic processor or a processor cycle accurate ISS model. The processor models have basic memory read and write capabilities, and the ability to model nested interrupts. Timing modelling and debugging are also discussed as well as modelling for multiple cores. This is just one (if important) element of an SoC and in the next article I will look at modelling busses/interconnects, memory sub-systems, timers and other peripherals for serial and high-speed interfaces etc., as well as external connection to other programs to extend the model capabilities with things like connection with third party models, or co-simulation with logic. #modelling #embeddedsystems #embeddedsoftware #cpu #processor #microprocessors #simulation #iss #softwarearchitecture

Three simple lines is all you need to simulate with Vivado simulation libraries (unisim, etc). Same API no matter which simulator you use (commercial or open-source). Detects when a re-compile is needed or not. Compiles in just 8 seconds with GHDL! #fpga #vhdl #verilog #systemverilog #amd #xilinx #vivado #simulation #verification #ci

ChipNeMo: Domain-Adapted LLMs for Chip Design #nvidia basically compressed 30 years of its corporate memory into 13B parameters. Their greatest creations add up to 24B tokens, including chip designs, internal codebases, and engineering logs like bug reports. Let that sink in. The model "ChipNeMo" is deployed internally, like a shared genie: - EDA scripts generation. EDA stands for "Electronic Design Automation", a core software suite for designing the next-gen GPUs. These scripts are the keys to a $1T market cap 🦾; - Engineering assistant chatbot for GPU ASIC and Architecture engineers that understands internal hardware design specs and is capable of explaining complex design topics; - Bug summarization and analysis as part of an internal bug and issue tracking system; - Domain-finetuned retriever that achieves much better accuracy over internal knowledge. A whitepaper to share ChipNeMo's creation process: https://lnkd.in/gssvgyP5 Official blog: https://lnkd.in/gQ6AbMF8

🚀 Day 22 of the #Verilog30DaysChallenge with #HDLBits Finite State Machines Simple FSM 1 (asynchronous reset) Simple FSM 1 (synchronous reset) Simple FSM 2 (asynchronous reset) Simple FSM 2 (synchronous reset) #Verilog #FPGA #HardwareDesign #Engineering #CodingChallenge #LearnVerilog #TechCommunity #30DayChallenge #HDLBitsChallenge #vlsi