Lup Yuen Lee’s Post

** Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core #riscv https://lnkd.in/dRu2mbdJ

Public Key Encryption using Learning With Errors (LWE) https://lnkd.in/gB-zrit

#HowTo: Dive into the world of cutting-edge technology with this fascinating blog from Codasip! Learn all about effectively hiding sensitive data with #RISCV Zk and custom instructions ➡️ https://hubs.la/Q02lSdBs0 #RISCVeverywhere

REx: Rule Explorer project and Detection Engineering Threat Report (DETR) If you found LoFP from http://lolol.farm useful, this provides significantly more insights via a much more powerful platform (built on the Elastic stack!) CC: @br0k3ns0und #elastic #threatradar #threatintelligence #edr #detection #threat

MultiDump - Post-Exploitation Tool For Dumping And Extracting LSASS Memory Discreetly https://lnkd.in/d3r93MEK

🚀 Day 16 of the #100daysRTLChallenge: Ensuring data integrity with a 3-bit Even Parity Checker! 🧮 ## What Is an Even Parity Checker? An even parity checker is a digital circuit that verifies whether a given binary data word has an even number of 1s. It's like having a vigilant guardian for your data, ensuring it remains accurate during transmission. ## How Does It Work? - For a 3-bit input, the even parity checker examines the data bits. - If the total number of 1s is even, it confirms that the data is error-free. - If the number of 1s is odd, it raises an alarm, indicating a potential error. ## Practical Applications: - Even parity checkers are used in: - Communication systems to validate transmitted data. - Memory storage devices to ensure reliable data storage. - Digital systems where data accuracy matters. Remember, even parity checkers are the gatekeepers of data reliability! 🌟 #digitalcircuits #vlsi #verilog #digitalLogic #PublicLearning #EngineeringJourney #vivado #hdlLearning #ECE #VLSI

I am pleased to announce the completion of a project :"Computer Vision board (CVB)" , which I consider a significant milestone in advanced computer vision results analysis. Through this project , I developed auxiliary algorithms to achieve multiple objectives simultaneously, including tracking, counting, timing, and impact assessment. I appreciate your support. Anyone interested in applying this project to their work is welcome to contact me. I assure you that it will be open-source in the near future. #ComputerVision #Object_Clustring #Object_Detection #Object_Counting #Object_Tracking #Advanced_CV #Object_Classification #ML #MLOPS #Tracking_Analysis

Day-17 of #100DaysOfRTL Challenge: Parity Generator and checker Parity generators and checkers are essential components in modern digital systems, providing a straightforward yet effective method for error detection. Their applications span various real-world scenarios, from ensuring data integrity in network communications and memory storage to enhancing the reliability of peripheral device interactions. Understanding and implementing parity logic is crucial for designing robust digital systems capable of handling and mitigating data errors efficiently. CheckOut my Github Repository: https://lnkd.in/g8aVHwn6 #DigitalDesign #Verilog #ErrorDetection #RTL #100DaysOfRTL #LearningJourney

When I look at the logs on my website, the clog2() Verilog-2001 function is the most searched query. This implementation deals with a quirk of Vivado to reduce warnings. It's useful to compute address and counter widths from other parameters. https://lnkd.in/gGGVUWyT

Polymorphic Memory Resources - Worth Using? https://lnkd.in/eraDnjBu #cpp #cplusplus