Pratiksha Kulkarni’s Post

🏵 🏵 Which of the following constraints ensures that x and y are consecutive even numbers? A. constraint c { (x % 2 == 0) && (y == x + 2); }   B. constraint c { (x % 2 == 0) && (y % 2 == 0) && (y == x + 2); }   C. constraint c { (x - y == 2) && (x % 2 == y % 2); }   D. constraint c { (x - y == 1) && (x % 2 == 0); } Comment the right options below 👇 👇 🤷♀️ 🤷♀️ Keep in mind there may be chances of having more than 1 option correct, carefully select the answer... Thank you 😊 Let's learn Let's shine 🌟 #digital #vlsi #systemverilog #sv #asic #uvm #fpga #constraints #semiconductor #verilog

🍒🍒 When defining constraints in SystemVerilog, which of the following would allow the variable `x` to be within the range 10 to 20, but only if the variable `y` is greater than 5? A. constraint c { if (y > 5) x inside {[10:20]}; } B. constraint c { y > 5 -> x inside {[10:20]}; } C. constraint c { y > 5 implies x inside {[10:20]}; } D. constraint c { y inside {[6:15]} && x inside {[10:20]}; } Comment the right option below 👇👇👇 Thank you Let's learn Let's shine 💫 #digital #verilog #systemverilog #uvm #vlsi

⭐ ⭐ Types of modes of UVM Drivers ⭐ ⭐ 1. Push mode 2. Pull mode 1. 🏹 Push mode: Driver Role: In this model, the driver actively pushes transactions from the sequencer onto the DUT (Device Under Test). Mechanism: The sequencer generates transactions and sends them to the driver. The driver then processes these transactions and drives them to the DUT. Usage: In Push mode, "uvm_push_sequencer" is connected to "uvm_push_driver". 2. 🏹 Pull mode: Driver Role: In this model, the driver pulls transactions from the sequencer. Mechanism: The sequencer queues transactions, and the driver retrieves these transactions as needed. The driver then processes the pulled transactions and drives them to the DUT. Usage: In Pull mode, "uvm_sequencer" is connected to "uvm_driver". Summary: Typically we use "Pull mode" type of UVM driver. Thank you 😊 Let's learn Let's shine ✨ #uvm #systemverilog #digital #verilog #vlsi #asic

✨ Constraint for Binary to Gray code conversion!!! Any alternatives for this please feel free to comment it 😀 #constraints #digital #verilog #systemverilog #uvm Thank you!! Let's learn let's shine ⭐

💫 Here's a overview of APB protocol: Advanced Peripheral Bus (APB) Protocol 1. Overview: The APB protocol is a low-power, low-bandwidth protocol designed for connecting simple peripherals to a microcontroller or System-on-Chip (SoC). It is commonly used in embedded systems where power efficiency and simplicity are important. 2. Clocking: APB uses a single clock for both read and write operations. This clock is typically derived from the system clock but runs at a lower frequency to conserve power. The clock signal is used to synchronize data transfers between the microcontroller and the peripherals. 3. Data Width: APB supports various data widths, but it is most commonly used with an 8-bit data bus. This means that data transfers occur in 8-bit increments, making it suitable for transferring small amounts of data at a time. 4. Addressing: APB uses a simple addressing scheme to access peripherals. Each peripheral is assigned a base address, and additional registers within the peripheral are accessed using offsets from this base address. This allows multiple peripherals to share the same address space, simplifying the design of the system. 5. Read and Write Operations: APB supports separate read and write operations. When a write operation is initiated, the microcontroller places the data on the bus along with the address of the peripheral register to be written to. The peripheral then latches the data on the rising edge of the clock signal. Similarly, in a read operation, the peripheral places the data on the bus, and the microcontroller reads it on the rising edge of the clock. 6. Handshaking: APB uses a simple handshaking mechanism to control data transfers. The peripheral asserts the PREADY signal to indicate that it is ready to accept data or provide data. The microcontroller asserts the PSEL signal to select the peripheral it wants to communicate with. The PENABLE signal is used to indicate that a valid transfer is taking place. 7. Synchronization: APB does not require complex synchronization mechanisms between the microcontroller and the peripherals. The use of a single clock signal ensures that both the microcontroller and the peripherals operate in sync, simplifying the design of the system. 8. Power Efficiency: APB is designed to be power-efficient, making it suitable for use in battery-powered devices and other low-power applications. By using a lower frequency clock and simple handshaking mechanisms, APB minimizes power consumption while still providing adequate performance for many applications. In summary, the APB protocol is a simple, efficient, and power-efficient protocol for connecting simple peripherals to a microcontroller or SoC. Its simplicity and low power consumption make it a popular choice for many embedded systems. Thank you!! Let's learn let's shine ⭐ #vlsi #digital #verilog #sv #uvm #systemverilog #vhdl #protocols #semiconductor #electronics #amba #busprotocols

Hello everyone 😀, Many times I studied about "Constraints" , Still I missed one or other types of it. So, I searched and jotted down ✍ types of constraints with 1 line definition for it. I deliberately didn't gone deep into it, to keep the post short and simple. 😇 ✨ Here's the list of "Types of Constraints" 1. Inside constraint: Constrains a value to be within a specified range or set. 2. Weighted distribution constraint: Specifies the probability distribution for choosing values. 3. Implication constraint: Defines a logical relationship where one condition implies another. 4. If else constraint: Conditionally enables or disables a constraint based on another condition. 5. Equality constraint: Constrains two values to be equal. 6. Bidirectional constraint: All constraints are bidirectional it is called so, because it works parallely. 7. Static constraint: When a static constraint is turned on or off and when used the constraint is turned on and off in all instances of class. 8. Foreach constraint: Constrains the iteration over elements of a collection. 9. Inline constraint: Specifies that a constraint should be solved at the point of use. 10. Solve before constraint: Specifies the order in which constraints should be solved. 11. Soft constraint: Defines a constraint that is a preference but not a requirement. 12. External constraint: Constraints written outside of class using 'extern' keyword. 12. Disable constraint/randomization: Temporarily deactivates a constraint/randomization. [Turn on and off] 13. Randcase constraint: Specifies a random selection of cases in a constraint. PS: If I missed any of them please put it in the comments section, it will be a great help. 🤝 Thank you 😊 Let's learn, let's shine 🎇 #vlsi #systemverilog #constraints #uvm #asic

Suppose you have a class "Matrix" that contains a 2D dynamic array "data" of integers and a method "getData" that returns a reference to "data". If you perform a shallow copy of an object of type "Matrix" and modify the data in the copied object, how will it affect the original object? #systemverilog #uvm #dv #shallowcopy #deepcopy

🔧 Flexible Coding Made Easy: Polymorphism in SystemVerilog 🔧 Ever wondered how hardware designers make their code flexible and reusable? The answer is through polymorphism in SystemVerilog! 🔹 What is Polymorphism? Polymorphism in SystemVerilog is a powerful concept that allows for flexible and reusable code. It is primarily achieved through method overriding, which allows a subclass to provide a specific implementation for a method that is already defined in its superclass. 🔹 Implementation in System Verilog: To implement polymorphism, you use method overriding as said earlier. Also you define a method in a base class as 'virtual', you use 'extends' keyword (Inheritance) in subclass to override and redefine superclass method with a new implementation. This allows each subclass to have its own version of the method. For this both base class and subclass "method name" should be same and we should assign handler of base class to superclass. 🔹 Why Does it Matter? Polymorphism makes your code more flexible and easier to change. If you want to add a new subclass with a different properties in a method, you just create the new class and your existing code can still use it without any changes. So, next time you're designing hardware, remember that polymorphism can be your best friend for writing clean and reusable code in SystemVerilog! 🍒 🍒 Refer to the below code to understand polymorphism in more detail. Play with the code modify and remove virtual and check and understand it deeply. Thank you 😊 Let's learn, let's shine 🎇 #systemverilog #polymorphism #hardwaredesign #flexiblecoding #vlsi #vlsidesign #digitaldesign #oopsconcepts #oops #verilog #uvm