RunTime - Engineering Recruitment’s Post

The electronics industry is all about #optimization - cramming more and more functionality into a single chip. For example, in 2012, the industry saw its first #SoC #FPGA - an SoC with a hard processor core working alongside traditional FPGA fabric. Since then, devices have been getting increasingly complex; with AMD’s Versal Adaptive Compute Acceleration Platform (ACAP), announced in 2022, building on the capabilities of the company’s popular Zynq 7000 and MPSoC families. #Versal ACAP introduces a programmable network on chip (NoC) and three dedicated groups of engines: scalar engines, adaptable engines, and AI engines (AIE - a combination or AI/ML and signal processing chipsets for functions and workloads that need vector processing, domain-specific parallel processing, and high compute efficiency). It’s an impressive device. And large too when you consider that one of the devices in the Premium series (the V1902) has 8.4 million look-up tables (LUTs) and 18.5 million system logic cells. However, just because we have a target with plenty of space for software to run and for functionality to be described at the register transfer level (RTL) our designs still need to be optimized for performance and power. They also need to be thoroughly verified and in our latest blog post ‘Versal ACAP Simulation Challenges’ we explain how. https://lnkd.in/dGnmgkfm. Also, through the blog post, you can access a recording of a webinar we gave on the same subject. Follow us and be sure not to miss out on notifications on other webinars, product launch news and tool tips. #AMD #RivieraPRO #XilinxFPGA #AMDFPGA #EDA #rtldesign #QEMU #FPGASoC #FPGAsimulation #fpgaverification #XilinxFPGA #AMDFPGA

Hardware in the loop targets are devices designed for running real-time simulations. To achieve small time steps they use a combination of powerful processors and big #FPGA. The Speedgoat Performance real-time target features a #Xeon #microprocessor with a FPGA module connected over #PCIe. In this article I show you how to use this interface to share data in real time between the FPGA and the microprocessor. Check it out! https://lnkd.in/dkMRcf5N

"Digital design and verification workloads are growing larger as chips expand in size (or take on multi-die architectures). Yet, time-to-market goals continue to be aggressive. 4th Gen AMD EPYC processors with AMD 3D V-Cache technology are ready to take on the demands, delivering scalable performance as well as energy efficiency for cloud-native computing workloads. Through our longstanding collaboration with AMD, Synopsys digital design and verification flows are optimized to run on AMD EPYC 9004 processors, enabling chip designers to do more with their engineering resources and with greater energy efficiency." #amd #epyc #synopsys https://lnkd.in/gu2AHxhM

Fidus shares insights from Spencer Chin's latest article on Design News, showcasing Lattice Semiconductor's pioneering move into mid-range FPGAs with the Avant-G and Avant-X. As Fidus, we're impressed by Lattice's strategic expansion, addressing the surging demand across global FPGA developers. With over 50,000 developers in its ecosystem, Lattice Semiconductor continues to redefine possibilities in communications, computing, and more. The Avant-G and Avant-X not only meet but exceed expectations, offering unmatched versatility and advanced features. #Fidus #FirstTimeRight #FPGAInnovation #LatticeSemiconductor #FidusPerspective Dive into the full article:

⚡ FPGA (Field-Programmable Gate Array) is becoming a key player in the evolution of optical interconnects. But how is this transformative technology reshaping the way we connect and communicate? Design News takes a closer look at how FPGA is turning the tables on optical interconnects. It explores the innovative strategies and applications that are making optical communication faster, more efficient, and highly adaptable to the ever-growing demands of modern technology. Check out the full article here: https://lnkd.in/eNThYMNG #FPGA #OpticalInterconnects #Technology

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Continuing with our thematic focus on FPGA, this week we are exploring the benefits of Video Direct Memory Access (VDMA) for video processing workflows. 🎬 We guide you through the whole process and explain the key benefits of using VDMA instead of DMA. Check it out! ⬇️ #FPGA #vdma #vitis #vivado #videoprocessing #ProtostarLabs

Ayar Labs Showcases 4 Tbps Optically-enabled Intel FPGA at Supercomputing 2023 Delivering 5x more I/O bandwidth, up to 20x lower latency and 5x more power efficiency than current generation offerings¹, and enabling new disaggregated system and memory architectures for HPC and AI

Check out our latest blog post on VDMA implementation and testing on FPGA. 👇

We are thrilled to hear that the #BeagleV Fire was unveiled at the #riscv Summit last week. 🎉 The BeagleV Fire is a beginner-friendly board that features the #PolarFire #SoC #FPGA from #Microchip Technology. It is a great way to get started with the RISC-V architecture and the FPGA fabric in a low-cost and low-power platform. 👍 But if you are ready to take your FPGA-SoC design to the next level, we have the perfect products for you: the #PolarBerry and the #SOM1-SoC. 😃 These are two System-on-Modules (SoMs) that are based on #PolarFire SoC FPGA, but with different features and specifications. They are also very similar in size to the BeagleV Fire. ✅ The attached table shows the differences between the BeagleV Fire, the PolarBerry, and the SOM1-SoC. As you can see, the PolarBerry and the SOM1-SoC have FPGAs with more resources, such as logic elements, memory, I/Os, and SERDES channels. 📊 They are suitable for applications that require more performance and functionality, such as industrial automation, edge computing, smart home, aerospace, defense, medical, and automotive. 🏭📡🏠🚀⚕️🚗 The SOM1-SoC is the most advanced product among the three. It has the largest FPGA fabric, the most memory, the most I/Os, and the most SERDES channels. 🥇 It also has a memory attached to the FPGA fabric and a high number of SERDES for when the high-speed I/Os are critical. It is ideal for applications that require high processing power and bandwidth, such as video processing and machine learning. 🎞️🤖 Both the PolarBerry and the SOM1-SoC have flexible clocking on board to allow FPGA core designers the ability to use them for very accurate timing. They can adjust the clock frequency and phase to meet the specific requirements of the FPGA logic and the IO cluster. ⏱️ They can also use external clock sources and PLLs to generate multiple clock domains and signals. 🔀 Both the PolarBerry and the SOM1-SoC are production-ready SoMs that can be used in products as they are. They have been tested and certified to meet the highest standards of quality and reliability. 👍 They also come with comprehensive documentation and support to help you get started and succeed with your projects. 📚💪 If you are interested in learning more about the PolarBerry and the SOM1-SoC, please visit our website or contact us. 💻📞 We would love to hear from you and answer any questions you may have. Thank you for choosing us as your partner in FPGA-SoC design. 🤝 #FPGA #SoC #RISCV