TIRIAS Research’s Post

Great article by Semiconductor Engineering's Brian Bailey on one of the hot industry topics - 3D-IC - arguing that "3D-ICs May Be The Least-Cost Option." Advanced packaging has evolved from expensive custom solutions to those ready for more widespread adoption. "This is especially true if the industry gets to super-NoCs, hierarchically designed across chiplets, which would mean top-down design. This step is akin to co-designing various chiplets that need to work together, primarily adopted for highly complex chiplet-based structures, less in an ecosystem of a third-party chiplet market. From a top-down perspective, participants in a chiplet ecosystem need to plan out far into the future, not unlike IP players today, to understand the requirements dictated by the end applications the chiplets are designed for.” It was great to be part of the conversation with Siemens EDA (Siemens Digital Industries Software)'s Vidya Neerkundar, Ansys' Marc Swinnen, and Synopsys Inc's Kenneth Larsen. #Arteris #NetworkOnChip #SoCIntegrationAutomation #Chiplets #SystemOnChip #Semiconductor #ArtificialintelligenceAI #PhysicallyAwareNoC https://bit.ly/3T49752

At advanced semiconductor nodes, traditional 2D design rule checking (DRC) often misses critical hot spots. Luckily the SEMulator3D® virtual fabrication platform presents a potential solution to better identify 3D failures, cut costs, and reduce reliance on wafer-based experiments. The Lam Research blog dives into the large area analysis process using SEMulator3D®. #LifeAtLam

At advanced semiconductor nodes, traditional 2D design rule checking (DRC) often misses critical hot spots. Luckily the SEMulator3D® virtual fabrication platform presents a potential solution to better identify 3D failures, cut costs, and reduce reliance on wafer-based experiments. The Lam Research blog dives into the large area analysis process using SEMulator3D®. #LifeAtLam

Semiconductor chip packages are getting more complex every day, and this complexity brings more challenges in terms of performance, integration and reliability. The shift towards more sustainable products and an increase of demand outside of the classical applications push us to develop new workflows capable of addressing the most common issues in these fields. This LIVE webinar will dive into the latest #SIMULIA solutions for #semiconductors, highlighting workflows such as ECAD Translation into CAE, PCB level modeling, Signal Integrity, Power Integrity and more. I hope you'll join us!

The Siemens EDA tools are ready for Cryogenic CMOS design using Semiwise cryogenic PDK strength compact models.   According to a recent Siemens press release the Siemens’ Analog FastSPICE platform, powered by technology from Siemens’ Analog FastSPICE eXTreme™ platform and the Siemens’ Solido Design Environment were adopted for using the unique Semiwise PDK strength cryogenic compact models. They will be initially deployed by Surecore to develop cryogenic CMOS IP in the framework of the £6.5M Innovate UK Cryogenic CMOS project.   https://lnkd.in/eZcGZ44t   Semiwise has developed unique design strength PDK cryogenic compact models for the GLOBAFOUNDRY 22FDX process. The models cover all aspects of the room temperature 22FDX PDK models including corners, statistics, layout effects. They can be used in the standard analogue and digital CMOS design flows for both design and verification at sign-off. The models are the only PDK strength cryogenic compact models commercially available at this point of time.   The models are develop using a patented Semiwise technology based on single wafer measurements and comprehensive use of TCAD simulations. The measurements are performed by Insize. The TCAD simulations are performed with Sentaurus process (Synopsys) and the compact model extraction is performed with the TCAD-to SPICE Synospsy tool chain.   https://lnkd.in/eTybYJV3   The applications of the cryogenic models and design tools is in the development of CMOS circuits and chip for quantum computing and for cold (77K) CMOS aiming to reduce the power consumption of large data centres.

To provide long-term gains at a similar rate to Moore’s Law, chips must go vertical. Heterogeneous 3D-ICs are the real goal, with 2.5D being a learning technology with training wheels. There are good reasons why full 3D was not attempted first. “The top three problems are thermal, thermal, and thermal,” says John Park, product management group director in the Custom IC & PCB Group at Cadence. “We can stack these things all day long, and you see examples of L3 and L4 cache getting stacked on logic. That is only possible because cache doesn’t generate a lot of heat. We also see examples where they take full wafers and stack them, but those require exotic fluid-cooled packages. TNO’s state of the art 2-phase micro fluidic cooling as an embedded solution for direct in-chip cooling may just be the answer the thermal challenges mentioned here in above article. Reach out to us for more information. https://lnkd.in/eB4D5v8F #TNO #Micro #Cool #Thermal #management #Heat #Dissipation #embeded #Integrated #Solution.

SEMI #3D and Systems Summit to Spotlight Trends in Hybrid Bonding #technologynews #electronicsenws #electronics #technology #electronicsera