INTEGRATION, the VLSI journal 44 (2011) 242255

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INTEGRATION, the VLSI journal

Power efcient multi-stage CMOS rectier design for UHF RFID tags$
Shu-Yi Wong, Chunhong Chen n
Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada N9B 3P4

a r t i c l e i n f o
Article history: Received 5 April 2010 Received in revised form 7 March 2011 Accepted 8 March 2011 Available online 17 March 2011 Keywords: RFID Low power Differential-drive rectier

a b s t r a c t
Power efciency of a UHF rectier circuit, which is part of long-range IC-based passive RFID tags, has become a serious bottleneck in implementing power-hungry intelligent sensors. This paper presents an analytical approach for multi-stage rectiers, which provides design tradeoffs as well as a set of design rules to improve power efciency of the rectier. As an example, three-stage rectiers are designed with ST 90 nm CMOS technology for optimized performance at both 10 and 22 m distances. When compared with existing results at the same level of output power, the proposed rectiers show a 3 better performance in power efciency (73%) and 55% reduction in power-up threshold with longer operating range. & 2011 Elsevier B.V. All rights reserved.

1. Introduction Passive radio-frequency identication (OR RFID) tags are a class of RFID devices that obtain the power solely from the incident radio frequency energy [3,4,10]. Some of them fulll the function as bar-code replacements with no need for sophisticated power harvesting schemes due to their low power consumption of a few micro-Watt [4]. RFID applications for the auto industry (such as remotely powered intelligent sensors), however, require power of at least an order of magnitude higher while maintaining a long detection range. It is, therefore, necessary for these sensors to have a highly efcient power supply. To this end, the focus is on design of the tags analog front-end circuit and, in particular, rectier for power extraction. Due to the relatively higher regulatory limit for equivalent isotropic radiative power (PEIRP) of 4 W, the operating frequency of 915 MHz is desirable for the UHF RFID, which offers a good balance between detection range and available power. Conventional rectier circuits are based on the Dickson multiplier topology [2,5,6,8], where the MOS transistors are used in the diode-connected mode. These circuits suffer from inferior power conversion efciency (PCE) due to the forward voltage drop which should be greater than transistors threshold voltage (Vth). While process enhancements help solve the problem [11,18], a variety of circuit design methods have achieved better performance with standard process by introducing a gate bias to reduce the effect of Vth. Examples include the external threshold-voltage cancellation (EVC) [6], internal threshold-voltage cancellation (IVC) [5], and self threshold-voltage cancellation (SVC) [7]. An

$ This work was supported in part by the AUTO21 Network of Centers of Excellence, Canada. n Corresponding author. E-mail addresses: [email protected] (S.-Y. Wong), [email protected] (C. Chen).

extreme case is the use of zero-threshold transistors [2] with which, however, comes signicant amount of the reverse leakage that degrades the power efciency. To address the conicting issues of reducing both forwardvoltage drop and leakage, a recent study on differential-drive CMOS rectier [1] shows a much higher PCE (up to 66%) than previous works on the same subject [16]. Apart from the absence of design methodology, the above study only applies to a singlestage rectier. In general, more stages are needed for a practical tag in order to produce a sufcient output voltage. While a threestage rectier has also been designed [3], the reported PCE is only 24% with little or no room for improvement due to the conicting requirement of bandwidth and detection range. Traditionally, cascading of stages tends to degrade the power efciency due to the body effect of transistor. However, as we will see later in this work, this is not necessarily the case. Meanwhile, existing design methods attempt to minimize the power consumption for a given output power using a linear model of the rectier. While the linear assumption does simplify the design by associating some design metrics with the PCE, it is only valid for the case of low efciency where linear parasitic components dominate [3]. In this work, we aim to maximize the rectier output power for a given operating range instead, with the proposed piece-wise linear model of the rectier which is applicable for high PCE operation. We develop a new design methodology for multi-stage rectiers which promise the high PCE. Also, we show that the output voltage at individual stages, when well controlled, plays an important role in improving the rectiers PCE. The rest of the paper is organized as follows. Section 2 provides an overview of the proposed design method with brief description of main contributions of this work. Section 3 presents an analytical model for multi-stage differential-drive CMOS rectiers with discussions. The contour analysis shown in Section 4 identies the rectiers optimal operating conditions. Section 5 is

0167-9260/$ - see front matter & 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2011.03.005

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devoted to developing a piece-wise linear approximation model for the rectier. With this model, the matching theory for a piecewise linear load is discussed in Section 6. Section 7 looks at design considerations with tradeoffs among the bandwidth, operating range and technology process. Section 8 proposes our design for three-stage differential-drive CMOS rectiers, followed by simulation results and conclusions given in Sections 9 and 10, respectively.

which is dened as PU PL PA 2

where PA is the available power from the antenna, given by [14] PA PEIRP l G 4pr 2 4p
2

2. Overview and main contributions This section begins with description of general design problems for differential-drive CMOS rectier circuits along with some denitions, followed by an outline of the proposed design method and main contributions of this work. 2.1. Design problems for power efcient rectier Fig. 1 illustrates the block diagram of a UHF rectier [17], where the incident RF energy is rst converted to electrical power by the antenna. The matching network is responsible for controlling the voltage and current of this power in such a way that the highest possible portion of the power can be delivered through the rectier to the load under desired conditions. The rectier circuit converts the incoming AC power into DC power at the output where there is usually a shunt voltage regulator for stabilizing the voltage for the load. In this work, we only study the differential-drive CMOS rectier and the matching technique. The antenna is assumed to have resistive impedance with an innite bandwidth. To facilitate calculations, we also assume a simple half-wave dipole antenna with an impedance of 73 O and antenna gain of 1.64. The choice of such a narrowband antenna may not be optimal, but it serves as a vehicle for development of a theory that is equally applicable for other antennas with different impedance and gain. For the matching network, we use a simple off-chip rst-order L-match network since our goal is to explore the potential of obtaining high power efciency for the rectier. An off-chip matching network is typically not an issue because it can be easily integrated with the antenna, which has to be off-chip anyway due to its physical size for the operating frequency under consideration. An off-chip matching network provides additional design exibility while supporting higher Q and larger component values, which would otherwise be impossible for a chip-integration solution. Prior to further discussions on design problems, some denitions are given below. First, the PCE is used exclusively to represent the rectiers power efciency as follows [3]: PL PCE PR 1

where PEIRP is the equivalent isotropic radiative power of the source, r is the distance between the tag and the source, l is the wavelength of the incident RF energy and G is the antenna gain. Design of a power efcient rectier involves (a) maximization of PCE through the well-designed rectier and (b) maximization of PU by making PR as close to PA as possible through proper matching. Traditional design methods [57,9] have demonstrated how the transistors on-resistance could affect the rectiers efciency. Therefore, the natural step for boosting the latter is to reduce the diode-drop, or the voltage across the resistors. Ideally, the efciency would become very high when the voltage drop approaches zero. In reality, this does not happen because a close-to-zero voltage drop would mean that the transistors are turned off most of the time, and that there is very little power being transferred to the load. In this case, the off-resistance due to substrate loss and channel leakage becomes dominant [2,3]. The benet of analyzing the voltage drop is the result of its linearity in both high and low values, in alignment with the linear model of power matching. However, the high PCE of CMOS differential-drive rectier [1,12] is a good reminder that the rectier is non-linear in nature. Intuitively, it should operate most efciently when the power is transferred via the non-linear transistor switches to the load, instead of being dissipated in the turn-on or parasitic resistance. This represents the demand for a non-linear matching model for the rectier. Also, under such a non-linear condition, it is of interest to nd the efciency and to determine where its upper bound may lie. Our approach starts with an analytical model, which provides a set of salient efciency-determining parameters while a fully analytical solution is not available due to the models complexity. It is found that by xing these parameters, rectier circuits remain scalable for most load conditions. This allows us to decompose the original design problem into two independent ones. The rst is efciency optimization, which is done by simulating the analytical model described in Sections 3 and 4. The second is matching problem, which is discussed after Section 5. 2.2. Main contributions The general idea behind this work is as follows. We begin by developing a PCE model, which captures most of CMOS transistors non-linear effects. We then seek to determine a set of circuit design parameters, which uniquely x the PCE. Unlike previous work which assumes the importance of load current, our work shows that the more important parameters are, in fact, the output voltage (Vout), the ratio of input to output voltages (d) and the transistor width ratio between the PFET and NFET pair (g2). Instead of scaling transistors directly based on the load current requirement, we rst nd the set of Vout, d and g2 for the maximum PCE. Subsequently, the transistors are scaled in order to meet the load current requirement while keeping the set of parameters constant. This allows us to (a) scale transistors freely for any output current level without affecting the PCE, and (b) cascade multiple rectier stages without incurring PCE degradation. Finally, a piece-wise linear model is presented for approximations with the non-linear rectier, which allow for the power matching and PU optimization. It is found that the proposed model can account for all effects with the rectier at the point of peak PCE, and yield results quite different from those expected

where PL denotes the average output power at the load and PR is the average real input power to the rectier. Another important quantity is system efciency [3]. To avoid confusion between these two terms, we shall refer to the latter as power utilization (PU),
Antenna Ra=73 Matching Circuit LLS Model For Differential-Drive CMOS Rectifier Rectifier IL Load PL=VL IL

Tag Circuits

Shunt Regulator

AC

CLP

Lcompensate

VL

Fig. 1. Block diagram for the overall rectier circuit.

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with the traditional matching technique. The main contributions of this work are summarized as follows: Development of an analytical model for the rectier. Discussion of conditions for maximum PCE. Description of a PCE-invariant design scaling method. Investigation of a piece-wise linear approximation model for the rectier and a new matching theory for piece-wise linear loads. (v) Establishment of relationship among the rectiers bandwidth, operating range and technology process. (vi) Design of three-stage rectiers with ST 90 nm CMOS technology for optimal performance at 10 and 22 m. (vii) Demonstration of simulation results showing that the obtained PU is potentially 3 times as much, and that the maximum operating range is 55% longer, when compared to the existing results under the same level of available power. 3. An analytical model for multi-stage rectiers This section rst describes a general multi-stage differentialdrive CMOS rectier. It is shown that such a rectier can be fully characterized by its half-wave bridge version, the detailed analysis of which is then given in order to develop our design theory. 3.1. Multi-stage differential-drive CMOS rectiers Typical RFID tags require a supply voltage beyond a singlestage rectier can provide. A three-stage differential-drive CMOS rectier is shown in Fig. 2, where Cint represents the uniform charge reservoirs, and Co is the output capacitor which could have a bigger value than Cint, depending on the transient load current. While all bulk connections of the NMOS transistors in Fig. 2 are wired together, the separate N-wells of PMOS transistors allow a degree of freedom for their biasing (i.e., Vb1, Vb2 and Vb3), which can be utilized for some design advantages (see Section 4.2 for details). The dotted lines in Fig. 2 indicate stage boundaries, where basic cells of rectier are cascaded. For convenience of discussion, a basic cell of rectier is also illustrated in Fig. 3(a), where voltage sources Vx and Vx 1 are used to replace Cint of Fig. 2 (the sufx x denotes the stage number). This replacement is reasonable since (a) the ripple effect can be made arbitrarily small by using a large capacitor, and (b) a shunt voltage regulator in the tag also enables the voltage to stay within a tight range.
1st stage

(i) (ii) (iii) (iv)

With DC analysis, it can be seen from Fig. 3 that the output current (Iox) equals the input current (Iix). If the output voltage (Vx) is divided into two voltages, Vex and Vx 1, then an effective ground can be created, as shown in its equivalent circuit of Fig. 3(b). Since both gate voltages (Vi1x and Vi2x) are raised by Vx 1, the coupling capacitors (i.e., Cc) are needed in Fig. 2 for DC blocking. If Vex equals V1 for all stages, it follows that Vx xV1, and one only needs to fully characterize one basic cell in order to understand the multi-stage rectier. Also, the basic cell shares the form of a full-wave bridge rectier with its two identical alternately conducting half-wave bridge circuits. In the following discussions, we refer to the above rectier circuits as the differential-drive CMOS full-wave bridge rectier (DDCFB) and halfwave bridge rectier (DDCHB), respectively. 3.2. Differential-drive CMOS half-wave bridge rectier A DDCHB consists of a pair of complementary MOS transistors, as shown in Fig. 4. Both transistors are connected in series with an output capacitor. For convenience of discussion, we introduce some terms as follows: VinRF input voltage; Vthn, Vthpthreshold voltages of NMOS and PMOS transistors; Vgsn, Vgspgate-to-source voltages for NMOS and PMOS transistors; Vdsp, Vdsndrain-to-source voltages for NMOS and PMOS transistors; Voutoutput voltage across the output capacitor; Icurrent through the output capacitor; g2transistor sizing parameter. Particularly, g2 encapsulates the geometric properties of the circuit and is dened as g2

bn bp

where bn (bp) represents the technology process and geometry constant of the NMOS (PMOS) transistors and is given by

bn mn Cox

Wn , Ln

bp mp Cox

Wp Lp

Throughout this paper, the channel lengths for both NMOS and PMOS transistors are assumed to be the same (i.e., Ln Lp). With
2nd stage 3rd stage

Cc V1 Q2 Q3 Vb1
AC

Cc V2 Q6 Q7 Vb2 Q10

Cc V3 Q11 Vb3

Q4

Q1 Cint Cc

Q8

Q5 Cint Cc

Q12

Q9 Co Cc

Fig. 2. Schematic of a three-stage differential-drive CMOS rectier.

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Vi1x Vi1x Qh1 Qh1 Vbx

Vbx

Point A Iix

Vx-1 Qh2

Iox Vx

Qh2 Iix Vi2x

Iox Vex

Vi2x

Effective Ground

Vx-1

Fig. 3. A basic cell of rectier (a) and its equivalent circuit (b).

I Vgsp1 Vi2x Vdsp Qh1

Vgsp2 Vin

Vbx Vex

voltage for a slightly higher forward current. However, this current change due to the body effect is very small, and (6) or (7) still provides a good estimate for the total current. The advantage of this rectier is evident when compared to the Dickson multiplier topology. For instance, a transistor in the Dickson multiplier will turn on only when Vin Vout ZVthp. But the transistor in differential-drive rectier turns on when Vin ZVthp, which means that it can work at a lower input level. 3.2.2. Region two (reversed triode conduction) When Vin becomes smaller than Vout, we have Vgsn Vgsn2 and Vgsp Vgsp2 and the current I starts owing in the reversed direction (i.e., from bottom to top in Fig. 4), and both Vdsn and Vdsp become negative. Under this condition, Vgsn Vout Vdsp, Vgsp Vin Vdsp and 9Vdsp9 (or 9Vdsn9)oVout Vin. As long as Vin Z9Vthp9, the transistors remain in triode mode, and (6) and (7) apply. The bulk terminals are now connected with source terminals with no body effect. Otherwise, the reverse leakage current (particularly the subthreshold and reverse conduction currents) will increase, causing undesirable power loss. 3.2.3. Region three (partial saturation) When Vthn rVin o9Vthp9, the PMOS transistor works in saturation mode while the NMOS transistor stays in triode mode. The current for the PMOS becomes Ips 2 1 b V Vthp Vdsp 2 p in 8

AC

Vgsn2 Vx-1 Vi1x Qh2 Vdsn Vgsn1

Fig. 4. A differential half-bridge rectier circuit.

the level-one SPICE model, one can get some insight to the operation of Fig. 4. More specically, the DC operation curve for one signal cycle involves six different regions of operation as described below. 3.2.1. Region one (forward conduction region) It can be seen from Fig. 4 that if Vin Z Vout, then Vgsn Vgsn1 and Vgsp Vgsp1. Under this condition, the current I ows from top to bottom with Vin Vgsp Vgsn and Vin Vout Vdsn Vdsp.. As a result, Vdsp (or Vdsn) oVin Vout. When Vout Z9Vthp9, the transistors will always operate in triode mode, and the current is given by [15] ! 1 2 6 Itcr bp Vin Vthp Vdsp Vdsp 2 or 1 2 Itcr bn Vin Vthn Vdsn Vdsn 2 ! 7

3.2.4. Region four (full saturation) If we dene

n Vthn Vthp Vout n rVin oVthn. The resulting current is given by [15]
Ifs 1 g2 b V n2 2 1 g2 p in

Then the transistors enter the saturation region when

10

Solving (6) and (7) with the above conditions leads to an expression for Itcr in terms of Vin, Vout, Vthn and Vthp only. It should be noticed that the bulk is intentionally connected to drain terminals such that the body effect will decrease the threshold

3.2.5. Region ve (subthreshold conduction) When Vin is smaller than n, both Vgsn and Vgsp are still forward biased, and the transistors are in the subthreshold mode of operation. The current can be expressed as [15] Isc tp bp eVgsp Vsbp =nVT 1eVdsp =VT 1lsubp Vdsp 11

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where Vsbp is the source-to-bulk voltage, lsubp is for modeling the effect of drain induced barrier lowering (DIBL) of the PMOS transistor and tp is given by

tp

Isop

mp Cox

12

where Isop is the curve-t offset leakage current for the PMOS transistor. Since Vgsn Vout Vdsp and Vgsp Vin Vdsp, the differential-drive CMOS rectier is clearly better than Dickson multiplier in which the transistors are biased with a constant voltage when Vin rVout. This is because the constant Vgs bias signicantly raises the subthreshold current which is exponentially related to Vgs, and is hence highly disadvantageous for the PCE. 3.2.6. Region six (full reverse conduction) If the size of the NMOS transistor is much larger than that of the PMOS transistor, Vdsp becomes much greater than Vdsn and is close to the value of Vout as Vin approaches zero. As a result, Vgsn E 0 and Vgsp EVout. The NMOS transistor will operate in reverse leakage mode when Vin o0. Conversely, when the PMOS transistor is much larger than the NMOS transistor, the former will rst enter the reverse leakage mode when Vin o0. On the other hand, when the two transistors are sized such that Vdsp equals Vdsn, both of them will enter the reverse leakage mode in the range of Vout rVin r0. Under the reverse leakage mode, the current I is given by Irl tp bp eVsbp =nVT 1eVdsp =VT 1lsubp Vdsp 13

which depends on Vsb (but not Vgs). The above analytical model will be used in Section 4 for PCE optimization. Fig. 5 depicts the current waveform for a half-cycle of conduction through all of the six operating regions described above. In Section 3.3, we focus on investigation of matching issue. The idea is to use the rectiers AC model and, through step-bystep simplication, obtain a piece-wise linear matching model which will be derived in Section 5. 3.3. AC model for differential-drive CMOS rectier The model discussed so far only applies to DC analysis. However, parasitic capacitances of actual transistors will lead to extra AC currents. For modeling of the AC currents, small signal model will not yield useful result as the input AC signal spans a

wide range of voltages and the rectier also behaves non-linearly, especially when it operates with high PCE [3]. A large signal model for parasitic capacitances has been given by well known sources (such as [13]). Fig. 6(a) depicts a PMOS with parasitic capacitors across each pair of its terminals. These capacitors represent the gate-to-source, gate-to-drain, gate-to-bulk, drainto-bulk and source-to-bulk capacitances, denoted by Cgsp, Cgdp, Cgbp, Cdbp and Csbp, respectively. The leakage current through the gate of a 90 nm PMOS is still in the pico-ampere range even when the transistor width is tens of micro-meters. Normally, the transistors substrate is reversely biased with respect to the channel, the source and the drain. Therefore, the leakage currents through the substrate consist of junction leakages. However, these currents are orders of magnitude smaller than the dominant channel conduction current due to the triode mode and the subthreshold mode conduction. For this reason, these leakage currents can be ignored, leading to the replacement of the PMOS by an equivalent P-type non-linear resistor, as depicted in Fig. 6(b), whose operations follow the equations given in Section 3.2. In this analysis process, we are not interested in the nonlinear resistors exact circuit model. Rather, we seek to nd its behavioral model at the point of circuits optimal efciency. This is done by separating the non-linear circuit element from the linear elements in order to approximate the rectier circuit by a simple linear RC network with an in-parallel non-linear resistor, which is to be described at the end of this section. Due to the resistors non-linearity, instead of analyzing it directly we discuss the conditions of optimal PCE based on the simulation of Section 4. It is under these conditions that the piece-wise linear model approximates the non-linear resistor (refer to Section 5). By the same token, the NMOS can also be modeled by Cgsn, Cgdn, Cgbn, Cdbn, Csbn and an N-type non-linear resistor. This model can be used to replace the PMOS and NMOS transistors in Fig. 4 and result in the equivalent circuit of Fig. 7. Furthermore, for AC analysis, the xed voltage sources of Vbx, Vx 1 and Vex are treated as a shortcircuit, and so are the Cdbn and Cdbp capacitors in parallel with the sources. By rearranging components of Fig. 7, we ultimately obtain the AC equivalent circuit of Fig. 4, shown in the top half of Fig. 8. The AC equivalent circuit for the other half-bridge of the rectier is shown at the bottom part of Fig. 8. If the same voltage is applied to each respective half-bridge, the values of the capacitors C0 in Fig. 8 should be exactly the same as the values of capacitors C since the two circuits are symmetrical. In general, all capacitances in Fig. 8 are non-linear and their values depend on the biasing level. For instance, when the transistors are in cut-off region, Cgsn, Cgdn, Cgsp and Cgdp mainly consist of overlap capacitors, which have relatively small values while Cgbn and Cgbp have much bigger values. When the transistor turns on instead, with a strong inversion layer, the values of Cgbn and Cgbp diminish while Cgsn, Cgdn, Cgsp and Cgdp increase [13]. When both top and bottom half-bridges of Fig. 8 are considered

drain Cgd gate Cgs Cdb substrate Cgd Cdb Vdsp

Csb

Cgb

Cgs

Csb

Cgb

source
Fig. 5. Current for a half-cycle of conduction through all six-regions. Fig. 6. PMOS model of [13] (a) and its approximated model (b).

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4.1. 3-dimensional contour for PCE

Csbp Cgsn Cgsp

Cgbn Vbx Cgdn

Cgbp Csbn Cdbp Cgdp Cdbn Vex Vx-1 NR N-type Non-linear Resistor

PR P-type Non-linear Resistor

Fig. 7. Equivalent circuit of DDCHB with parasitic capacitors.

where i is dened as a voltage in the range of [ Vout, 0], which depends on the ratio of transistor sizes (refer to Section 3.2). Since the rectier is typically supplied with a sinusoidal input voltage Vin, we assume Vin V sin y, where y is an arbitrary frequency parameter in radian. From (1), the rectiers PCE can be written as R 2p Vout I dy PCE R 2p 0 15 V 0 I sin y dy where I is given by (14). Since bp is a common term in (14), it will be canceled in calculating (15). This implies that the effect of transistor geometry on the PCE is due to g2 (dened by (4)), and the PCE can be maintained while scaling the transistors for any output power level. Intuitively, a high PCE would occur when the forward voltage drop through the transistors is small. From (15), this happens when VEVout and y E p/2, leading to PCE EVout/V. For any value of y, the PCE is generally dependent on the ratio Vout/V which is denoted as

Csbp Cgsp Cgsn Cgbp

Cgbn

Cgdn

P-type Non-linear Resistor I+ IN-type Non-linear Resistor

PR

I Csbn Cgdp

AC

NR

d
Cgbp Cgsp Cgsn Csbp Cgbn Cgdn P-type Non-linear Resistor Csbn Cgdp N-type Non-linear Resistor NR

Vout V

16

PR

Fig. 8. AC equivalent circuit of DDCFB.

together, the C and C0 values tend to change in complementary of each other due to their AC input being 1801 out of phase for a sinusoidal input. Another feature of the rectiers AC equivalent circuit is that the currents I and I in Fig. 8 are identical due to the symmetrical nature of the circuit, leading to an average current of I that equals zero. This implies the center-tap that connects the non-linear resistors to the capacitors can be disconnected for simplicity of modeling. These phenomena allow us to use a xedvalue capacitor (denoted by a parasitic capacitor Cp) to model the above capacitive network. Ideally, Cp is purely reactive and consumes no power. Thus, although the circuit of Fig. 4 is fully characterized with AC and DC analysis, the DC analysis can be applied rst to get the most important insight about PCE. The AC effect is then taken into consideration for non-ideal properties of Cp. For instance, the high resistivity of poly-silicon gates and the substrate loss will manifest themselves as losses. As an approximation, these losses can be represented by a loss resistor Rloss(AC), which connects in parallel with Cp. More discussions about the AC loss will be given later in Sections 4.3 and 5.

where d ranges from 0 to 1. From the above analysis, it follows that the PCE depends upon three key parameters, namely g2, d and Vout (the body effect will be discussed in the next subsection). Other parameters are process-related and can be treated as a constant during the design. To account for channel modulation effects, we rely on BSIM3 simulation results to ne-tune (6)(13). With all these effects included, it would be too complicated to nd an analytical solution for (15). In general, the PCE vs. above key parameters can be examined in a four-dimensional coordinate system. However, with (16) in mind, we can look at the projection of the above four-dimension problem into 3-dimensional contours with various values of d. Also, to handle the complexity with large volume of data, we resort to MATLAB for computation. Fig. 9 illustrates an example of PCE contour

4. PCE contour analysis Based on the rectier model derived in Section 3, this section discusses the conditions for maximum PCE with the rectier.

Fig. 9. A PCE contour example for Vsb 0 and d 0.82.

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(for Vsb 0 and d 0.82) from a single-stage rectier with CMOS 90 nm technology. It can be seen from Fig. 9 that the PCE peaks at Vout 0.28V and g2 0.5, and it drops when Vout deviates 0.28 V. On one hand, Vout must be greater than 9Vthp9 in order for the transistors to operate in triode mode for low loss (refer to Section 3.2). On the other, if Vout is too high such that Vin rVout, the leakage becomes signicant, leading to a reduced PCE. The fact that the PCE peaks at g2 0.5 indicates the existence of an optimal transistor size ratio. This is because the transistor size ratio affects the Vds (in the subthreshold region) and hence the transistors percentage time spent in the subthreshold mode of conduction, which is a signicant contributor to the leakage. While Fig. 9 shows only one contour for d 0.82, more contours can be obtained with different values of d. Analytically, the global optimal PCE can be determined by solving @PCE @PCE @PCE 0 @Vout @d @g 2 17

Our simulation shows that the optimal PCE of 74.6% occurs at the contour with d 0.82 and Vsb 0 (for both transistors). 4.2. Maximum PCE vs. body effect Traditional analysis has identied the threshold voltage Vth as a culprit for power loss in rectier circuits. Thus, it is natural to assume that the body effect will degrade the PCE, especially for multi-stage rectier designs using regular CMOS transistors with non-zero Vth [2]. This is because the bulk of NMOS transistors in intermediate stages will unavoidably experience an increasingly negative bias voltage. However, the above assumption is not necessarily valid for a CMOS differential bridge rectier. Figs. 10 and 11 show a top view of PCE contour diagrams for two different source-to-bulk bias voltages, where the darker color represents lower PCE while the brighter area corresponds to higher PCE. It can be seen from Figs. 10 and 11 that with a higher sourceto-bulk bias voltage of 0.66 V for the NMOS transistor, the point of maximum PCE simply shifts to a higher value of 78.8% when Vout 0.3 V and g2 1.2. While this may seem to be counterintuitive, it is recognized that unlike the Dickson multiplier topology, the DDCHB or DDCFB conducts with the transistors mainly operating in their triode regions (refer to Section 3.2),
Fig. 11. PCE contour for Vsbp 0, Vsbn 0.66 V and d 0.82 (maximum PCE of 78.8% occurs at Vout 0.3 V and g2 1.2).

where the Vds is signicantly lower than Vth. In this sense, the rectier performance is less affected by Vth. Since maximum PCE would require Vout bias to be just slightly above Vth, this leads to a low forward conduction current that accentuates the effect of subthreshold current. Fortunately, a higher Vsb now suppresses both the subthreshold and reverse leakage currents (see (11) and (13)), resulting in a possible improvement in PCE. Nevertheless, only a little improvement could be expected in this case, because the subthreshold current is much less signicant compared to the currents in other operation regions. The fact that increasing Vth will not necessarily degrade the PCE can be utilized to our design advantage. For instance, we can match the required load voltage to the optimal rectier voltage by controlling the source-to-bulk bias. Section 3.1 shows a multi-stage rectier circuit where the source-to-bulk of PMOS transistor can be independently biased. For instance, assuming the required load voltage is 0.33 V while the optimal rectier voltage Vout is 0.29 V, the latter can be shifted to the desired 0.33 V by raising the PMOS transistors source-to-bulk voltage in that particular stage. 4.3. Effects of nite gate and substrate resistance To account for effects of the nite gate and substrate resistance which are ignored in the above analysis, we simulated a singlestage rectier circuit with 915 MHz input sources using Cadence Spectre tools. Results show the maximum PCE turns out to be 72.4% and 74.3% for Vsbn 0 and 0.66 V, respectively, compared to 74.6% and 78.8% (without consideration of the above effects) as shown in Figs. 10 and 11. This slight difference in PCE due to the loss resistance allows us to combine the DC results obtained so far with a simple linear loss model for covering both AC and DC effects with reasonable accuracy, as will be discussed in the section that follows.

5. Piece-wise linear model This section describes a piece-wise linear approximation model for the rectier. This model is useful for development of our matching theory as well as consideration of design tradeoffs, which are to be discussed in the next few sections.

Fig. 10. PCE contour for Vsbp 0, Vsbn 0 and d 0.82 (maximum PCE of 74.6% occurs at Vout 0.28 V and g2 0.5).

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As it can be seen from Figs. 9 and 11, when the PCE reaches its peak value with Vout Z9Vthp9, the transistors operate in triode mode and behave in a nearly linear fashion. Therefore, they can be modeled as a linear xed-value resistor. Fig. 12 shows such a model for the DDCFB, where the transistors are modeled by a resistor connected to a switch that turns on when Vin Z9Vthp9. The average current (Io) for a sinusoidal input Vin V sin y is calculated as
Io 1 2p Z psin1 wd V sin yV
sin
1

out

wd

dy

! q V 1 2 1wd2 dp 2d sin wd 2pR

18 where R is the xed-value resistor and w 9Vthp9/Vout. The transistors can be sized in such a way that the model gives the same Io as the real circuit would. Figs. 13 and 14 compare the xed-resistor model with actual simulation results (in terms of current and power loss, respectively) when the circuit is subject to a full cycle of sinusoidal input signal (Vin). It can be seen from the gures that there is about 10% difference in peak current value. The average power is calculated by integrating the main envelope of Fig. 14 for the forward region, and the side envelopes for the reverse region. The power discrepancy between models was found to be 3% and 69%, respectively. To account for the error in power loss in the reverse region, a shunt resistor (known as loss element) is introduced (as shown in Fig. 12), which can be sized to offset the above discrepancy. If the resistance of this loss element is denoted by Rloss, the PCE can be

Fig. 14. Power waveform for xed-resistor model (dotted line) vs. actual simulation (solid line).

On when VinVthp R Loss Element Io Iloss

Vin AC Iin

Vout

Fig. 12. A xed-resistor model for the half-bridge rectier. Fig. 15. Simulated PCE vs. modeled PCE.

obtained by substituting (18) into (15) as

19

Fig. 13. Current waveform for xed-resistor model (dotted line) vs. actual simulation (solid line).

Since the xed-resistor model represents a circuit that switches between two perfectly linear regions, it is hence named piece-wise linear model. Fig. 15 shows a comparison of PCE (for 915 MHz) from the piece-wise linear model and the actual Cadence Spectre simulation for a single-stage rectier design example. It should be noticed that the factor pR/Rloss in (19) causes the downward bending of the modeled curve in Fig. 15. To increase the peak value of PCE, we need to either decrease R or increase Rloss. As mentioned in Section 3, increasing Vout forces the transistors to work in the triode region, leading to an increase in Io or, equivalently, a decrease in R. However, if Vout is increased too much, the reverse conduction current will go up as well, which results in a decrease in Rloss. Therefore, a more practical way to improve the peak value of PCE is to keep Vout slightly above 9Vthp9

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and, at the same time, reduce the reverse leakage current by increasing the source-to-bulk bias (equivalent to increasing Rloss). The fact that the modeled curve traces the simulated curve closely until the maximum PCE of 73.3% means that this simple model can be used in the real circuit for both low and high PCE analysis. In Fig. 15, the value of d at the point of maximum PCE is marked as dmax. As the value of d goes beyond dmax, the modeled PCE deviates from the simulated PCE. This is because at high value of d, the reverse current (see Section 3.2) becomes increasingly dominant with the highly non-linear nature which cannot be modeled accurately by a linear resistor. Fortunately, our goal is to achieve the maximum PCE for which the effect of non-linearity is not yet dominant. Thus, the proposed piece-wise linear model is sufcient for our analysis. Our assumption in Section 4.1 that PCE is strongly related to d is also conrmed by Fig. 15 which shows that d indeed follows the PCE closely.

Table 1 Available power (PA) at various distances for PEIRP 4 W. Distance r (m) 1.76 3 5 10 20 30 Available power PA (mW) 1450 496 178 44 11 5

Since the term U2/8Rr in (22) is the available power (PA) from o the antenna, Rr can be written from (3) as   2 prU0 2 23 Rr PEIRP G l where l and PEIRP are typically a constant and, for our particular case with 915 MHz band, equal to 327.87 mm and 4 W, respectively, G 1.64 for a simple dipole antenna, and the value of r is set by the operating range, leaving U0 as an only unknown variable. Table 1 shows a list of PA for different values of r. 6.2. Power utilization At the beginning of a design cycle, design specications typically include the range requirement (or estimated PA from Table 1) and load requirement in terms of voltage and current. What is unknown is how much of the available power can actually be delivered to the load, which is dened as the power utilization (PU) as shown in (2). Dividing (22) by PA results in the following expression of PU for a half-bridge rectier: !   q Rloss 8k kp 24 1wk2 ksin1 wk PUhalf Rloss Rr 1 sp 2 Since a full bridge consists of two identical half-bridge circuits in parallel, the PU for a full bridge (PUfull) is simply PUfull 2 PUhalf 25

6. Matching of rectier to antenna For the DDCHB or DDCFB rectier, PCE peaks only at a specic combination of g2, d and Vout values. If the input of the rectier is modeled by a traditional linear impedance model for impedance matching without considering the above combination, it could lead to an inferior PCE. Conversely, if the combination of g2, d and Vout is met without satisfying the impedance requirement, the power transfer would not be maximized. Therefore, a natural question to ask is whether both power transfer to the load (or PU) and the PCE can be optimized at the same time. This section discusses the matching problem based on the above piece-wise linear model. 6.1. Piece-wise linear model for matching Consider the matching problem in an antenna-coupled rectier circuit with the proposed piece-wise linear model, as shown in Fig. 16 where Rr is the equivalent radiative resistance from the antenna and U0 is the amplitude of the sinusoidal source with y ot. If we assume   Rr Vout k 1 20 Rloss U0

To nd the maximum value of PU, let @PUhalf =@k 0. This leads to q wk2 1wk2 2k sin1 wkkp 1w q 0 26 1wk2 The solution of (26) for k is denoted by kmax. For the special case of w 1, kmax is found to be 0.3942. The maximum PU also depends on the value of s. For s 0 in particular, the PU maxima for the full-bridge and half-bridge rectiers are 0.9226 and 0.4613, respectively. This implies that even with a lossless rectier, the power that can be extracted would be no more than 92% of the available power since generally 0 o s. 6.3. Transistor sizing for optimal power transfer According to (21), the accurate value of s is unknown since the values of R, Rr and Rloss are not available. However, an estimate of s can still be obtained by the following method. As is shown in Section 4.1, d Vout/V, where V is the voltage amplitude across R and Vout in Fig. 16. For a narrow band antenna and matching network, V is approximately sinusoidal. In Fig. 16, the peak current through R can be expressed in terms of V or in terms of dmax and Vout, where dmax is the value of d that maximizes the PCE (refer to Fig. 15). By using (20) and (21), the best resistance ratio s, dened as smatch, can be estimated as

RRr Rloss Rr Rloss

21

the power at the load (with the output voltage Vout) can be expressed as Z psin1 wk 1 U0 sin yVout PL dy Vout 2p sin1 wk Rr ==Rloss R !   q U2 Rloss 8k kp 22 1wk2 ksin1 wk 0 8Rr Rloss Rr 1 sp 2

Rr

Rr //Rloss

AC

U0sin ( t)

Rloss

AC

R Rloss Rr + Rloss U0sin ( t) Vout

Vout

Fig. 16. Model of an antenna-coupled rectier circuit (a) and its equivalent circuit (b).

smatch %

kmax 1dmax dmax kmax

27

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where kmax is the value of k that maximize the PU. Since Rloss is due to transistors leakage and AC parasitic loss, and is typically much larger than Rr , the estimated value of PA and hence maximum operating range r can be found from (2), (24) and (25) for a given PL by substituting (27) into (25). Alternatively, one can nd the estimated value of PL if PA is given as an initial design parameter. Either way, the value of R can be found from (16) and (18) with given values of dmax, Vout, Io and w. It has been shown in Section 4.1 that the global maximum value of PCE is independent of transistor size scaling as long as d, Vout and g2 are constants. Our goal is then to maintain dmax at an available power level of PA. The value of Rloss can be found by substituting R and the PCE into (19). Thus, the transistors in a basic cell of rectier (see Fig. 3) can be scaled linearly for the output current Io while keeping g2 constant. This can be done through simulation with Cadence Spectre tools. Assuming that all transistors have the same channel length, it becomes clear that the maximum PU will be obtained only with transistors of particular sizes for a designed level of PA. In other words, for any given target operating range, an optimal transistor size exists for maximum power transfer. 6.4. Coupling capacitors and parasitic gate capacitances As is shown in Section 3.1, for a multi-stage DDCFB rectier, the DC bias generated by the stage cascading requires the use of coupling capacitors (Cc) in all stages (except the rst stage) for DC blocking. These capacitors represent a capacitive divider with parasitic gate capacitances (Cp) of transistors, as shown in Fig. 17 where Vin(eff) is introduced as an effective input voltage to the bridge rectier. The amplitude of the voltage across R and Vout in Fig. 17, denoted by Vr, can be determined (without proof) as follows, regardless of R and Vout: Vr % Vineff Cc Cc 2Cp 28

Matching Network LLS 73 Equivalent Rectifier

QL =
AC

Rr 1 73
CLP

Reff Lcompensate Cp(eff ) Rloss(eff ) Vout(eff )

Fig. 18. An equivalent rectier with L-match network to a dipole antenna.

process. For the CMOS 90 nm process under our consideration, this constant is 0.5932 fF/mm. The value of Rloss(eff) in Fig. 18 can be obtained by scaling Rloss. However, since Rloss(eff) is generally very large, its impact on matching is negligible. The matching network in Fig. 18 will be briey discussed later in Section 6.6. 6.5. Determining the equivalent radiative resistance In order to determine the equivalent radiative resistance (Rr), one can nd U0 by substituting (30) and kmax into (20) (again with the assumption of Rr/Rloss E0 since Rloss bRr). The value of U0 is then substituted into (23) to obtain Rr. Further substituting the value of Rr into (21) gives the value of s, which may not match smatch due to the narrow-band approximation in deriving (27). In general, the above procedure needs to be done iteratively until the value of s converges. However, as will be seen in Sections 8 and 9, a single iteration is usually satisfactory with reasonably good results. 6.6. Matching with an L-match network Typically, the value of Rr as determined above is much larger than the low impedance of a simple antenna (73 O for a simple dipole antenna). This allows us to use an L-match network, as shown in Fig. 18 where QL is the quality factor for the L-match. The inductor Lcompensate in the network is required because our PU analysis assumes no reactive current. The reactive impedance due to Cp(eff) can be canceled by an appropriately sized inductor. Real inductors and capacitors contain parasitic loss elements, the effect of which can be easily estimated by adjusting Rloss(eff) in Fig. 18.

This is because the charge loss due to Io through the capacitor network in one half-cycle will be compensated by the charge gain in the next. If Vin(eff) is viewed as the output from the matching circuit, then an equivalent rectier circuit can be obtained with some effective parameters, as shown in Fig. 18 where Cp(eff), Vout(eff) and Reff are given by   Cc Cpeff 29 Cp Cc 2Cp   2Cp Vouteff 1 Vout Cc Reff 1  2Cp R Cc  30

7. Design tradeoffs This section looks at the relationship among the rectiers bandwidth, operating range and technology process. 31 7.1. Bandwidth for an optimal rectier Bandwidth is an important attribute for the rectier in mobile tags that are situated in a noisy automotive environment, and should be considered based on both the matching network and antenna system. Since antenna design varies drastically with different performance characteristics and is beyond the scope of our discussion, this work shall only address the matching network and its effects on bandwidth. It can be seen in Fig. 18 that the bandwidth (B) depends on both QL of the L-match and the quality factor (QC) of the reactance compensation network. However, since most of the power is delivered to the load when the rectier turns on, the QC due to Reff is a very small number (typically less than one) because of the small value of Reff. As a result, the bandwidth characteristic is mainly determined by the relatively large QL. By using (20), (23), (30) as

and the value of Cp is estimated by multiplying a constant to the total width of all transistors, depending on the technology

Cc AC Vin (eff) R Cp

Cc Cc + 2Cp

Cc + Cp Vin (eff) AC R Vout

Vout

Fig. 17. A capacitive divider with parasitic gate capacitances.

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well as the value of QL given in Fig. 18, the expression for the bandwidth (B) can be approximately written as r 1 kmax c Ra PEIRP G B% 32 r p1 2Cp =Cc Vout 2 where Ra and c represent the radiative resistance of the physical antenna and the speed of light, respectively. 7.2. Tradeoffs for the rectier design It is interesting to see from (32) that the bandwidth B of the rectier is independent of the operating frequency. A general observation is that B is inversely proportional to the designed operating range (r) and the rectiers output voltage (Vout). For instance, the rectier designed in 0.18 or 0.35 mm CMOS process for the same operating range will have a narrower bandwidth than that of the 90 nm process which has a lower threshold voltage.

Likewise, the nal stages output at 0.99 V can be used to set the bulk voltage of the second stage. If this is done, the 9Vthp9 for rst two stages becomes 0.3117 V. While the Vsb for the nal stage remains at zero, the Vsb for the N-type of the same stage will be biased to 0.66 V, forcing the Vthn to be higher than 9Vthp9 at a value of 0.2806 V. Therefore, the bridge circuit will turn on at Vthn (instead of 9Vthp9) which, however, is still lower than 0.33 V when compared to other stages, and the optimal PCE may not be reached. Fortunately, as can be seen from the PCE contour in Section 4, the region around the optimal PCE is rather at, which means that the resulting PCE would be very close to its optimum. After the optimum number of stages is determined, the transistors in each stage should be sized using the procedure from Section 6.3 such that the average output current at Vout remains the same for all stages. This would require various transistor sizes for different stages, as opposed to the same transistor sizes used by other existing design methods. 8.2. Sizing for coupling capacitors

8. Multi-stage rectier design This section details two multi-stage rectier designs based on differential-drive CMOS full-wave bridge topology with CMOS 90 nm technology, and addresses other issues that arise. 8.1. Optimum number of stages It has been shown that an optimal PCE only occurs at a particular value of Vout that is slightly higher than 9Vthp9. For CMOS 90 nm process, 9Vthp9 is around 300 mV. Since circuits on an RFID tag typically require a power supply of 1 V to operate, there is a need for multiple stages. Also, Section 6 shows that the maximum power transfer will occur only when the ratio of U0 (i.e., effective antenna voltage) and Vout(eff) is approximately equal to kmax. A simple strategy to ensure this is to have all stages operating at roughly the same Vout. Thus, the optimal number of stages (Nopt) can be expressed as Nopt desired total output voltage 9Vthp 9 D 33

Different transistor sizes result in different size of Cp at each stage (refer to Section 6.4). Strictly speaking, the Cc also needs to be sized accordingly to ensure that Vout(eff) also stays the same throughout the rectier for optimal PCE (refer to (30)). In practice, however, keeping the same Cc would be quite acceptable, again due to the at region around the optimal point on the PCE contour. From (32), the size of the Cc also affects the bandwidth of the rectier. It should be noticed that as Cc becomes much larger than Cp, any further increase in Cc provides little or no improvement in the bandwidth. 8.3. Equivalent resistances with multi-stage rectier For the multiple-stage rectier where individual resistances at each stage are almost the same and are connected in parallel, its overall effective resistances would be lower than the single-stage counterpart. More specically, the Reff or Rloss(eff) as described in Section 6.4 for the single-stage rectier should be divided by Nopt given in (33) for the case of multiple-stage design. 8.4. Other parasitic parameters Signicant amount of parasitic loss comes from the nite gate resistance and substrate resistance of transistors. These resistances can be modeled by nding the quality factor of the gate capacitance to be lumped with the equivalent loss resistance Rloss(eff). Practically, the negative effect of the gate resistance can be reduced to a negligible level by introducing a sufcient number of gate ngers. Another point of caution is the selection of driving plate for the coupling capacitor Cc. Let us rst consider the top plate driving method where the input signal is connected to the top plate of Cc, as shown in Fig. 19 where Ca represents the bottom plate coupling to the substrate. In this case, Cas are directly across Cp, which reduces Vr according to (28). This is not desirable as an increased QL is required for compensating the voltage loss with the reduced bandwidth. Fig. 20 shows another case where the bottom plate is driven instead. In this case, no negative side-effects are present because the Cas are in parallel with the source. For both cases of Figs. 19 and 20, however, the substrate loss would decrease the PCE of the rectier circuit. Since the value of Ca is proportional to the size of Cc, small Cc or capacitors with low Ca should be used. The MIM-type capacitor supported by ST 90 nm technology is ideal for this purpose as it uses a lot less area than regular capacitors for obtaining the same capacitance.

where D is an additional offset to ensure that Vout of individual stages operate above 9Vthp9 in order to achieve the maximum PCE. The value of D can be obtained from empirical observation of the PCE contour (see Section 4), and it ranges from 0.01 to 0.03 V. Assuming D 0.02 V, Vsb 0 and 9Vthp90.2785 V (for ST 90 nm process), (33) gives the value of 3.35. One can round this value to 3 for a three-stage design by setting the sum of 9Vthp9 and D to be 0.33 V per stage. This can be done by modifying the body bias of the PMOS transistors based on the threshold voltage at different body bias voltages, as shown in Table 2. If each stage is set to Vout of 0.33 V, we can connect the output of the second stage (0.66 V) to the P-type bulk of the rst stage.
Table 2 Vth at different body bias voltages with ST 90 nm process. Vsb (V) 0 0.2 0.3 0.33 0.36 0.6 0.66 0.72 Vthn (V) 0.2237 0.2434 0.2523 0.2549 0.2574 0.2763 0.2806 0.2849 9Vthp9 (V) 0.2785 0.2991 0.3088 0.3117 0.3145 0.3364 0.3417 0.3469

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Top Plate Cc Cp

Table 3 Design performance for RF10 at 10 m. PA Target PL Designed PU Target Io PCE (1st stage) PCE (2nd stage) PCE (3rd stage) 44.59 mW 33.14 mW 74.3% 33.48 mA 73.33% at g2 0.6 74.15% at g2 0.8 74.1% at g2 1.4

AC

Cc

C Top Plate

Substrate Loss

Table 4 Model and matching parameters for RF10. Cp(eff) Reff Rr QL B 163.87 fF 341.57 O 2382.41 O 5.62 162.68 MHz 0.77 0.39

Fig. 19. Input signal driving the top plate of Cc..

dmax
kmax

Cc

Table 5 Transistor parameters for RF10.

AC

Cp

Bottom Plate
Wp (mm) p_ngers Wn (mm) n_ngers

Stage 1 40.2 120 9.9 30

Stage 2 40.87 122 12.92 38

Stage 3 31.35 95 16.75 50

Cc Substrate Loss

Table 6 Other component values for RF10 (refer to Figs. 1 and 16). Component LL (nH) CL (pF) Lcompensate (nH) Cc (pF) Coutput (pF) Value 71.42 0.410 184.63 1.2 1.2

Fig. 20. Input signal driving the bottom plate of Cc..

8.5. Rectier optimized for 10-m range (RF10) Two three-stage rectiers were designed for different range and bandwidth requirements. The matching networks components as well as the antenna are assumed to be external while transistors, coupling capacitors and output capacitors are integrated on individual ICs with ST CMOS 90 nm technology. An output voltage of 0.99 and 0.33 V is assumed for the overall rectier and each stage, respectively. The rst rectier was designed for the optimized power transfer to the load at 10 m. This design is labeled RF10 whose target performance is shown in Table 3. Table 4 provides piece-wise model and other design parameters for the matching network used in RF10. It can be seen from Table 4 that our piece-wise linear matching model produces the effective radiative resistance (Rr) that is almost seven times as much as the effective on-resistance of the switch (Reff). This is quite different from the traditional concept of matching which suggests an equal value for these two resistances. Transistor parameters and other component values for RF10 are shown in Tables 5 and 6, respectively, where p_ngers and n_ngers are the number of ngers used in P- and N-type gate contacts, and Coutput is the output capacitor at individual stages. The channel length of all transistors is assumed to be 0.1 mm. 8.6. Rectier optimized for 22-m range (RF22) The second rectier labeled RF22 was designed for the optimized power transfer to the load at 22 m. Transistor parameters as

Table 7 Transistor parameters for RF22. Stage 1 Wp (mm) p_ngers Wn (mm) n_ngers 8.84 26 2.19 6 Stage 2 9.1 26 2.88 8 Stage 3 7 20 3.75 10

well as component values for the design are given in Tables 7 and 8, respectively.

9. Simulation results for three-stage rectiers We simulated three-stage rectiers for both RF10 and RF22 with Cadence Spectre tools using parameters from Tables 5 to 8. Results for the RF10 design are summarized in Tables 9 and 10. It can be seen from Table 9 that the PCE reaches its maximum value of 74%, and the obtained PU is 72%. The output current at 10 m distance is 32.45 mA, which is potentially 80 times better than the silicon implementation result of [6] under comparable conditions. Both PU and PCE are higher than the simulated results of [3],

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Table 8 Other component values for RF22. Component LL (nH) CL (pF) Lcompensate (nH) Cc (pF) Coutput (pF) Value 147.74 0.203 772.22 1.2 1.2

matches the estimation from (32). Since each of the circuits simulated is optimized for only one distance (i.e., 22 m), the PU drops when the distance is shorter than the designed values. However, as can be seen from Tables 9 and 11, the resulting rectier designs can still provide sufcient output currents.

10. Conclusions We have presented a new approach for analysis, design and optimization of CMOS differential-drive full-wave bridge rectier circuits. It has been shown that maximum power conversion efciency (PCE) of the rectier occurs only when a particular value of output voltage, input-to-output voltage ratio, and transistor sizes are chosen. The method of transistor scaling has been discussed for different load current requirements without affecting PCE. It has also been demonstrated that the increased bulk biasing level would not necessarily degrade PCE. Instead, this body effect has been strategically utilized to improve the PCE of multi-stage rectiers. To address the non-linear nature of matching problem for rectiers operating at high PCE, which has not been investigated in prior work, we have proposed a piece-wise linear model of the rectier that allows us to formulate the matching problem. It has been shown that maximum power transfer does not occur when the rectiers impedance is matched to the source in a traditional sense. It has also been found that when driven by a sinusoidal source, the rectier under investigation can transfer no more than 92% of available power from the antenna to the load, even under ideal conditions. To validate the proposed design theory, two three-stage rectier circuits, one of which is optimized for 10 m and the other optimized for 22 m, have been designed for the operating frequency of 915 MHz with different transistor sizes and P-type bulk connections for different stages. For the case of 10 m, simulation results have revealed an improvement in output current (32.45 mA) that is potentially 80 times that of the silicon test results of [6] under similar conditions. The rectier designed for 22 m distance, its power utilization (PU) exceeds that of the simulated results of [3] by at least three times while providing 55% improvement in power-up threshold. Since the silicon measurements of [3] match the simulated counterparts, it is reasonable to expect similar performance improvement in actual silicon implementation. At the designed operating range, the output current of two rectier circuits differs by 5 times while maintaining the same PCE. This conrms the validity of the proposed scaling method for PCE-invariant design. It has also been shown that our method results in a high PCE that does not degrade with body effect. This is evident in our three-stage rectiers which operate with the PCE of 74%, the highest simulated value ever reported at the designed distance, especially for multi-stage rectiers, regardless of transistors source-to-bulk bias level. The proposed rectier circuits have also been simulated for different distances ranging from a very short distance ( o1 m) to 19 and 34 m without any observable intermediate dead-zone.

Table 9 PCE and PU for RF10. r (m) 5 7 9 10 11 12 13 PA (mW) 178.38 91.01 55.06 44.59 36.86 30.97 26.39 PA (dBm) 7.49 10.41 12.59 13.51 14.34 15.09 15.79 PU 0.57 0.67 0.72 0.72 0.71 0.69 0.65 PCE 0.71 0.73 0.74 0.74 0.74 0.73 0.72 Io (mA) 102.4 61.72 39.89 32.45 26.4 21.45 17.33

Table 10 Bandwidth (B) for RF10 measured at 10 m. Designed B 162.7 MHz Simulated B 159.2 MHz

Table 11 PCE and PU for RF22. r (m) 16 18 20 22 24 26 28 Pa (mW) 17.42 13.76 11.15 9.21 7.74 6.60 5.69 Pa (dBm) 17.59 18.61 19.53 20.36 21.11 21.81 22.45 PU 0.68 0.71 0.72 0.73 0.72 0.70 0.67 PCE 0.73 0.74 0.74 0.74 0.74 0.74 0.73 Io (mA) 12.05 9.87 8.15 6.76 5.61 4.65 3.83

Table 12 Bandwidth (B) for RF22 measured at 22 m. Designed B 78.6 MHz Simulated B 89.8 MHz

which compare well with the silicon measurements of the same study. In terms of power-up threshold which is dened as the minimum PA for an output power of 2 mW [3], our simulation shows that the proposed design can potentially operate as far as 19 m or at the PA level of 19.1 dBm with the output current of 2.3 mA. Results for the RF22 design are shown in Tables 11 and 12, where the PCE is at its maximum value of 74%, and the PU is 73%. The output power in this case is 6.76 mA 0.99 V6.7 mW, which is potentially more than 3 times better than the silicon implementation result of [3] under comparable conditions. In terms of power-up threshold, RF22 can operate at 24.14 dBm or an equivalent distance of 34 m, which is potentially 55% better than that of [3]. It is evident that the simulated bandwidth generally

References
[1] A. Sasaki, K. Kotani, T. Ito, Differential-drive CMOS rectier for UHF RFIDs with 66% PCE at 12 dBm input, in: Proceedings of the 2008 IEEE Asian Solid-State Circuits Conference (ASSCC08), November 2008, pp. 105108. [2] J. Yi, W. Ki, C. Tsui, Analysis and design strategy of UHF micro-power CMOS rectiers for micro-sensor and RFID applications, IEEE Transactions on Circuits and Systems-I 54 (1) (2007) 153166 (January).

S.-Y. Wong, C. Chen / INTEGRATION, the VLSI journal 44 (2011) 242255

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[3] S. Mandal, R. Sarpeshkar, Low-power CMOS rectier design for RFID applications, IEEE Transactions on Circuits and Systems-I 54 (6) (2007) 11771188 (June). [4] A. Shameli, A. Safarian, A. Rofougaran, et al., Power harvester design for passive UHF RFID tag using a voltage boosting technique, IEEE Transactions on Microwave Theory and Techniques, Part I 55 (6) (2007) 10891097 (June). [5] H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. Mukaida, et al., A passive UHF RF identication CMOS Tag IC Using Ferroelectric RAM in 0.35-mm technology, IEEE Journal of Solid-State Circuits 42 (1) (2007) 101110 (January). [6] T. Umeda, H. Yoshida, S. Sekine, Y. Fujita, et al., A 950-MHz rectier circuit for sensor network tags with 10-m distance, IEEE Journal of Solid-State Circuits 41 (1) (2006) 3541 (January). [7] K. Kotani, T. Ito, High efciency CMOS rectier circuit with self-Vth-cancellation and power regulation functions for UHF RFIDs, in: Proceedings of the 2007 IEEE Asian Solid-State Circuits Conference (ASSCC07), November 2007, pp. 119122. [8] C. Ma, C. Zhang, Z. Wang, Power analysis for the MOS AC/DC rectier of passive RFID transponders, in: Proceedings of the 2006 IEEE Asia Pacic Conference on Circuits and Systems (APCCAS06), December 2006, pp. 13501353. [9] U. Karthans, M. Fischer, Fully integrated passive UHF RFID transponder IC with 16.7 mW minimum RF input power, IEEE Journal of Solid-State Circuits 38 (10) (2003) 16021608 (October). [10] R. Glidden, et al., Design of ultra-low-cost UHF RFID tags for supply chain applications, IEEE Communications Magazine 42 (8) (2004) 140151. [11] J.-P. Curty, N. Joehl, C. Dehollain, M.J. Declercq, Remotely powered addressable UHF RFID integrated system, IEEE Journal of Solid-State Circuits 40 (11) (2005) 21932202 (November). [12] K. Kotani, A. Sasaki, T. Ito, High-efciency differential-drive CMOS rectier for UHF RFIDs, IEEE Journal of Solid-State Circuits 44 (11) (2009) 30113018 (November). [13] R.Jacob Baker, Harry W. Li, David E. Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, 1998 (p. 8488). [14] K. Finkenzeller, RFID Handbook, 2nd ed, John Wiley and Sons Ltd., 2003. [15] Edward S. Yang, Microelectronic Devices, McGraw-Hill, 1988 (pp. 244247, 259263). [16] A. Facen, A. Boni, CMOS power retriever for UHF RFID tags, Electronics Letters 43 (25) (2007) 14241425 (December). [17] G.D. Vita, G. Iannaccone, Design criteria for the RF Section of UHF and microwave passive RFID transponders, IEEE Transactions on Microwave Theory and Techniques 53 (9) (2005) 29782990 (September).

[18] Y.K. Teh, F. Mohd-Yasin, F. Choong, M.I. Reaz, A.V. Kordesch, Design and analysis of UHF Micropower CMOS DTMOST rectiers, IEEE Transactions on Circuits and Systems-II 56 (2) (2009) 122126 (February).

Shu-Yi Wong (M93) received the B.A.Sc. degree in electrical engineering from the University of Waterloo, Ontario, Canada, in 1994. Since then, he had worked in different companies as a communication rmware designer, mix-signal analog/digital designer and chief design engineer. In 2008, he left his job at Tyco Safety Products Canada, Ltd. and joined the University of Windsor, Ontario, where he received his M.A.Sc. degree in 2009. He is currently pursuing the Ph.D. degree at the Department of Electrical and Computer Engineering, the University of Toronto, Ontario, Canada. His research interest is in the area of low power design methodologies.

Chunhong Chen (M99-SM04) received the B.S. and M.S. degrees from Tianjin University, China, in 1983 and 1986, respectively, and Ph.D. degree from Fudan University, China, in 1997, all in electrical engineering. From September 1997 to August 1998, he was a Research Associate at the Hong Kong University of Science and Technology. From December 1998 to August 2000, he was a Postdoctoral Fellow at Northwestern University, Evanston, IL. Since 2001, he has been with the Department of Electrical and Computer Engineering at University of Windsor, Ontario, Canada, where he is presently a professor. His research interests include timing analysis and power optimization for integrated circuits and systems, and more recently reliability and timing issues with single-electron devices and circuits.