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1.symmetric and Distributed Shared Memory Architectures
1.symmetric and Distributed Shared Memory Architectures
Unit III
Multiprocessors and Thread-Level Parallelism
By
N.R.Rejin Paul
Lecturer/VIT/CSE
MIMD Class 1:
MIMD Class 2:
Distributed-memory multiprocessor
P1
u=?
$
P3
3
u=?
u :5 u = 7
u :5
I/O devices
u :5
Memory
11
Pn
P1
Bus snoop
Mem
Cache-memory
transaction
P1
u=?
$
P3
3
u=?
u :5 u = 7
u :5
I/O devices
u :5
u=7
Memory
14
Write Update
16
Placing a write miss on the bus when a write hits in the shared state ensures an
exclusive copy (data not transferred)
18
CPU may read/write hit/miss to the block May receive read/write miss from bus
May place write/read miss on bus
19
Cache Coherence
State Diagram
Figure 6.10 and Figure 6.12 (CPU in
black and bus in gray from Figure 6.11)
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Coherence Problems
Simple approach: uncacheable
shared data are marked as uncacheable and only private data are kept in caches
very long latency to access memory for shared data
Directory Protocols
Similar to Snoopy Protocol: Three states
Shared: 1 or more processors have the block cached, and the value in memory is
up-to-date (as well as in all the caches)
Uncached: no processor has a copy of the cache block (not valid in any cache)
Exclusive: Exactly one processor has a copy of the cache block, and it has
written the block, so the memory copy is out of date
The processor is called the owner of the block
25
Figure 6.29
Transition
diagram for
cache block
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Summary
Chapter 6. Multiprocessors and Thread-Level Parallelism
6.1 Introduction
6.2 Characteristics of Application Domains
6.3 Symmetric Shared-Memory Architectures
6.4 Performance of Symmetric Shared-Memory
Multiprocessors
6.5 Distributed Shared-Memory Architectures
6.6 Performance of Distributed Shared-Memory
Multiprocessors
6.7 Synchronization
6.8 Models of Memory Consistency: An Introduction
6.9 Multithreading: Exploiting Thread-Level Parallelism
within a Processor
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