The document discusses scan insertion for testing sequential elements on a chip. It explains that the tool first performs basic checks on the design before scan insertion. It then identifies all sequential elements for input/output controllability and observability. Any fault locations that cannot be controlled or observed from inputs/outputs may not be fully testable or testable at all. It also provides an overview of built-in self-test (BIST), which generates and analyzes test patterns internally to test circuits on a chip.
The document discusses scan insertion for testing sequential elements on a chip. It explains that the tool first performs basic checks on the design before scan insertion. It then identifies all sequential elements for input/output controllability and observability. Any fault locations that cannot be controlled or observed from inputs/outputs may not be fully testable or testable at all. It also provides an overview of built-in self-test (BIST), which generates and analyzes test patterns internally to test circuits on a chip.
The document discusses scan insertion for testing sequential elements on a chip. It explains that the tool first performs basic checks on the design before scan insertion. It then identifies all sequential elements for input/output controllability and observability. Any fault locations that cannot be controlled or observed from inputs/outputs may not be fully testable or testable at all. It also provides an overview of built-in self-test (BIST), which generates and analyzes test patterns internally to test circuits on a chip.
The document discusses scan insertion for testing sequential elements on a chip. It explains that the tool first performs basic checks on the design before scan insertion. It then identifies all sequential elements for input/output controllability and observability. Any fault locations that cannot be controlled or observed from inputs/outputs may not be fully testable or testable at all. It also provides an overview of built-in self-test (BIST), which generates and analyzes test patterns internally to test circuits on a chip.