Hardware Tutorial 05
Hardware Tutorial 05
Thetaskistodesignatwobitcontrolledcounter D1 D Q which has two counting bits (Q2,Q1), has one 1 1 2 Q1 Q' controlinput C1, andalsotwoextraoutputs,one 0 1 0 1 indicating overflow, the other underflow. When Q2 D2 D Q 0 0 3 C1=0thecountercountsupby2s;i.e.0becomes2, Q' 1 Overflow 0 1becomes3.Inthismodethevalues2and3goto Indicator 1 the overflow state. Whenthecontrolinput C1=1, D3 D Q Q3 OV 0 UN Q' thecountercountsdownby2s,i.e. 3 becomes 1, Underflow 1 0 Indicator and2becomes0,and1and0gototheunderflow state. Thecounterremainsinoneofthese"error" Clock statesuntilthecontrolbit C1 ischangedatwhich point it goes to state 0. The finite state machine showsthisoperatingsequence.Onewaytodesignthiscircuitistosetupsixstates.Thesearethefouroutput countstates:0,1,2,3,andthetwo"error"states:OV(overflow)andUN(underflow).Inordertoprovidesix internalstates,weneedaminimumofthreeflipflops.Inthefollowingincompletetransitiontablesixflipflop outputsareassigned,twoareleftasdon'tcares.
C1
1CompletethetransitiontablebyshowingtheQ3,Q2,Q1outputsofthe"next"state.
C1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 State 0 1 2 3 UN X X OV 0 1 2 3 UN X X OV CurrentState Q3 Q2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Q1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 State 2 3 OV OV 0 X X OV UN UN 0 1 UN X X 0 NextState Q3 Q2 Q1
X X
X X
X X
X X
X X
X X
2. FillintheKMapsfortheDtypeflipflopinputsD3,D2,andD1.(iethenextstateQ3,Q2,Q1 values)anddeterminetheminimisedexpressionsforD3,D2,andD1;
C1 Q3 00 01 11 10 Q2,Q1 00 01 11 10 C1 Q3 00 01 11 10 Q2,Q1 00 01 11 10 C1 Q3 00 01 11 10 Q2,Q1 00 01 11 10
D3
D2
D1
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3.Determinethenecessaryoutputcircuitswhichprovidetherequiredoutputsignals:Overflow IndicatorandUnderflowIndicator.
2 1 3
D3
C1 Q2,Q1 Q3 00 01 11 00 01 11 10
D2
0
10
OV
UN
D1
6 5
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