3.2 At89C51 Microcontroller: 3.2.1 Features:: Fig 3.2:block Diagram of AT89C51 Micro Controller
3.2 At89C51 Microcontroller: 3.2.1 Features:: Fig 3.2:block Diagram of AT89C51 Micro Controller
2 AT89C51 MICROCONTROLLER:
3.2.1 Features:
2 4K Bytes of Re-programmable Flash Memory.
3 RAM is 128 bytes.
4 2.7V to 6V Operating Range.
5 Fully Static Operation: 0 Hz to 24 MHz.
6 Two-level Program Memory Lock.
7 128 x 8-bit Internal RAM.
8 32 Programmable I/O Lines.
9 Two 16-bit Timer/Counters.
10 Six Interrupt Sources.
11 Programmable Serial UART Channel.
12 Low-power Idle and Power-down Modes
Description:
The AT89C51 is a low-power, high performance CMOS 8-bit micro controller with 4K bytes of
In-system programmable flash memory. The device is manufactured using Atmel’s high-density
nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction
set and pinout. The on-chip flash allows the program memory to be reprogrammed in-system or by
a conventional non-volatile memory pro-grammar. By combining a versatile 8-bit CPU with
In-system programmable flash on a monolithic chip, the atmel AT89C51 is a powerful micro
controller, which provides a highly flexible and cost-effective solution to many embedded control
applications.
RST:
reset input.a highon this pin for two machine cycles while the oscillator is running resets the
device.this pin drives high for 98 oscillator periods after the watchdog times out.the DIS-RTO bit
in SFR AUXR(address 8EH) can be used to disable this feature.in this default state of bit
DISRTO,the RESET HIGH out feature is enabled.
ALE/PROG:
address latch enable(ALE) is an output pulse for latching the low byte of the address during
accesses to external memory.this pin is also the program pulse input(PROG) during flash
programming.
PSEN:
program store enable(PSEN) is the read strobe to external program memory.when the AT89C51 is
executing code from external program memory,PSEN is activated twice each machine
cycle,except that two PSEN activations are skipped during each acess to external data memory.
EA/VPP:
external access enable.EA must be strapped to GND in order to enable the device to fetch code
from external program memorylocations starting at 0000H up to FFFFH.Note,however,that if lock
bit 1 is programmed,EA will be internally latched on reset.EA should be strapped to vcc for
internal program executions.this pin also recieves the 12-volt programming enable voltage(PP)
during flash programming.
XTAL1:
input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2:
output from the inverting oscillator amplifier
Oscillator characteristics:
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can e
configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be
used. To drive the device from an external clock source, XTAL2should be left unconnected while
XTAL1 is driven.
B Register:
R Registers (R0-R7):
This is a common name for the total 8 general purpose registers (R0, R1, R2 ...R7). Even they are
not true SFRs, they deserve to be discussed here because of their purpose. The bank is active when
the R registers it includes are in use. Similar to the accumulator, they are used for temporary
storing variables and intermediate results. Which of the banks will be active depends on two bits
included in the PSW Register. These registers are stored in four banks in the scope of RAM.