Logic Gates
Logic Gates
Logic Gates
Learning Objectives:
At the end of this topic you will be able to;
Use combinations of NAND gates to perform other logic functions;
Implement a logic system using only NAND gates;
Recognise redundant gates in a logic system constructed only from
NAND gates.
Module ET1
Introduction to Analogue and Digital Systems.
NAND Gate Logic.
Now that you are able to simplify logic expressions for logic systems, there is
one final simplification that can be made. The inverted gates, NAND and NOR
are special because the function of all other gates can be made from various
combinations of NAND or NOR gates. In this syllabus only NAND gate
alternatives of the other logic functions will be discussed. You may find
some reference to NOR gate logic in some text books but these will not
be asked for in the examination.
You may ask yourself why we would want to go to the trouble of changing an
already simplified system of logic gates into NAND gates, so consider the
two logic circuits below, which perform the same logic function.
System 1 : Mixture of gates.
B
C
Q
B
When system 2 is compared to system 1, you may think that we have made
the circuit more complicated as we have more logic gates in system 2,
Q
however, in system 1 three different types of gates are required NOT, OR
2
is the same as
Complete the truth table below for the NAND equivalent circuit.
Input
A
0
1
Output
Q
Module ET1
Introduction to Analogue and Digital Systems.
2.
A
B
Q A
Complete the truth table below for the NAND equivalent circuit.
Inputs
B
0
0
1
1
3.
A
0
1
0
1
Output
Q
The OR gate.
The OR gate is a little more complicated, and requires three NAND
gates as shown below.
A
A
B
X
A
Q
is the same as
B
Y
A
Complete the truth table below for the NAND equivalent circuit.
4
Inputs
B
0
0
1
1
4.
A
0
1
0
1
Output
Q
A
A
B
is the same as
B
Complete the truth table below for the NAND equivalent circuit.
Inputs
B
0
0
1
1
A
0
1
0
1
Output
Q
Module ET1
Introduction to Analogue and Digital Systems.
5.
A
A
O
Z
Q is the same as
P
B
N
Y
Complete the truth table below for the NAND equivalent circuit.
Inputs
B
0
0
1
1
A
0
1
0
1
Output
Q
Q is the same as
S
O
Z
R
X
T
P
Complete the truth table below for the NAND equivalent circuit.
Inputs
B
0
0
1
1
6.
A
0
1
0
1
Output
Q
A
A
B
Q is the same as
B
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Module ET1
Introduction to Analogue and Digital Systems.
Converting Logic Diagrams to NAND gates.
The process for converting logic system diagrams into NAND gate format is
quite straightforward if you work logically through the circuit. Each gate is
replaced in turn by its NAND equivalent, and connected up in the same way.
We will look at an example to show how this is done.
Example 1: Convert the following logic system into NAND gates only.
B
C
In this case we need to replace a NOT gate, OR gate and an AND gate.
Stage 1: Redraw the NAND equivalent circuits of the gates shown above,
where possible retain the position of these gates so that you can
identify the connections afterwards.
A
Q
B
C
A
Q
B
C
This circuit is now the equivalent circuit to that using in NOT, OR and
AND gate given earlier, however there is one further simplification we
can make.
Stage 3 : Consider the circuit again as shown below.
2
A
B
C
If you look carefully at the two NAND gates labelled 1 & 2, we can see
that these are both configured to be inverters or NOT gates. If we
consider what happens to signal A as it passes through these two gates
we have the following:
AAAA
Therefore gates 1 and 2, serve no useful purpose in this circuit, and are
known as redundant gates and can be removed. We call this double
inversion and it occurs commonly when creating NAND gate circuits
from other logic systems.
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Module ET1
Introduction to Analogue and Digital Systems.
In an examination you are usually asked to cross out any redundant gates, so
if this was an examination you would end up with the following circuit.
A
Q
B
C
Occasionally, you will be asked to redraw the circuit, with redundant gates
removed in which case the final circuit would be as follows:
A
Q
B
A
As has been the case with other examples we have taken our time with this
one to illustrate each stage of the simplification process. Most of these
steps can be carried out in just a couple of stages but there are a couple of
things that will help to ensure that you dont make mistakes that in an
examination could cost you a lot of marks.
i.
ii.
iii.
iv.
10
identify each of the gates from the original circuit and their NAND
equivalent.
connect each equivalent NAND gate circuit as per the original
diagram.
identify and cross out and redundant gates caused by double
inversions.
do not try to remove double inversions in your head, as you can
easily forget which ones you have done and leave some out.
A
B
CB
First of all we will replace all of these gates with their NAND equivalent and
connect them together.
Finally we check for any redundant gates, and identify these.
A
Note the way in which different pairs of redundant gates are marked.
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Module ET1
Introduction to Analogue and Digital Systems.
Now here are a couple for you to try.
Exercise 1:
1.
(a)
Redraw the following logic circuit using 2 input NAND gates only.
A
B
Q
C
(b)
12
(a)
Redraw the following logic circuit using 2 input NAND gates only.
A
Q
B
(b)
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Module ET1
Introduction to Analogue and Digital Systems.
Multiple Redundancy.
As we have seen in the examples so far we can have a situation arising
A
whereby a pair of NAND inverters can be removed from the system. Very
occasionally a situation of multiple redundancy may occur, and needs to very
carefully spotted.
easier
A
Q
B
C
In
gate
this
NAND
format,
becomes
B
Q
*
14
C
The issue is what to do with the three gates marked with a * in the diagram.
Actually we can eliminate all three gates, since the output of the both right
hand gates will be A, so in this case we must eliminate all three NOT gates,
otherwise the wrong output will be obtained. (You might like to try this by
only cancelling two out of the three gates and checking the resulting outputs.)
We can explain this by comparing the following equivalent circuits.
A
is the same as
is the same as
A
Q
B
Q
*
C
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Module ET1
Introduction to Analogue and Digital Systems.
The area to look at is where there is a junction between two NAND gates
connected as inverters as shown by the area enclosed by the box above.
When this situation arises you must check to see what is at the other end the
junction. In this case it is another NAND inverter and so we can cancel the
three gates out as part of the same redundancy.
A
B
Q
16
A
Q
B
C
In
gate format, this becomes
A
NAND
B
Q
C
At first
glance
the three gates marked with a * look like the previous circuit. However,
there is a huge difference. Whilst the top two gates are the same, the
junction between them leads to one input of a NAND gate. The second
input of this NAND gate is connected to input C.
In this case we cannot delete three gates, as doing so will change the
function of the circuit.
We can however delete the top two gates, provided we add a NAND
inverter to provide the input to the lower gate which has to be the
inverse of A i.e. a net saving of 1 gate. The circuit becomes:
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Module ET1
Introduction to Analogue and Digital Systems.
Redundant gates cancelled
A
B
Extra Inverter added
C
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Module ET1
Introduction to Analogue and Digital Systems.
Solutions to Student Exercises.
ExNOR gate from Page 7.
A
Q
B
Exercise 1:
1.
A
B
Q
C
2.
A
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(a)
Write down the Boolean expressions for the outputs Q1, Q2, Q3, and Q4 in terms of the
inputs A and B for the following system.
Q1 = ..........................................................................
Q2 = ..........................................................................
Q3 = ..........................................................................
Q4 = ..........................................................................
[4]
(b)
In the space below, draw the same logic system, but with the logic gates replaced by their
NAND equivalents.
[3]
(c)
Module ET1
Introduction to Analogue and Digital Systems.
2.
(a)
Write down Boolean expressions for the outputs L, M, and Q in terms of the inputs A, B
and C.
L = ........................................................................
M = ........................................................................
Q = ........................................................................
[3]
(b)
(i)
Redraw the logic system shown above, replacing each logic gate with its NAND
gate equivalent.
(ii)
Identify any redundant gates in the system you have just drawn.
(iii)
[3]
[2]
[1]
22
Write down Boolean expressions for the outputs X, Y, and Q in terms of the inputs A and
B.
X = ........................................................................
Y = ........................................................................
Q = ........................................................................
[3]
(b)
(i)
Redraw the logic system shown above, replacing each logic gate with its NAND
gate equivalent.
(ii)
Identify any redundant gates in the system you have just drawn.
(iii)
Explain why it can be cheaper to convert logic systems to their NAND gate
equivalents.
[3]
[1]
..................................................................................................................................................
..................................................................................................................................................
..................................................................................................................................................
[1]
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Module ET1
Introduction to Analogue and Digital Systems.
4.
(a)
Redraw the logic system shown above, replacing each logic gate with its NAND gate
equivalent.
(b)
Identify any redundant gates in the system you have just drawn.
[3]
[1]
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Module ET1
Introduction to Analogue and Digital Systems.
5.
(a)
Show how a logic system can be made up, using AND, OR and NOT gates, for the
expression:
Q B A.C
[3]
(b)
(c)
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(a)
A
0
0
1
1
B
0
1
0
1
[3]
(b)
In the space below, draw the same logic system, but with the logic gates replaced by their
NAND gate equivalents.
[3]
(c)
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Module ET1
Introduction to Analogue and Digital Systems.
7.
(a)
(i)
In the space below, draw the same logic system, but with the logic gates replaced
by their NAND gate equivalents.
[3]
(ii)
How many pairs of redundant gates are there in this system ? ............................
[1]
(b)
[1]
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Learning Objectives
1.
2.
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