FPGA Based Efficient Implementation of Viterbi Decoder: Anubhuti Khare
FPGA Based Efficient Implementation of Viterbi Decoder: Anubhuti Khare
I.INTRODUCTION
A. Convolutional Encoder
Convolutional code is a type of error-correcting code in
which each (nm) m-bit information symbol (each mbit
string) to be encoded is transformed into an n-bit symbol,
where m/n is the code rate (nm) and the transformation is a
function of the last k information symbols, where K is the
constraint length of the code.
B. Viterbi Algorithm
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C. Viterbi Decoder
The basic units of Viterbi decoder are branch metric unit,
add compare and select unit and survivor memory
management unit.
1) Branch Metric Unit
The first unit is called branch metric unit. Here the
received data symbols are compared to the ideal outputs of
the encoder from the transmitter and branch metric is
calculated. Hamming distance or the Euclidean distance is
used for branch metric computation.
85
Value(bits)
Input
Output
Code rate
Constraint length
86
2) Simulation
Simulator is a software program to verify functionality of a
circuit. The functionality of code is checked. The inputs are
applied and corresponding outputs are checked. If the
expected outputs are obtained then the circuit design is
correct. Simulation gives the output waveforms in form of
zeros and ones. Although problems with the size or timing
of the hardware may still crop up later, the designer can at
least be sure that his logic is functionally correct before
going on to the next stage of development.
3) Implementation
Device implementation is done to put a verified code on
FPGA. The various steps in design implementation are:
1. Translate
2. Map
3. Place and route
4. Configure
The full design flow is an iterative process of entering,
implementing, and verifying your design until it is correct
and complete. The Xilinx Development System allows
quick design iterations through the design flow cycle. Xilinx
devices permit unlimited reprogramming.
87
182
3
14
2
195
24
7%
8%
88
2,395
3,584
66%
2,395
2,395
100%
2,395
0%
3,064
7,168
42%
REFERENCES:
2,773
142
2
1
195
24
Parameter
Using
Traceback
scheme
Number of
Slices
registers
133 (3 %)
Number of
Slice Flip
Flops
97
Number of
4 input
LUTs
Number of
bonded
IOBs
Number of
BRAMs
Number of
GCLKs
Using
Register
Exchange
scheme
2381 (66
%)
[3] Inyup Kang, Member IEEE and Alan N. Wilson (1998). Low
Available
in Spartan
3A
XC3S400A
FPGA
[4]
[5]
[6]
3564
[7]
(1 %)
1898 (26
%)
7168
[8]
[9]
182 (1 %)
2906 (40
%)
14
(7 %)
2
(1
%)
(5 %)
2
(10
%)
20
(8%)
2
(8
%)
24
7168
[10]
89
Probability of Error
Viterbi decoder, First International
Conference on Emerging Trends in Engineering and Technology,
IEEE, 2008.
Kelvin Yi-Tse Lai, An Efficient Metric Normalization Architecture
for High-speed Low- Power Viterbi Decoder, IEEE 2007.