HCS12 Timer System PDF
HCS12 Timer System PDF
The HCS12 has a standard timer module (TIM) that consists of:
The TIM block diagram is shown in the diagram. The Bus Clock for the MC9S12DP256B runs at 24 MHz
- address $0050
- address $0052
- address $005E
Setting and clearing bit 7 (TEN) of TSCR1 will also start and stop the counting of the TCNT counter.
Setting bit 4 (TFFCA) will enable fast timer flag clear function. If this bit is clear, then the user must write
a one to a timer flag in order to clear it.
TEN Timer Enable bit
0 - disable timer - can be used to save power
1 - enable timer
TSWAI - timer stops while in wait mode
0 - allows timer to continue running during wait mode
1 - disables timer when HCS12 is in wait mode
TSFRZ - timer and modulus counter stop while in freeze mode
0 - allows timer and modulus counter to continue running during freeze mode
1 - disables timer and modulus counter when HCS12 is in freeze mode
TFFCA - timer fast flag clear all bit
0 - allows timer flag clearing to work normally
1 - for TFLG1, a read from an input capture or a write to the output compare channel causes
the corresponding channel flag, CnF, to be cleared. For TFLG2, any access to the TCNT
register clears the TOF flag. Any access to the PACN3 and PACN2 registers clears the PAOVF
and PAIF flags in the PAFLG register. Any access to the PACN1 and PACN0 registers clears
the PBOVF flag in the PBFLG register.
Timer System Control Register 2 (TSCR2) - address $004D
The main use of this register is to set the pre-scale value for the timer clock frequency
Pre-Scale Computations
The Timer function of the HCS12 microcontroller uses a 16 bit free-running counter called TCNT. The
maximum count is 216 -1 with a total of 216 = 65,536 counts (0 to 65535 counts).
The MC9S12DP256B microcontroller has an E Clock of 24 MHz. The longest time that can be measured
with this clock and a pre-scale value of 1 is thus:
Tlongest = 65,536/24Mhz = 2.74 msec.
The use of a pre-scale factor larger than 1 is necessary if measuring longer times. Pre-scale values range
from 1 to 128 in binary multiples. If the pre-scale value is 2, then the value of the pre-scaled Timer clock
is
Pre-scaled clock = 24 MHz /2 = 12 MHz
The Table shows the choice of possible pre-scale values
Pre-scale value
E Clock
Pre-scaled clock
24 MHz
12 MHz
2.74 msec
24 MHz
6 MHz
10.9 msec
24 MHz
3 MHz
21.8 msec
16
24 MHz
1.5 MHz
43.7 msec
32
24 MHz
750 kHz
87.4 msec
64
24 MHz
375 kHz
175 msec
128
24 MHz
187.5 kHz
350 msec
Questions
What pre-scale value is needed to measure a time delay of 100 msec?
TOF
Only bit 7 is used. Bit 7 will be set when overflow of TCNT occurs
Timer Function Applications
Example: The command movb #$F0, TIOS will enable channels 0 to 3 as Input Capture and channels
4 to 7 as Output Compare.
Use of Input Capture
Physical time is often represented by the contents of the main timer. The occurrence of an event is
represented by a rising or falling edge of a signal waveform. The time when an event occurs can be
recorded by latching the count of the main timer into a register when a signal edge arrives as illustrated
in the diagram.
Timer Control Registers 3 and 4 (TCTL3 and TCTL4) - address $004A and $004B
The signal edge to be captured is specified by TCTL3 and TCTL4 and can be a rising edge, a falling edge or
both edges.
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
As the counter TCNT counts up it is compared with the appropriate TCx register after each count. If they
match the corresponding bit for that channel is set to a 1. In appropriate applications such as Input
Capture, this would indicate that an edge has been detected.
To clear a bit in TFLG1, write a 1 to the appropriate bit. Alternately setting the TFFCA bit in the TRSC1
register allows the clearing of a flag by reading the corresponding Input Capture register or writing a
value to the Output Capture register.
Applications of Input Capture
Input Capture can be used as an Event Arrival Time Recording mechanism. The period of a waveform
can be measured by capturing the TCNT timer value for two corresponding rising or falling edges.
Measurement of Period
If period and pulse width have both been measured then the Duty Cycle of a waveform can be
determined.
Calculation of Duty Cycle
TIOS:
equ
TSCR1:
equ
TSCR2:
equ
TCTL4:
equ
TFLG1:
equ
TC0:
equ
;mask values
IOS0:
equ
C0F:
equ
edge1:
edge2:
period:
$40
$46
$4D
$4B
$4E
$50
;address
;address
;address
;address
;address
$01
$01
TIOS register
TSCR1 register
TSCR2 register
TCTL4 register
TFLG1 register
readPeriod:
movb #$90,TSCR1
bclr TIOS,IOS0
movb #$04,TSCR2
movb #$01,TCTL4
movb #C0F,TFLG1
brclr TFLG1,C0F,*
ldd
TC0
std
edge1
brclr TFLG1,C0F,*
ldd
TC0
std
edge2
subd edge1
std
period
swi
C Code
of
of
of
of
of
void main(void) {
unsigned int edge1, period;
TSCR1 = 0x90;
/* enable timer counter */
TIOS &= ~IOS0;
/*enable Input Capture 0 */
TSCR2 = 0x04;
/*set pre-scale to 16 */
TCTL4 = 0x01;
/* capture rising edge of wave form at PT0 */
TFLG1 = 0x01;
/* clear C0F flag */
while (!(TFLG1 & C0F));
/* wait for first rising edge */
st
edge1 = TC0;
/* save 1 captured edge and clear C0F flag */
while (!(TFLG1 & C0F));
/* wait for 2nd rising edge */
period = TC0 - edge1;
asm(swi);
}
Taking the 2s compliment of FD12 gives the value of 02EE. Fortunately for us the software takes into
account when edge1 is less or greater than edge2 and gives the correct result.
TCNT Counter Circular Pictorial
Edge2 > Edge1
Reset point
Edge1
Edge2
Edge2
10
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The value stored in TCx (the future event) will be compared to the current value of TCNT in every clock
cycle. If they are equal (a successful compare has occurred) the corresponding flag bit in theTFLG1
register will be set.
Applications of the Output Compare Function
Generating a Square Wave
The Output Compare function can be used to generate wave forms by adding calculated values
(representing the high and low times for a square wave for example) to a copy of the free running
counter TCNT.
Create an active high square wave at 1 kHz with a 30 % duty cycle. Use a pre-scale value of 8.
Period T = 1/1 kHz = 1 msec
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Assembler Code
TCNT:
TIOS:
TSCR1:
TSCR2:
TCTL2:
TFLG1:
TC0:
OC0:
C0F:
hi_time:
lo_time:
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
$44
$40
$46
$4D
$49
$4E
$50
$01
$01
900
2100
ORG
$2000
movb #$90,TSCR1
movb #$03,TSCR2
bset TIOS,OC0
movb #$03,TCTL2
ldd TCNT
repeat:
addd #lo_time
std TC0
brclr TFLG1,C0F,*
movb #$02,TCTL2
ldd TC0
addd #hi_time
std TC0
brclr TFLG1,C0F,*
movb #$03,TCTL2
ldd TC0
bra repeat
swi
end
C Code
;counter address
;Input/output compare select address
;TSCR1 address
;TSCR2 address
;Timer control register 2 address
;Timer interrupt flag register address
;address of PORT T, PTO (TC0)
;enable OC0 mask
;clear C0F flag mask
;hi_time value
;lo_time value
#include <hidef.h>
#include "derivative.h"
#define hi_time 900
#define lo_time 2100
#define OC0 0x01
#define C0F 0x01
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C Code Implementation
This application is particularly useful as it is very difficult to calculate from theory the delay value
needed for a for loop delay subroutine in C code. Using the Output Compare timer function
makes it easy.
// Creates a 200 sec delay
Void Delay (void) {
TSCR1 = 0x90;
TSCR2 = 0x01;
TIOS |= 0x01;
TC0 = TCNT + 2400;
while(!(TFLG1 & 0x01));
}
Pre- scale factor set to 2. The pre-scaled clock frequency is 24 MHz/2 = 12 MHz
delay value = delay time x clock freq = 100 sec x 12 MHz = 2400
Application Note
Written by David Lloyd
Computer Engineering Program
Humber College
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