UCC28880 700-V Lowest Quiescent Current Off-Line Switcher: 1 Features 3 Description
UCC28880 700-V Lowest Quiescent Current Off-Line Switcher: 1 Features 3 Description
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UCC28880
SLUSC05A JULY 2014 REVISED OCTOBER 2014
3 Description
PACKAGE
SOIC (7)
2 Applications
Simplified Schematic
40
UCC28880
GND DRAIN
GND
FB
VDD
35
8
30
NC
HVIN
Power (mW)
VIN
25
20
15
10
VOUT
-
5
0
50
150
200
AC Input Voltage (VRMS)
250
300
D015
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UCC28880
SLUSC05A JULY 2014 REVISED OCTOBER 2014
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
3
4
4
4
5
6
7
4 Revision History
Changes from Original (August, 2014) to Revision A
Page
UCC28880
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DRAIN
GND
FB
NC
VDD
HVIN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
GND
Ground
GND
Ground
FB
Feedback terminal
VDD
HVIN
Supply pin
NC
N/C
DRAIN
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
HVIN
0.3
DRAIN
Internally
clamped
IDRAIN
IDRAIN
MAX
UNIT
700
(3)
700
(3)
320
320
mA
mA
FB
0.3
VDD
0.3
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. These ratings apply over the
operating ambient temperature ranges unless otherwise noted.
TA = 25C
UCC28880
SLUSC05A JULY 2014 REVISED OCTOBER 2014
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MIN
MAX
65
150
V(ESD)
(1)
(2)
Electrostatic discharge
UNIT
C
260
2000
2000
1500
1500
500
500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
NOM
MAX
UNIT
VVDD
VFB
Voltage on FB pin
0.2
V
V
TA
40
105
TJ
40
125
SOIC (D)
UNIT
7 PINS
RJA
134.4
RJC(top)
42.6
RJB
85
JT
6.4
JB
76
(1)
C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
UCC28880
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
VHVIN(min)
30
INL
58
100
IFL
72
120
ICH0
VVDD = 0 V,
ICH1
VVDD
VFB_TH
VVDD(on)
VDD low-to-high
VVDD(uvlo)
DMAX
ILIMIT
Current Limit
3.8
1.6
0.4
mA
3.40
1.30
0.25
mA
4.5
5.0
5.5
0.94
1.02
1.10
3.55
3.92
4.28
VDD high-to-low
0.28
0.33
0.38
FB = 0.75 V
45%
55%
Static, TA = 40C
Static, TA = 25C
170
Static, TA = 125C
140
210
300
mA
260
mA
mA
TJ(stop)
Thermal Shutdown
Temperature
150
TJ(hyst)
50
BV
TJ = 25C
ID = 30 mA, TJ = 25C
32
40
RDS(on)
ID = 30 mA, TJ = 125C
55
68
DRAIN_ILEAKAGE
HVIN_IOFF
700
4.0
7.5
20
12.0
20
UCC28880
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TEST CONDITIONS
MIN
TYP
MAX
UNIT
52
62
75
kHz
fSW(max)
tON_MAX
FB = 0.75 V
5.7
7.6
9.5
tOFF_MIN
FB = 0.75 V
5.7
7.6
9.5
tMIN
Minimum on time
0.17
0.22
0.30
tOFF(ovl)
130
200
270
UCC28880
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1.17
1.14
1.11
1.08
1.05
1.02
0.99
0.96
0.93
0.9
0.87
-40
-20
20
40
60
80
Temperature (C)
100
120
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
-40 C
25C
125C
0.6
0.5
0.4
140
100
D001
600 650
1.5
1.2
1.15
1.1
1.05
1
0.95
0.9
IFL
INL
0.85
-40
-20
20
40
60
80
Temperature (C)
100
120
ICH0
ICH1
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
-40
140
-20
20
D001
40
60
80
Temperature (C)
100
120
140
D001
1.01
500
VDD(on)
VDD(uvlo)
1.0075
450
200
300
400
500
Drain Current Slope (mA/s)
D001
1.005
1.0025
1
0.9975
0.995
0.9925
0.99
400
350
300
250
200
150
100
IDRAIN 25C
IDRAIN 125C
50
0.9875
-40
-20
20
40
60
80
Temperature (C)
100
120
140
D001
10
15
20 25 30 35 40 45
Drain Source Voltage (V)
50
55
D001
60
UCC28880
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1.02
1.02
1.01
1.01
1
0.99
0.98
0.97
1
0.99
0.98
0.97
0.96
-50
50
Temperature (C)
100
0.96
-40
150
-25
20 35 50 65
Temperature (C)
80
95
110 125
D005
1.045
2.6
1.04
1.035
1.03
LMIN/VIN(PH/V)
2.7
1.05
1.025
1.02
1.015
1.01
2.5
2.4
2.3
1.005
2.2
1
TOFF(min)
TON(max)
0.995
0.99
-40
2.1
-20
20
40
60
80
Temperature (C)
100
120
140
D001
-10
D012
30
60
90
Temperature (C)
120
150
D014
UCC28880
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7 Detailed Description
7.1 Overview
The UCC28880 integrates a controller and a 700-V power MOSFET into one monolithic device. The device also
integrates a high-voltage current source, enabling start up and operation directly from the rectified mains voltage.
The low-quiescent current of the device enables excellent efficiency. The device is suitable for non-isolated ACto-DC low-side buck and buck-boost configurations with level-shifted direct feedback, but also more traditional
high-side buck, buck boost and low-power flyback converters with low standby power can be built using a
minimum number of external components.
The device generates its own internal low-voltage supply (5 V referenced to the devices ground, GND) from the
integrated high-voltage current source. The PWM signal generation is based on a maximum constant ON-time,
minimum OFF-time concept, with the triggering of the ON-pulse depending on the feedback voltage level. Each
ON-pulse is followed by a minimum OFF-time to ensure that the power MOSFET is not continuously driven in an
ON-state. The PWM signal is AND-gated with the signal from a current limit circuit. No internal clock is required,
as the switching of the power MOSFET is load dependent. A special protection mechanism is included to avoid
runaway of the inductor current when the converter operates with the output shorted or in other abnormal
conditions that can lead to an uncontrolled increase of the inductor current. This special protection feature keeps
the MOSFET current at a safe operating level. The device is also protected from other fault conditions with
thermal shutdown, under-voltage lockout and soft-start features.
High Voltage
Current Source
8
Thermal
Protection
VDD
Gate
LDO
UVLO
DRAIN
Q
Current
Limit
Control and
Reference
IFB = 1 V
+
FB
PWM Controller
and Output Short
Circuit Protection
Leading Edge
Blanking Time
LEB
1, 2
GND
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10
UCC28880
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t
FB_COMP_OUT
t
PWM
t
CURRENT LIMIT
t
RSTN
GATE
t
tON(max)
tOFF(min)
tON(max)
tOFF(min)
tON(max)
tOFF(min)
tON(max)
tOFF(min)
11
UCC28880
SLUSC05A JULY 2014 REVISED OCTOBER 2014
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tOFF
PWM
t
Current Limit
t
LEB
~200 ns
~200 ns
tON_TO
tON_TO
tON_TO
t
Increase tOFF
( Decrease fSW )
Decrease tOFF
(Increase fSW )
CNT_IN
Gate
tON
tON
UCC28880
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ILIMIT
INDUCTOR
CURRENT
DRAIN
CURRENT
tON_TO
t
GATE
tON_TO
tON < tON_TO
tON_TO
tON < tON_TO
tON_TO
tON < tON_TO
tON_TO
L
L ! MIN TR(max) u VIN(max)
VIN MIN
(1)
13
UCC28880
SLUSC05A JULY 2014 REVISED OCTOBER 2014
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D2
1N4937
L2
1 mH
C2
4.7 PF
400 V
HVIN
C1
4.7 PF
400 V
VDD
RFB1
590 k:
+/- 1%
D1
600 V
W5575 ns
L1
2.2 mH
330 mA
+
CL
4.7 PF
16 V
RL
402 k:
Q1
500 V
VOUT
12 V
100 mA
-
DRAIN
UCC28880
AC
(115 V/230 V)
CVDD
100 nF
10 V
FB
GND
RFB2
51 k:
+/- 1%
D3
1N4007
MIN
MAX
UNIT
Design Input
VIN
AC input voltage
85
265
VRMS
fLINE
Line frequency
47
63
Hz
IOUT
Output current
100
mA
50
mW
Design Requirements
PNL
VOUT
Output voltage
VOUT
Converter efficiency
14
12
13
350
mV
68%
UCC28880
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Resistor RF is a flame-proof fusible resistor. RF limits the inrush current, and also provide protection in case
any component failure causes a short circuit. Value for its resistance is generally selected between 4.7 to
15 .
A half-wave rectifier is chosen and implemented by diode D2 (1N4937). It is a general purpose 1-A, 600-V
rated diode. It has a fast reverse recovery time (200 ns) for improved differential-mode-conducted EMI noise
performance. Diode D3 (1N4007) is a general purpose 1-A, 1-kV rated diode with standard reverse recovery
time (>500 ns), and is added for improved common-mode-conducted EMI noise performance. D3 can be
removed and replaced by a short if not needed.
EMI filtering is implemented by using a single differential-stage filter (C1-L2-C2).
Capacitors C1 and C2 in the EMI filter also acts as storage capacitors for the high-voltage input DC voltage
(VIN).The required input capacitor size can be calculated according formula (1).
VBULK(min)
2 u PIN
1
1
u
u arccos
2 u VIN(min)
fLINE(min) RCT 2 u S
CBULK min
2
2
VIN(min)
VBULK(min)
where
CBULK(min) is minimum value for the total input capacitor value (C1 + C2 in the schematic of Figure 14).
RCT = 1 in case a single wave rectifier and RCT = 2 in case of full-wave rectifier (for the schematic reported in
Figure 20 RCT = 1 because of a single rectifier).
PIN is the converter input power.
VIN(min) is the minimum RMS value of the AC input voltage.
VBULK(min) is the minimum allowed voltage value across bulk capacitor during converter operation.
fLINE(min) is the minimum line frequency when the line voltage is VIN(min).
The converter maximum output power is: POUT = IOUT x VOUT = 0.1 A x 12.5 V = 1.25 W
Assuming the efficiency = 68.% the input power is PIN = POUT/ = 1.765 W
VBULK(min) = 80 V
VIN(min) = 85 VRMS (from design specification table)
fLINE(min) = 57 Hz
(2)
CBULK(min) = 6.96 F. Considering that electrolytic capacitors, generally used as bulk capacitor, have 20% of
tolerance in value, the minimum nominal value required for CBULK is:
CBULK(min)
CBULKn(min) !
8.7 PF
1 TOLCBULK
(3)
Select C1 and C2 to be 4.7F each (CBULK = 4.7 F + 4.7 F = 9.4 F > CBULKn(min)).
By using a full-wave rectifier allows a smaller capacitor for C1 and C2, almost 50% smaller.
8.2.1.2.2 Regulator Capacitor (CVDD)
Capacitor CVDD acts as the decoupling capacitor and storage capacitor for the internal regulator. A 100-nF, 10-V
rated ceramic capacitor is enough for proper operation of the device's internal LDO.
15
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The freewheeling diode has to be rated for high-voltage with as short as possible reverse-recovery time (trr).
The maximum reverse voltage that the diode should experience in the application, during normal operation, is
given by Equation 4.
VD1(max)
2 u VIN(max)
2 u 265V 375V
(4)
Initial calculations:
Ripple current at full load:
'IL
(5)
Average MOSFET conduction minimum duty cycle at full load and maximum input voltage is:
VOUT Vd
DMIN
VIN(max) Vd
(6)
(7)
FSW _ VIN(max)
(8)
(9)
FSW _ VIN(max)
fSW(max)
66kHz
(10)
The duty cycle does not force the MOSFET on time to go below tON_TO. If DMIN/TON_TO < fSW(max), the switching
frequency is reduced by current runaway protection and the maximum average switching frequency is lower than
fSW(max).
The minimum inductance value satisfies both the following conditions:
VOUT Vd
L1 !
2mH
'IL u fSW _ VIN(max)
VIN(max)
u tON _ TO
L1 ! MIN MIN TJ(max) u VIN(max) L1 !
ILIMIT
VIN
(11)
PH
2.65 u V u 375 V # 1 mH
(12)
In the application example, 2.2 mH is selected as the minimum standard value that satisfy Equation 11 and
Equation 12.
16
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The value of the output capacitor impacts the output ripple. Depending on the combination of capacitor value and
equivalent series resistor (RESR). A larger capacitor value also has an impact on the start-up time. For a typical
application, the capacitor value can start from 47 F, to hundreds of F. A guide for sizing the capacitor value
can be calculated by the following equations:
ILIMIT IOUT
270mA 100mA
CL ! 4 u
4u
30 PF
fSW(max) u 'VOUT
350mV u 66kHz
(13)
RESR
'VOUT
ILIMIT
1:
(14)
Take into account that both CL and RESR contribute to output voltage ripple. A first pass capacitance value can be
selected and the contribution of CL and RESR to the output voltage ripple can be evaluated. If the total ripple is
too high the capacitance value has to increase or RESR value must be reduced. In the application example CL
was selected (47 F) and it has an RESR of 0.3 . So the RESR contributes for 1/3 of the total ripple. The formula
that calculates CL is based on the assumption that the converter operates in burst of four switching cycles. The
number of bursts per cycle could be different, the formula for CL is a first approximation.
8.2.1.2.6 Load Resistor (RL)
The resistor should be chosen so that the output current in any standby/no-load condition is higher than the
leakage current through the integrated power MOSFET. If the standby load current is ensured to always be
larger than the specified ILEAKAGE, the RL is not needed. If OVP protection is required for safety reasons, then a
zener could be placed across the output (not fitted in the application example). In the application example RL =
402 k. This ensures a minimum load current of at least ~30 A when VOUT = 12 V.
17
UCC28880
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The feedback path of Q1, RFB1 and RFB2 implements a level-shifted direct feedback. RFB2 sets the current
through the feedback path, and RFB1 sets the output voltage. Q1 acts as the level shifter and needs to be rated
for high voltage. The output voltage is determined as follows:
R
VOUT VFB _ TH u FB1 VBE
RFB2
where
For the application example a target of ~20-A of current is selected through the external feedback path (IFB).
VFB _ TH
1.0 V
RFB2
50k:
IFB
| 20 PA
(16)
Choose a standard resistor size for RFB2 = 51 k. For the high-voltage PNP transistor choose a 500-V rated
transistor with a VBE 0.5 V for the feedback current. To achieve the 12-V output voltage RFB1 needs to be:
V OUT VBE
12 V 0.5 V
u RFB1
u 51 k: 586k:
RFB1
VFB _ TH
1V
(17)
Choose a standard resistor size for RFB1 = 591 k.
To change the output voltage, change the value for RFB1. For example, to target a 5-V output voltage, RFB1
should be changed to a 230-k resistor.
Accuracy of the output-voltage level depends proportionally on the variation of VFB_TH, and on the absolute
accuracy of VBE according to Equation 16 and Equation 17.
The current through the feedback path is connected over the high voltage input (VIN), and this feedback current
is always on. Higher current provides less noise-sensitive feedback, the feedback current should be minimized in
order to minimize the total power consumption.
18
UCC28880
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90
80
85 V
115 V
230 V
265 V
12
Output Voltage (V)
Efficiency (%)
70
60
50
40
30
85 V
115 V
230 V
265 V
20
10
10
8
6
4
2
0
0
0.5
1
1.5
Output Power (W)
2.5
0.05
D016
0.1
0.15
Ouput Current (A)
0.2
0.25
D017
Table 2 shows converter efficiency. Table 3 shows the converter input power in no-load conditions and output
shorted conditions. The no-load condition shows the converter stand-by performance.
Table 2. Converter Efficiency
VIN_AC (VRMS)
115
230
LOAD (mA)
EFFICIENCY (%)
25
80.3
50
81.4
75
81.6
100
81.9
25
78.5
50
81.1
75
82.1
100
82.7
81.3
81.2
85
16
453
214
115
19.5
435
213
140
22.5
417
211
170
26
443
213
230
33
430
209
265
37.5
344
182
19
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L2
D2
HVIN
VDD
UCC28880
CVDD
C1
DRAIN
RFB1
FB
VIN
C2
GND
CFB
RFB2
D4
L1
CL
D1
D3
RL
+
VOUT
-
MIN
MAX
UNIT
Design Input
VIN
AC input Voltage
85
265
fLINE
Line frequency
47
63
VRMS
Hz
IOUT
Output current
100
mA
50
mW
14
250
mV
Design requirements
PNL
VOUT
Output voltage
VOUT
Converter efficiency
20
12
68%
UCC28880
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In low-side buck converter the output voltage is always sensed by the FB pin and UCC28880 internal controller
can turn on the MOSFET on VOUT. In high-side buck converter applications the information on the output
voltage value is stored on CFB capacitor. This information is not updated in real time. The information on CFB
capacitor is updated just after MOSFET turn-off event. When the MOSFET is turned off, the inductor current
forces the freewheeling diode (D1 in Figure 17) to turn on and the GND pin of UCC28880 goes negative at -Vd1
(where Vd1 is the forward drop voltage of diode D1) with respect to the negative terminal of bulk capacitor (C1 in
Figure 17). When D1 is on, through diode D4, the CFB capacitor is charged at VOUT Vd4 + Vd1. Set the output
voltage regulation level using Equation 18.
RFB1 VOUT(T) Vd4 Vd1 VFB _ TH VOUT(T) VFB _ TH
#
RFB2
VFB _ TH
VFB _ TH
where
WFB
1
CFB u RFB1 RFB2 #
u CL u RL
10
(18)
(19)
The time constant selection leads to a slight output-voltage increase in no-load or light-load conditions. In order
to reduce the output-voltage increase, increase FB. The drawback of increasing FB is t in high-load conditions
VOUT could drop.
21
UCC28880
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10
Efficiency (%)
12
8
6
4
85 V
115 V
230 V
265 V
2
0
0
0.2
0.225
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
85 V
115 V
230 V
265 V
0
0.25
0.5
0.75
1
1.25 1.5
Output Power (W)
D018
1.75
2.25
D020
LOAD (mA)
EFFICIENCY (%)
115
25
75.2
76.8
50
77.1
230
75
77.6
100
77.7
25
72.6
50
75.1
75
75.7
100
76.3
74.8
22
VIN (VRMS)
85
31
415
212
115
34
399
209
140
36
414
211
170
38
401
208
230
44
394
195
265
47
333
174
UCC28880
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RFB1
D1
+
CL
VDD
VIN
Q1
L1
HVIN
VOUT
DRAIN
UCC28880
FB
GND
RFB2
RSENSE
C1
R2
D1
RFB1
CL
R1
Q2
Current Feedback
VIN
-
L1
HVIN
VDD
VOUT
DRAIN
Q1
UCC28880
FB
GND
RFB1
23
UCC28880
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HVIN
VDD
+
DRAIN
UCC28880
VIN
FB
10
GND
D2
CFB
RFB2
L1
+
CL
D1
VOUT
-
VOUT
D1
VDD
+
L1
HVIN
DRAIN
UCC28880
VIN
FB
GND
RFB2
24
UCC28880
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HVIN
VDD
DRAIN
UCC28880
+
FB
VIN
RFB1
GND
D2
CFB
RFB2
D1
+
VOUT
-
CL
L1
RFB2
RFB1
CL
HVIN
VDD
VIN
-
+
VOUT
-
DRAIN
UCC28880
CVDD
FB
GND
RFB2
25
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RFB2
CL
HVIN
VDD
VIN
-
+
VOUT
-
DRAIN
UCC28880
CVDD
FB
GND
RFB
26
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10 Layout
10.1 Layout Guidelines
In both buck and buck-boost low-side configurations, the copper area of the switching node DRAIN should be
minimized to reduce EMI.
Similarly, the copper area of the FB pin should be minimized to reduce coupling to feedback path. Loop CL,
Q1, RFB1 should be minimized to reduce coupling to feedback path.
In buck and buck-boost high side the GND, VDD and FB pins are all part of the switching node so the copper
area connected with these pins should be minimized
Minimum distance between 700-V coated traces is 1.41 mm (60 mils).
D2
RF
C1
C2
D3
60 mils
AC
INPUT
GND
DRAIN
L1
GND
D1
FB
NC
HVIN
VDD
VDD
RFB2
RFB1
Q1
= top layer
CL
= bottom layer
RL
DC
OUTPUT
27
UCC28880
SLUSC05A JULY 2014 REVISED OCTOBER 2014
www.ti.com
11.3 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
28
www.ti.com
16-Sep-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
UCC28880D
ACTIVE
SOIC
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28880
UCC28880DR
ACTIVE
SOIC
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
U28880
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
16-Sep-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
16-Sep-2014
Device
UCC28880DR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
16-Sep-2014
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28880DR
SOIC
2500
367.0
367.0
35.0
Pack Materials-Page 2
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