Memristor

The memristor (/mmrstr/; a portmanteau of memory resistor) was originally envisioned in 1971 by circuit
theorist Leon Chua as a missing non-linear passive twoterminal electrical component relating electric charge and
magnetic ux linkage.[1] According to the characterizing mathematical relations, the memristor would hypothetically operate in the following way: The memristors
electrical resistance is not constant but depends on the
history of current that had previously owed through the
device, i.e., its present resistance depends on how much
electric charge has owed in what direction through it in
the past. The device remembers its history - the so-called
non-volatility property:[2] When the electric power supply
is turned o, the memristor remembers its most recent
resistance until it is turned on again.[3][4]
Leon Chua has more recently argued that the denition
could be generalized to cover all forms of two-terminal
non-volatile memory devices based on resistance switching eects[2] although some experimental evidence contradicts this claim, since a non-passive nanobattery eect
is observable in resistance switching memory.[5] Chua
also argued that the memristor is the oldest known circuit
element, with its eects predating the resistor, capacitor
and inductor.[6]

An array of 17 purpose-built oxygen-depleted titanium dioxide

memristors built at HP Labs, imaged by an atomic force microscope. The wires are about 50 nm, or 150 atoms, wide.[12]
Electric current through the memristors shifts the oxygen vacancies, causing a gradual and persistent change in electrical resistance.[13]

In 2008, a team at HP Labs claimed to have found Chuas

missing memristor based on an analysis of a thin lm
of titanium dioxide;[7] the HP result was published in
Nature.[3] The memristor is currently under development
by various teams including Hewlett-Packard, SK Hynix
and HRL Laboratories.

voltage
v

charge
q
Capacitor
dq = Cdv
Resistor
dv = Rdi

Memristor
d = Mdq

dq

id

current
i

Inductor
d = Ldi

vd

These devices are intended for applications

in nanoelectronic memories,
computer logic
and
neuromorphic/neuromemristive
computer
architectures.[8] In October 2011, the team announced
the commercial availability of memristor technology
within 18 months, as a replacement for Flash, SSD,
DRAM and SRAM.[9] Commercial availability of new
memory was more recently estimated as 2018.[10] In
March 2012, a team of researchers from HRL Laboratories and the University of Michigan announced the rst
functioning memristor array built on a CMOS chip.[11]

flux

Conceptual symmetries of resistor, capacitor, inductor, and memristor.

Background

linear inductor (magnetic ux linkage vs. current). He

In his 1971 paper, Chua extrapolated a conceptual sym- then inferred the possibility of a memristor as another
metry between the nonlinear resistor (voltage vs. cur- fundamental nonlinear circuit element linking magnetic
rent), nonlinear capacitor (voltage vs. charge) and non- ux and charge. In contrast to a linear (or nonlinear) re1

2 MEMRISTOR DEFINITION AND CRITICISM

sistor the memristor has a dynamic relationship between

current and voltage including a memory of past voltages
or currents. Other scientists had proposed dynamic memory resistors such as the memistor of Bernard Widrow,
but Chua attempted to introduce mathematical generality.

Soni discussed some fundamental issues and problems in

the realization of memristors.[20] They indicated inadequacies in the electrochemical modelling presented in the
Nature paper "The missing memristor found"[3] because
the impact of concentration polarization eects on the
behavior of metalTiO-metal structures under voltage
or
current stress was not considered. This critique was reMemristor resistance depends on the integral of the inferred
to by Valov et al.[5] in 2013.
put applied to the terminals (rather than on the instantaneous value of the input as in a varistor).[3] Since the ele- Meuels and Soni[20] furthermore noted that the dynamic
ment remembers the amount of current that last passed state equations set up for a solely current-controlled memthrough, it was tagged by Chua with the name mem- ristor with the so-called non-volatility property[2] would
ristor. Another way of describing a memristor is as allow the violation of Landauers principle of the miniany passive two-terminal circuit element that maintains mum amount of energy required to change information
a functional relationship between the time integral of states in a system: In order to exhibit the non-volatility
current (called charge) and the time integral of voltage property requires that the internal memristor or infor(often called ux, as it is related to magnetic ux). The mation states are separated from each other by Gibbs
slope of this function is called the memristance M and is free energy barriers,[20] viz. there is always a lower limit
similar to variable resistance.
of energy requirement for changing a bit value in a bi[21]
The memristor denition is based solely on the fun- nary device.[22] This critique was adopted by Di Ventra
damental circuit variables of current and voltage and and Pershin in 2013. The concept of a solely currenttheir time-integrals, just like the resistor, capacitor and controlled memristor provides no physical mechanism
system to cope with inevitable
inductor. Unlike those three elements however, which enabling such a memristor
[20]
thermal
uctuations,
viz.
such a system would erratare allowed in linear time-invariant or LTI system theically
change
its
state
just
under
the inuence of white
ory, memristors of interest have a dynamic function with
[23]
current
noise.
Memristors
whose
resistance (memmemory and may be described as some function of net
ory)
states
depend
solely
on
the
current
or voltage hischarge. There is no such thing as a standard memristor.
tory
would
thus
be
unable
to
protect
their
memory states
Instead, each device implements a particular function,
against
unavoidable
JohnsonNyquist
noise
and permawherein the integral of voltage determines the integral of
nently
suer
from
information
loss,
a
so-called
stochascurrent, and vice versa. A linear time-invariant memristic catastrophe,[22] viz. such envisioned memristors cantor, with a constant value for M, is simply a conventional
resistor.[1] Manufactured devices are never purely mem- not exist as solid state devices in physical reality.
ristors (ideal memristor), but also exhibit some capaci- Other researchers noted that memristor models based
tance and resistance.
on the assumption of linear ionic drift do not account
for asymmetry between set time (high-to-low resistance
switching) and reset time (low-to-high resistance switchand do not provide ionic mobility values consistent
2 Memristor denition and criti- ing)
with experimental data. Non-linear ionic drift models
cism
have been proposed to compensate for this deciency.[24]
According to the original 1971 denition, the memristor was the fourth fundamental circuit element, forming a
non-linear relationship between electric charge and magnetic ux linkage. In 2011 Chua argued for a broader definition that included all 2-terminal non-volatile memory
devices based on resistance switching.[2] Williams argued
that MRAM, phase change memory and RRAM were
memristor technologies.[14] Some researchers argued that
biological structures such as blood[15] and skin[16] t the
denition. Others argued that the memory device under development by HP Labs and other forms of RRAM
were not memristors but rather part of a broader class
of variable resistance systems[17] and that a broader definition of memristor is a scientically unjustiable land
grab that favored HPs memristor patents.[18]
In 2011, Meuels and Schroeder noted that one of the
early memristor papers included a mistaken assumption
regarding ionic conduction.[19] In 2012, Meuels and

An 2014 article from researchers of ReRAM concluded

that Strukovs (HPs) initial/basic memristor modelling
equations do not reect the actual device physics well,
whereas subsequent (physics-based) models such as Picketts model or Menzels ECM model (Menzel is a coauthor of this paper) have adequate predictability but are
computationally prohibitive. As of 2014, the search continues for a model that balances these issues; the article
identies Changs and Yakopcics models as potentially
good compromises.[25]
Martin Reynolds, an electrical engineering analyst with
research outt Gartner, commented that while HP was
being sloppy in calling their device a memristor, critics
were being pedantic in saying it was not a memristor.[26]

Experimental tests for memristors

Substituting the ux as the time integral of the voltage,

and charge as the time integral of current, the more convenient form is

Chua suggested experimental tests to determine if a device may properly be categorized as a memristor:[27]
M (q(t)) =

dm /dt V (t)
=
dq/dt
I(t)

The Lissajous curve in the voltage-current plane is a

pinched hysteresis loop when driven by any bipolar To relate the memristor to the resistor, capacitor, and inperiodic voltage or current without respect to initial ductor, it is helpful to isolate the term M(q), which charconditions.
acterizes the device, and write it as a dierential equation.
The area of each lobe of the pinched hysteresis loop The above table covers all meaningful ratios of dierenshrinks as the frequency of the forcing signal in- tials of I, Q, , and V. No device can relate dI to dq, or
d to dV, because I is the derivative of Q and is the
creases.
integral of V.
As the frequency tends to innity, the hysteresis
loop degenerates to a straight line through the origin,
whose slope depends on the amplitude and shape of
the forcing signal.

It can be inferred from this that memristance is chargedependent resistance. If M(q(t)) is a constant, then we
obtain Ohms Law R(t) = V(t)/ I(t). If M(q(t)) is nontrivial, however, the equation is not equivalent because q(t)
and M(q(t)) can vary with time. Solving for voltage as a
According to Chua[28][29] all resistive switching memo- function of time produces
ries including ReRAM, MRAM and phase change memory meet these criteria and are memristors. However, the
lack of data for the Lissajous curves over a range of iniV (t) = M (q(t))I(t)
tial conditions or over a range of frequencies, complicates
assessments of this claim.
This equation reveals that memristance denes a linear
Experimental evidence shows that redox-based resistance relationship between current and voltage, as long as M
memory (ReRAM) includes a nanobattery eect that is does not vary with charge. Nonzero current implies time
contrary to Chuas memristor model. This indicates that varying charge. Alternating current, however, may rethe memristor theory needs to be extended or corrected veal the linear dependence in circuit operation by inducto enable accurate ReRAM modeling.[5]
ing a measurable voltage without net charge movement
as long as the maximum change in q does not cause much
change in M.

Theory

Furthermore, the memristor is static if no current is applied. If I(t) = 0, we nd V(t) = 0 and M(t) is constant.
The memristor was originally dened in terms of a non- This is the essence of the memory eect.
linear functional relationship between magnetic ux linkThe power consumption characteristic recalls that of a reage (t) and the amount of electric charge that has
sistor, I 2 R.
owed, q(t):[1]

f(

m (t), q(t))

=0

The magnetic ux linkage", , is generalized from the

circuit characteristic of an inductor. It does not represent
a magnetic eld here. Its physical meaning is discussed
below. The symbol may be regarded as the integral
of voltage over time.[30]
In the relationship between and q, the derivative of
one with respect to the other depends on the value of one
or the other, and so each memristor is characterized by its
memristance function describing the charge-dependent
rate of change of ux with charge.

M (q) =

dm
dq

P (t) = I(t)V (t) = I 2 (t)M (q(t))

As long as M(q(t)) varies little, such as under alternating
current, the memristor will appear as a constant resistor.
If M(q(t)) increases rapidly, however, current and power
consumption will quickly stop.
M(q) is physically restricted to be positive for all values
of q (assuming the device is passive and does not become
superconductive at some q). A negative value would mean
that it would perpetually supply energy when operated
with alternating current.
In 2008 researchers from HP Labs introduced a model for
a memristance function based on thin lms of titanium
dioxide.[3] For RON<<R<sub>OFF the memristance
function was determined to be

)
(
v RON
q(t)
M (q(t)) = ROFF 1
D2

THEORY

access memory relating the theory to active areas of research.

In the more general concept of an n-th order memristive
system the dening equations are

where ROFF represents the high resistance state, RON

represents the low resistance state, represents the mobility of dopants in the thin lm, and D represents the
lm thickness. The HP Labs group noted that window y(t) = g(x, u, t)u(t),
functions were necessary to compensate for dierences
between experimental measurements and their memristor x = f (x, u, t)
model due to nonlinear ionic drift and boundary eects.
where u(t) is an input signal, y(t) is an output signal, the
vector x represents a set of n state variables describing
the device, and g and f are continuous functions. For a
4.1 Operation as a switch
current-controlled memristive system the signal u(t) repFor some memristors, applied current or voltage causes resents the current signal, i(t) and the signal y(t) represents
substantial change in resistance. Such devices may be the voltage signal v(t). For a voltage-controlled memrischaracterized as switches by investigating the time and tive system the signal u(t) represents the voltage signal v(t)
energy that must be spent to achieve a desired change and the signal y(t) represents the current signal i(t).
in resistance. This assumes that the applied voltage re- The pure memristor is a particular case of these equations,
mains constant. Solving for energy dissipation during namely when x depends only on charge (x=q) and since
a single switching event reveals that for a memristor to the charge is related to the current via the time derivative
switch from R to R in time T to T, the charge dq/dt=i(t). Thus for pure memristors f (i.e. the rate of
must change by Q = Q Q.
change of the state) must be equal or proportional to the
current i(t) .
Ton
Qon
Qon
dt
dq
dq
Eswitch = V 2
= V2
= V2
= V Q
V
(q)
Toff M (q(t))
Qoff I(q)M (q)
Q
4.3 offPinched
hysteresis
Substituting V=I(q)M(q), and then dq/V = Q/V for
constant VTo produces the nal expression. This power
characteristic diers fundamentally from that of a metal
oxide semiconductor transistor, which is capacitor-based.
Unlike the transistor, the nal state of the memristor in
terms of charge does not depend on bias voltage.
The type of memristor described by Williams ceases
to be ideal after switching over its entire resistance
range, creating hysteresis, also called the hard-switching
regime.[3] Another kind of switch would have a cyclic
M(q) so that each o-on event would be followed by an
on-o event under constant bias. Such a device would
act as a memristor under all conditions, but would be less
practical.
Example of pinched hysteresis curve, V versus I

4.2

Memristive systems

The memristor was generalized to memristive systems in

Chuas 1976 paper.[27] Whereas a memristor has mathematically scalar state, a system has vector state. The
number of state variables is independent of the number
of terminals.
Chua applied this model to empirically-observed phenomena, including the HodgkinHuxley model of the
axon and a thermistor at constant ambient temperature.
He also described memristive systems in terms of energy storage and easily observed electrical characteristics. These characteristics might match resistive random-

One of the resulting properties of memristors and memristive systems is the existence of a pinched hysteresis
eect.[31] For a current-controlled memristive system, the
input u(t) is the current i(t), the output y(t) is the voltage
v(t), and the slope of the curve represents the electrical
resistance. The change in slope of the pinched hysteresis curves demonstrates switching between dierent resistance states which is a phenomenon central to ReRAM
and other forms of two-terminal resistance memory. At
high frequencies, memristive theory predicts the pinched
hysteresis eect will degenerate, resulting in a straight
line representative of a linear resistor. It has been proven
that some types of non-crossing pinched hysteresis curves
(denoted Type-II) cannot be described by memristors.[32]

5.2

4.4

Polymeric memristor

Extended memristive systems

Some researchers have raised the question of the scientic

legitimacy of HPs memristor models in explaining the
behavior of ReRAM.[17][18] and have suggested extended
memristive models to remedy perceived deciencies.[5]

5
an electric eld is applied, the oxygen vacancies drift
(see Fast ion conductor), changing the boundary between
the high-resistance and low-resistance layers. Thus the
resistance of the lm as a whole is dependent on how
much charge has been passed through it in a particular direction, which is reversible by changing the direction of
current.[3] Since the HP device displays fast ion conduction at nanoscale, it is considered a nanoionic device.[38]

One example[33] attempts to extend the memristive systems framework by including dynamic systems incorporating higher-order derivatives of the input signal u(t) as Memristance is displayed only when both the doped layer
a series expansion
and depleted layer contribute to resistance. When enough
charge has passed through the memristor that the ions can
no longer move, the device enters hysteresis. It ceases to
integrate
q=Idt,
but rather keeps q at an upper bound and
d2 u
d4 u
d2m
u
y(t) = g0 (x, u)u(t)+g1 (x, u) 2 +g2 (x, u) 4 +...+gmM
(x,xed,
u) thus
,acting as a constant resistor until current is
2m
dt
dt
dt
reversed.
x = f (x, u)
Memory applications of thin-lm oxides had been an area
where m is a positive integer, u(t) is an input signal, y(t) of active investigation for some time. IBM published an
is an output signal, the vector x represents a set of n state article in 2000 regarding structures similar to that devariables describing the device, and the functions g and scribed by Williams.[39] Samsung has a U.S. patent for
f are continuous functions. This equation produces the oxide-vacancy based switches similar to that described by
same zero-crossing hysteresis curves as memristive sys- Williams.[40] Williams also has a U.S. patent application
tems but with a dierent frequency response than that related to the memristor construction.[41]
predicted by memristive systems.
In April 2010, HP labs announced that they had practical
Another example suggests including an oset value a to memristors working at 1 ns (~1 GHz) switching times and
account for an observed nanobattery eect which violates 3 nm by 3 nm sizes,[42] which bodes well for the future of
the predicted zero-crossing pinched hysteresis eect.[5]
the technology.[43] At these densities it could easily rival
the current sub-25 nm ash memory technology.
y(t) = g0 (x, u)(u(t) a),
x = f (x, u)

5
5.1

Implementations
Titanium dioxide memristor

5.2 Polymeric memristor

In 2004, Krieger and Spitzer described dynamic doping
of polymer and inorganic dielectric-like materials that
improved the switching characteristics and retention required to create functioning nonvolatile memory cells.[44]
They used a passive layer between electrode and active
thin lms, which enhanced the extraction of ions from
the electrode. It is possible to use fast ion conductor as
this passive layer, which allows a signicant reduction of
the ionic extraction eld.

Interest in the memristor revived when an experimental

solid state version was reported by R. Stanley Williams
of Hewlett Packard in 2007.[34][35][36] The article was the
rst to demonstrate that a solid-state device could have
the characteristics of a memristor based on the behavior
of nanoscale thin lms. The device neither uses magnetic
ux as the theoretical memristor suggested, nor stores
charge as a capacitor does, but instead achieves a resis- In July 2008, Erokhin and Fontana claimed to have detance dependent on the history of current.
veloped a polymeric memristor before the more recently
Although not cited in HPs initial reports on their TiO2 announced titanium dioxide memristor.[45]
memristor, the resistance switching characteristics of ti- In 2012, Crupi, Pradhan and Tozer described a proof of
tanium dioxide were originally described in the 1960s.[37] concept design to create neural synaptic memory circuits
The HP device is composed of a thin (50 nm) titanium
dioxide lm between two 5 nm thick electrodes, one
titanium, the other platinum. Initially, there are two layers to the titanium dioxide lm, one of which has a slight
depletion of oxygen atoms. The oxygen vacancies act
as charge carriers, meaning that the depleted layer has a
much lower resistance than the non-depleted layer. When

using organic ion-based memristors.[46] The synapse circuit demonstrated long-term potentiation for learning as
well as inactivity based forgetting. Using a grid of circuits, a pattern of light was stored and later recalled. This
mimics the behavior of the V1 neurons in the primary visual cortex that act as spatiotemporal lters that process
visual signals such as edges and moving lines.

5.3

6 APPLICATIONS

Layered memristor

In 2014, Bessonov et al. reported a exible memristive

device comprising a MoO/MoS2 heterostructure sandwiched between silver electrodes on a plastic foil.[47]
The fabrication method is entirely based on printing and
solution-processing technologies using two-dimensional
layered transition metal dichalcogenides (TMDs). The
memristors are mechanically exible, optically transparent and produced at low cost. The memristive behaviour
of switches was found to be accompanied by a prominent memcapacitive eect. High switching performance,
demonstrated synaptic plasticity and sustainability to mechanical deformations promise to emulate the appealing
characteristics of biological neural systems in novel computing technologies.

5.4

Ferroelectric memristor

The ferroelectric memristor[48] is based on a thin ferroelectric barrier sandwiched between two metallic electrodes. Switching the polarization of the ferroelectric
material by applying a positive or negative voltage across
the junction can lead to a two order of magnitude resistance variation: ROFF RON (an eect called Tunnel
Electro-Resistance). In general, the polarization does not
switch abruptly. The reversal occurs gradually through
the nucleation and growth of ferroelectric domains with
opposite polarization. During this process, the resistance
is neither RON or ROFF, but in between. When the
voltage is cycled, the ferroelectric domain conguration
evolves, allowing a ne tuning of the resistance value.
The ferroelectric memristors main advantages are that
ferroelectric domain dynamics can be tuned, oering a
way to engineer the memristor response, and that the resistance variations are due to purely electronic phenomena, aiding device reliability, as no deep change to the
material structure is involved.

5.5
5.5.1

Spin memristive systems

Spintronic memristor

Chen and Wang, researchers at disk-drive manufacturer

Seagate Technology described three examples of possible
magnetic memristors.[49] In one device resistance occurs
when the spin of electrons in one section of the device
points in a dierent direction from those in another section, creating a domain wall, a boundary between the
two sections. Electrons owing into the device have a
certain spin, which alters the devices magnetization state.
Changing the magnetization, in turn, moves the domain
wall and changes the resistance. The works signicance
led to an interview by IEEE Spectrum.[50] A rst experimental proof of the spintronic memristor based on domain wall motion by spin currents in a magnetic tunnel
junction was given in 2011.[51]

5.5.2 Spin-transfer torque magnetoresistance

Spin-transfer torque MRAM is a well-known device that
exhibits memristive behavior. The resistance is dependent on the magnetic state of a magnetic tunnel junction,
i.e., on the relative magnetization alignment of the two
electrodes. This can be controlled by spin torque induced
by current owing through the junction. However, the
length of time the current ows through the junction determines the amount of current needed, i.e., charge is the
key variable.[52]
Additionally, Krzysteczko et al.,[53] reported that MgObased magnetic tunnel junctions show memristive behavior based on the drift of oxygen vacancies within the insulating MgO layer (resistive switching). Therefore, the
combination of spin-transfer torque and resistive switching leads naturally to a second-order memristive system
described by the state vector x = (x1 ,x2 ), where x1 describes the magnetic state of the electrodes and x2 denotes the resistive state of the MgO barrier. In this case
the change of x1 is current-controlled (spin torque is due
to a high current density) whereas the change of x2 is
voltage-controlled (the drift of oxygen vacancies is due
to high electric elds). The presence of both eects in a
memristive magnetic tunnel junction led to the idea of a
nanoscopic synapse-neuron system.[54]

5.5.3 Spin memristive system

A fundamentally dierent mechanism for memristive behavior has been proposed by Pershin[55] and Di Ventra.[56][57] The authors show that certain types of semiconductor spintronic structures belong to a broad class
of memristive systems as dened by Chua and Kang.[27]
The mechanism of memristive behavior in such structures is based entirely on the electron spin degree of freedom which allows for a more convenient control than the
ionic transport in nanostructures. When an external control parameter (such as voltage) is changed, the adjustment of electron spin polarization is delayed because of
the diusion and relaxation processes causing hysteresis.
This result was anticipated in the study of spin extraction
at semiconductor/ferromagnet interfaces,[58] but was not
described in terms of memristive behavior. On a short
time scale, these structures behave almost as an ideal
memristor.[1] This result broadens the possible range of
applications of semiconductor spintronics and makes a
step forward in future practical applications.

6 Applications
Williams solid-state memristors can be combined into
devices called crossbar latches, which could replace transistors in future computers, given their much higher circuit density.

7
They can potentially be fashioned into non-volatile solidstate memory, which would allow greater data density
than hard drives with access times similar to DRAM,
replacing both components.[13] HP prototyped a crossbar latch memory that can t 100 gigabits in a square
centimeter,[7] and proposed a scalable 3D design (consisting of up to 1000 layers or 1 petabit per cm3 ).[59] In
May 2008 HP reported that its device reaches currently
about one-tenth the speed of DRAM.[60] The devices resistance would be read with alternating current so that
the stored value would not be aected.[61] In May 2012
it was reported that access time had been improved to
90 nanoseconds if not faster, approximately one hundred
times faster than contemporaneous ash memory, while
using one percent as much energy.[62]
Memristor patents include applications in programmable
logic,[63] signal processing,[64] neural networks,[65]
control systems,[66] recongurable computing,[67]
brain-computer interfaces[68] and RFID.[69] Memristive
devices are potentially used for stateful logic implication, allowing a replacement for CMOS-based logic
computation. Several early works in this direction are
reported.[70] [71]
In 2009, a simple electronic circuit[72] consisting of an LC
network and a memristor was used to model experiments
on adaptive behavior of unicellular organisms.[73] It was
shown that subjected to a train of periodic pulses, the circuit learns and anticipates the next pulse similar to the
behavior of slime molds Physarum polycephalum where
the viscosity of channels in the cytoplasm responds to periodic environment changes.[73] Applications of such circuits may include, e.g., pattern recognition. The DARPA
SyNAPSE project funded HP Labs, in collaboration with
the Boston University Neuromorphics Lab, has been developing neuromorphic architectures which may be based
on memristive systems. In 2010, Versace and Chandler described the MoNETA (Modular Neural Exploring Traveling Agent) model.[74] MoNETA is the rst
large-scale neural network model to implement wholebrain circuits to power a virtual and robotic agent using
memristive hardware.[75] Application of the memristor
crossbar structure in the construction of an analog soft
computing system was demonstrated by Merrikh-Bayat
and Shouraki.[76] In 2011 they showed[77] how memristor crossbars can be combined with fuzzy logic to create an analog memristive neuro-fuzzy computing system
with fuzzy input and output terminals. Learning is based
on the creation of fuzzy relations inspired from Hebbian
learning rule.

7 Memcapacitors and meminductors

In 2009, Di Ventra, Pershin and Chua extended[79] the
notion of memristive systems to capacitive and inductive
elements in the form of memcapacitors and meminductors, whose properties depend on the state and history of
the system, further extended in 2013 by Di Ventra and
Pershin.[22]

8 Memfractance and memfractor,

2nd and 3rd order memristor,
memcapacitor and meminductor
In September 2014, Mohamed-Salah Abdelouahab, Rene
Lozi and Leon Chua, published a general theory of 1st,
2nd, 3rd order and nth order memristive element using
fractional derivatives.[80]

9 Timeline
9.1 1808
Sir Humphry Davy is claimed by Leon Chua to have
performed the rst experiments showing the eects of a
memristor.[6][81]

9.2 1960
Bernard Widrow coins the term memistor (i.e. memory
resistor) to describe components of an early articial neural network called ADALINE.

9.3 1968
Argall publishes an article showing the resistance switching eects of TiO2 which was later claimed in 2008 to
be evidence of a memristor by researchers from Hewlett
Packard.[37]

9.4 1971

Leon Chua postulated a new two-terminal circuit element

In 2013 Leon Chua published a tutorial underlining the
characterized by a relationship between charge and ux
broad span of complex phenomena and applications that
linkage as a fourth fundamental circuit element.[1]
memristors span and how they can be used as non-volatile
analog memories and can mimic classic habituation and
learning phenomena.[78]
9.5 1976
Chua and his student Sung Mo Kang generalized the theory of memristors and memristive systems including a

9 TIMELINE

property of zero crossing in the Lissajous curve charac- 9.9 2011

terizing current vs. voltage behavior.[27]
In October Tse demonstrated printed memristive counters based on solution processing, with potential applications as low-cost packaging components (no battery
9.6 2008
needed; powered by energy scavenging mechanism).[92]
On May 1 Strukov, Snider, Stewart and Williams published an article in Nature identifying a link between 9.10 2012
the 2-terminal resistance switching behavior found in
nanoscale systems and memristors.[82]
On March 23 HRL Laboratories and the University
On August 10, Dr. Kris Campbell discloses a new ap- of Michigan announced the rst functioning memrisproach to developing, fabricating, and testing memristors tor array built on a CMOS chip for applications in
neuromorphic computer architectures.[11]
on top of CMOS chips. [83]

9.7

2009

On January 23 Di Ventra, Pershin and Chua extended the

notion of memristive systems to capacitive and inductive
elements, namely capacitors and inductors whose properties depend on the state and history of the system.[79]

On July 5, Italian researchers from Politecnico di Torino,

Alon Ascoli and Fernando Corinto, showed that a purely
passive circuit, employing already-existing components,
can exhibit memristive dynamics.[93] The circuit is composed of an elementary diode bridge and an RLC series
circuit, introducing nonlinearity and dynamical behaviour
into the system, respectively. In his latest classication of
memristive systems, dated September 2013, Prof. L. O.
Chua classied this circuit as an example of a generalized
memristor.

On May 1 Kim, et al. described a newly discovered memristor material based on magnetite nanoparticles and proOn July 31, Meuels and Soni[20] questioned the appliposed an extended memristor model including both timecability of the concept of a solely current-controlled, nondependent resistance and time-dependent capacitance.[84]
volatile memristor to any physically realizable device.
On July 13 Mouttet described a memristor-based pattern recognition circuit performing an analog variation of
the exclusive nor function. The circuit architecture was 9.11 2013
proposed as a way to circumvent Von Neumann architecture#Von Neumann bottleneck for processors used in On February 27 Thomas et al., demonstrated that a memrobotic control systems.[85]
ristor can be used to mimic a synapse more readily than
On August 4 Choi et al. described the physical realization traditional CMOS technology and be used as the founof an electrically modiable array of memristive neural dation for building physical circuits capable of learning.
The approach utilizes memristors as key components in
synapses.[86]
a blueprint for an articial brain.[94]
On April 23 Valov, et al., argued that the current memristive theory must be extended to a whole new theory
9.8 2010
to properly describe redox-based resistively switching elements (ReRAM). The main reason is the existence of
On April 8 Borghetti, et al. described an array of nanobatteries in redox-based resistive switches which vimemristors demonstrated the ability to perform logical olates the memristor theorys requirement for a pinched
operations.[87]
hysteresis.[5]
On April 20 Memristor-based content addressable memory (MCAM) was introduced.[88]

9.12 2014

On June 1 Mouttet argued that the interpretation of the

memristor as a fourth fundamental was incorrect and that On February 10, Nugent and Molter presented a new
the HP Labs device was part of a broader class of mem- form of computing dubbed AHaH Computing, which
ristive systems.[89]
uses dierential pairs of memristors as the storage
On August 31 HP announced they had teamed up medium for synaptic weights. The proposed architecwith Hynix to produce a commercial product dubbed ture provides a solution to the "von Neumann bottleneck"
ReRam.[90]
by merging processor and memory, and future hardware
power consumpOn December 7 So and Koo developed a hydrogel form based on the technology may reduce the
[95]
tion
of
machine
learning
applications.
of memristor that was speculated to be useful to construct
a brain-computer interface.[91]

On November 10, Bessonov et al.

demonstrated a

9
new type of exible memristors comprising solution- [9] HP to replace ash and SSD in 2013, 7 October 2011
processed MoO/MoS2 heterostructures stacked with
[10] HP 100TB Memristor drives by 2018 if you're lucky, adprinted silver electrodes on a plastic foil.[47]
mits tech titan, 1 November 2013

9.13 2015

[11] Articial synapses could lead to advanced computer memory and machines that mimic biological brains, HRL Laboratories, March 23, 2012, retrieved March 30, 2012

On March 21st, Bio Inspired Technologies of Boise,

Idaho introduced the rst commercially available discrete
[12] Bush, S. (2 May 2008), HP nano device implements
memristor. The Bio Inspired memristor is fabricated on
memristor, Electronics Weekly
silicon and based upon the silver-chalcogenide conductive bridge stack design. The device is analog and is pro- [13] Kanellos, M. (30 April 2008), HP makes memory from a
grammed in various erase and program states by the aponce theoretical circuit, CNET News, retrieved 2008-04plication of DC voltages or discrete pulses. The memris30
tor forms the ideal building block for researchers interested in designing and prototyping neuromorphic circuits [14] Mellor, C. (10 October 2011), HP and Hynix to produce
the memristor goods by 2013, The Register, retrieved
and advanced memory architectures.
2012-03-07

10

See also

Memistor
Electrical element
List of emerging technologies
Physical neural network
RRAM

11

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12

Further reading

Ronald Tetzla, ed. (2013). Memristors and Memristive Systems. Springer. ISBN 978-1-4614-90685.
Andrew Adamatzky and Leon Chua, ed. (2013).
Memristor Networks. Springer. ISBN 978-3-31902630-5.
Keith Atkin (2013), An introduction to the memristor, Phys. Educ. 48 317 doi:10.1088/00319120/48/3/317. One of the relatively simple experiments described in this paper has been reproduced
by Chris Winstead.
Muthuswamy,
B
et
al.,
"Memristor
Modelling",
IEEE
ISCAS
2014,
doi:10.1109/ISCAS.2014.6865179;
see also
accompanying video/

13

External links

Video: Finding the missing memristor | Stanford

University (2012)
Interactive database of memristor papers (2013)
The Bio Inspired Technologies Memristor (2015)

EXTERNAL LINKS

13

14
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Memristor Source: http://en.wikipedia.org/wiki/Memristor?oldid=654655499 Contributors: The Anome, David spector, Heron, Tessonec,
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