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High Reliability Series Eeproms I C Bus: BR24L - W Series
High Reliability Series Eeproms I C Bus: BR24L - W Series
No.09001EDT04
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides
a failsafe method of data reliability, while a double reset function prevents data miswriting. In addition, gold pads and gold
wires are used for internal connections, pushing the boundaries of reliability to the limit.
BR24L-W Series assort 1Kbit64Kbit. BR24S-W Series are possible to operate at high speed in low voltage
and assort 8Kbit256Kbit.
Contents
BR24L-W Series
BR24L01A-W, BR24L02-W, BR24L04-W, BR24L08-W,
BR24L16-W, BR24L32-W, BR24L64-W
P2
BR24S-W Series
BR24S08-W, BR24S16-W, BR24S32-W, BR24S64-W,
BR24S128-W, BR24S256-W
P20
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1/40
2009.09 - Rev.D
Technical Note
Page write
Number of
Pages
Product
number
8Byte
16Byte
32Byte
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
BR24L series
Capacity
Bit
format
Type
Power source
Voltage
SOP8
SOP-J8
1Kbit
1288
BR24L01A-W
1.85.5V
2Kbit
2568
BR24L02-W
1.75.5V
4Kbit
5128
BR24L04-W
1.85.5V
MSOP8
TSSOP-B8J
VSON008
X2030
SSOP-B8 TSSOP-B8
8Kbit
1K8
BR24L08-W
1.85.5V
16Kbit
2K8
BR24L16-W
1.75.5V
32Kbit
4K8
BR24L32-W
1.75.5V
64Kbit
8K8
BR24L64-W
1.85.5V
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2009.09 - Rev.D
Technical Note
symbol
VCC
Permissible dissipation
Limits
-0.3+6.5
*1
450 (SOP8)
450 (SOP-J8) *2
300 (SSOP-B8) *3
330 (TSSOP-B8) *4
310 (MSOP8) *5
310 (TSSOP-B8J) *6
300 (VSON008X2030) *7
-65+125
-40+85
-0.3Vcc+1.0
Pd
Tstg
Topr
-
Unit
V
mW
Max.
-
Unit
Times
Years
Symbol
Vcc
VIN
Limits
1.85.5 *1
0Vcc
Unit
V
*1 BR24L02/16/32-W : 1.7~5.5V
VIH1
VIL1
0.7Vcc
-0.3
*2
Vcc +1.0 *2
2.5Vcc5.5V
0.3 Vcc
2.5Vcc5.5V
*2
VIH2
0.8Vcc
Vcc +1.0
1.8Vcc2.5V
VIL2
-0.3 *2
0.2 Vcc
1.8Vcc2.5V
*3
VIH3
0.8Vcc
Vcc +1.0
1.7Vcc1.8V
*4
Conditions
VIH3
0.9Vcc
Vcc +1.0
1.7Vcc1.8V
VIL3
-0.3
0.1 Vcc
1.7Vcc1.8V
VOL1
0.4
VOL2
0.2
ILI
-1
VIN=0VVcc
ILO
-1
VOUT=0VVcc, (SDA)
mA
Vcc=5.5V,fSCL=400kHz, tWR=5ms,
Byte write, Page write
Current consumption at
action
Standby current
1
2.0
*5
ICC1
ICC2
0.5
mA
ISB
2.0
3.0 *6
Vcc=5.5V,fSCL=400kHz
Random read, current read,sequential read
Vcc=5.5V, SDASCL=Vcc
A0, A1, A2=GND, WP=GND
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2009.09 - Rev.D
Technical Note
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
SCL frequency
fSCL
400
100
tHIGH
0.6
4.0
tLOW
1.2
4.7
tR
0.3
1.0
*2
kHz
tF
0.3
0.3
tHD:STA
0.6
4.0
tSU:STA
0.6
4.7
tHD:DAT
ns
tSU:DAT
100
250
ns
tPD
0.1
0.9
0.2
3.5
tDH
0.1
0.2
tSU:STO
0.6
4.7
tBUF
1.2
4.7
tWR
ms
tI
0.1
0.1
WP hold time
tHD:WP
ns
WP setup time
tSU:WP
tHIGH:W
P
0.1
0.1
1.0
--
1.0
WP valid time
*1 BR24L02/16/32-W : 1.75.5V
*2 Not 100% tested
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2009.09 - Rev.D
Technical Note
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tSU:STA
SDA
()
(input)
tHD:STA
tSU:STO
SDA
tPD
tBUF
tDH
SDA
START BIT
()
(output)
STOP BIT
SCL
DATA(1)
SCL
SDA
SDA
D0
D1
D0
W R
(n-th address)
ACK
WR
ACK
Write data
DATA(n)
ACK
Stop condition
Stop condition
WP
Start condition
HDWP
tSUWP
SCL
DATA(n)
DATA(1)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
WP
At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=LOW.
By setting WP HIGH in the area, write can be cancelled.
When it is set WP=HIGH during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
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2009.09 - Rev.D
Technical Note
*2
A0
Vcc
WP
SCL
SDA
*1
7bit 11bit
8bit 12bit
9bit 13bit
10bit
*2
*2
A1
A2
8bit
Address
decoder
*1
7bit 11bit
8bit 12bit
9bit 13bit
10bit
Data
register
Slave - word
address register
START
STOP
Control circuit
ACK
GND
High voltage
generating circuit
Power source
voltage detection
A0=N.C.
A0, A1=N.C.
A0, A1= N.C. A2=Dont Use
: BR24L04-W
: BR24L08-W
: BR24L16-W
A0
Terminal
name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input /
output
Input
Input
Input
Input /
output
Input
Input
-
A1
A2
GND
1
1
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
BR24L32-W
BR24L64-W
Vcc
WP
SCL
SDA
1
1
1
1
Function
BR24L01A-W
BR24L02-W
BR24L04-W
BR24L08-W
BR24L16-W
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BR24L32-W
BR24L64-W
Slave and word address, Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
6/40
2009.09 - Rev.D
Technical Note
4
SPEC
3
2
Ta=85
Ta=-40
Ta=25
1
0.8
Ta=85
Ta=-40
Ta=25
VOL1[V]
VIL1,2[V]
VIH1,2[V]
SPEC
3
4
5
Vcc[V]
Fig.3 H input voltage VIH1,2
Ta=25
SPEC
Ta=-40
0
0
3
4
5
6
IOL1[mA]
Fig.5 L output voltageVOL1-IOL1(VCC=2.5V)
3
4
5
6
Vcc[V]
Fig.4 L input voltageVIL1,2(SCL,SDA,WP)
1.2
0.8
0.8
0.8
0.4
SPEC
SPEC
ILO[A]
ILI[A]
VOL2[V]
Ta=25
Ta=85
0.6
0.4
0.2
0
0
3
4
IOL2[mA]
3
Vcc[V]
3
SPEC
fSCL=400kHz
DATA=AAh
2
1.5
3
4
5
6
Vcc[V]
Fig.9 Current consumption at WRITE action ICC1
(fscl=400kHz)
0.1
3
Vcc[V]
1
2
3
4
5
6
Vcc[V]
Fig.11 Current consumption at READ action ICC2
(fSCL=400kHz)
3.5
0.6
[BR24L32/64 series]
[BR24L01/02/04/08/16 series]
SPEC
3
fSCL=100kHz
DATA=AAh
SPEC
fSCL=100kHz
DATA=AAh
2.5
ICC1[mA]
1.5
1
Ta=25
Ta=85
Ta=-40
0.5
0.5
SPEC
ICC2[mA]
2
1.5
1
0.4
0.3
3
Vcc[V]
2.5
Ta=85
0.2
0.1
Ta=-40
0
0
3
Vcc[V]
1
2
3
4
5
6
Vcc[V]
Fig.14 Current consumption at READ action ICC2
(fSCL=100kHz)
fSCL=100kHz
DATA=AAh
Ta=25
Ta=25
Ta=85
Ta=-40
0.5
0
0
Ta=-40
2.5
Ta=25
0.2
0
0
10000
SPEC2
SPEC
1.5
1
100
Ta=-40
3
Vcc[V]
SPEC2
SPEC2
SPEC1
3
2
Ta=85
Ta=25
Ta=-40
SPEC1
3
4
5
Vcc[V]
Fig.18 Data clock "L" time tLOW
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3
Vcc[V]
4
3
2
Ta=-40
Ta=25
Ta=85
SPEC2
5
tSU:STA[s]
tHD:STA[s]
SPEC1
SPEC2
4
tLOW[s]
3
Vcc[V]
Ta=85
Ta=25
Ta=-40
Ta=-40
Ta=25
Ta=85
Ta=25
0
1
SPEC1
10
Ta=85
Ta=85
Ta=25
Ta=-40
tHIGH [s]
1000
fSCL[kHz]
ISB[A]
0.5
Ta=85
0.3
fSCL=400kHz
DATA=AAh
0.4
Ta=25
Ta=85
Ta=-40
0.5
SPEC
0.5
SPEC
Ta=25
Ta=85
Ta=-40
3
Vcc[V]
ICC2[mA]
ICC1[mA]
2.5
1.5
0.5
[BR24L32/64 series]
[BR24L01/02/04/08/16 series]
fSCL=400kHz
DATA=AAh
0.6
3.5
Ta=85
Ta=25
Ta=-40
0.2
0
ICC1[mA]
0.4
2.5
ICC1[mA]
0.6
Ta=85
Ta=25
Ta=-40
0.2
Ta=-40
1.2
SPEC
0.6
Ta=85
0.4
0.2
0.6
SPEC1
0
0
3
Vcc[V]
7/40
3
Vcc[V]
2009.09 - Rev.D
Technical Note
50
50
SPEC1,2
-50
-100
-50
Ta=85
Ta=25
-100
-150
-150
-200
1
3
Vcc[V]
SPEC1
100
0
-200
0
3
4
5
6
Vcc[V]
Fig.22 Input data hold timetHD:DAT(LOW)
Ta=85
Ta=25
Ta=-40
SPEC1
Ta=-40
-100
Ta=-40
Ta=25
Ta=85
Vcc[V]
3
Vcc[V]
3
Vcc[V]
SPEC1,2
SPEC2
0.5
Ta=25
2
Ta=-40
Ta=25
Ta=85
Ta=-40
tI(SCL H)[s]
tWR[ms]
tBUF[s]
Ta=85
SPEC1
3
Vcc[V]
0.3
Ta=85
0.2
SPEC1,2
3
Vcc[V]
0.5
0.5
0.3
Ta=-40
0.2
Ta=25
Ta=25
tI(SDA L)[s]
0.6
0.5
tI(SDA H)[s]
0.6
0.4
Ta=-40
0.3
Ta=85
0.2
0.1
3
Vcc[V]
0.4
Ta=-40
0.3
Ta=25
Ta=85
0.2
SPEC1,2
Ta=85
0.4
Ta=-40
Ta=25
0
0
0.4
0.1
tI(SCL L)[s]
SPEC1
SPEC1
0
0
SPEC2
0
1
SPEC1
SPEC2
Ta=25
-200
3
Vcc[V]
SPEC2
3
tPD1[s]
tPD0[s]
Ta=85
SPEC2
100
SPEC2
SPEC1
200
Ta=85
Ta=25
Ta=-40
-100
Ta=-40
-200
0
tSU:DAT(LOW)[ns]
tSU:DAT(HIGH)[ns]
Ta=-40
Ta=25
Ta=85
SPEC2
200
0
tHD:DAT(LOW)[ns]
tHD:DAT(HIGH)[ns]
SPEC1,2
SPEC1
0.1
0.1
SPEC1
0
0
3
Vcc[V]
0
0
3
Vcc[V]
3
4
5
6
Vcc[V]
Fig.32 Noise removal valid time tI(SDA L)
1.2
0.2
SPEC1,2
SPEC1,2
tHIGH:WP[s]
tSU:WP[s]
-0.2
Ta=85
-0.4
Ta=25
0.8
0.6
0.4
Ta=-40
Ta=25
Ta=85
0.2
Ta=-40
-0.6
0
0
3
Vcc[V]
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3
Vcc[V]
8/40
2009.09 - Rev.D
Technical Note
1-7
SCL
S
START ADDRESS
condition
R/W
ACK
1-7
DATA
ACK
1-7
DATA
ACK
P
STOP
condition
Maximum number of
connected buses
Slave address
1 0 1
A2 A1 A0
R/W
1 0 1
A2 A1 A0
R/W
1 0 1
A2 A1 PS
R/W
1 0 1
A2 P1 P0
R/W
1 0 1
P2 P1 P0
R/W
1 0 1
A2 A1 A0
R/W
1 0 1
A2 A1 A0
R/W
8
8
4
2
1
8
8
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2009.09 - Rev.D
Technical Note
Write Command
Write cycle
Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24L32 / L64-W)
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
S
T
O
P
DATA
SDA
LINE
WA
7
1 0 1 0 A2 A1 A0
Note)
WA
0
D7
D0
A
C
K
R A *1
/ C
W K
A
C
K
SLAVE
ADDRESS
SDA
LINE
W
R
I
T
E
1 0 1 0 A2 A1 A0
Note)
2nd WORD
ADDRESS
1st WORD
ADDRESS
WAWA
12 11
R A
/ C
W K
WA
0
D0
D7
A
C
K
A
C
K
*1
S
T
O
P
DATA
A
C
K
W
R
I
T
E
SLAVE
ADDRESS
W ORD
A D D R E S S (n )
WA
7
1 0 1 0 A 2A 1A 0
WA
0
R A
/ C *1
W K
N o te )
D A TA (n )
D A TA (n +1 5 )
D7
D0
A
C
K
S
T
O
P
*2
D0
A
C
K
A
C
K
SLAVE
ADDRESS
W
R
I
T
E
2nd W ORD
A D D R E S S (n )
WA WA
1 0 1 0 A 2A 1A 0
N ote )
1 st W O R D
A D D R E S S (n )
R A
/ C
W K
1 2 11
*1
D A T A (n )
WA
0
A
C
K
D7
A
C
K
S
T
O
P
D A TA (n + 3 1 )
D0
D0
A
C
K
A
C
K
1 0 1 0 A 2A 1A 0
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2009.09 - Rev.D
Technical Note
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
*1
WA
7
1 0 1 0 A2A1A0
Note)
WORD
ADDRESS
WA
0
R A
/ C
W K
*2
DATA(n)
D7
DATA(n+7)*3
D0
A
C
K
S
T
A
R
T
S
T
O
P
D0
A
C
K
1 0 1 0
A
C
K
Next command
tWR(maximum : 5ms)
Command is not accepted for this period.
1 0 1 0 A 2A 1A 0
*1 In BR24L16-W, A2 becomes P2.
*2 In BR24L08-W, BR24L16-W, A1 becomes P1.
*3 In BR24L04-W, A0 becomes PS, and in BR24L08-W and in BR24L16-W, A0 becomes P0.
8Byte
Product
number
BR24L01A-W
BR24L02-W
16Byte
BR24L04-W
BR24L08-W
BR24L16-W
32Byte
BR24L32-W
BR24L64-W
In the case BR24L02-W, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write.
It does not stand 5ms at maximum 8byte=40ms(Max.).
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11/40
2009.09 - Rev.D
Technical Note
WA4
0
0
0
-------------
0
0
0
WA1
0
0
1
WA0
0
1
0
Increment
---------
0
0
0
WA2
0
0
0
---------
---------
06h
WA3
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
For example, when it is started from address 06h,therefore, increment is made as below,
06h 07h 00h 01h ---, which please note.
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12/40
2009.09 - Rev.D
Technical Note
Read Command
Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used
when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address
data can be read in succession.
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
SDA
L IN E
S
T
A
R
T
W ORD
A D D R E S S (n )
WA
7
1 0 1 0 A 2 A 1A 0
WA
0
R A *1
/ C
W K
N o te )
R
E
A
D
SLAVE
ADDRESS
D A TA (n )
1 0 1 0 A 2 A 1A 0
A
C
K
S
T
O
P
D0
D7
A
C
K
R A
/ C
W K
SLAVE
ADDRESS
W
R
I
T
E
* * *
WA
0
WAWA
12 11
R A
/ C
W K
Note)
2nd WORD
ADDRESS
1st WORD
ADDRESS
1 0 1 0 A2A1A0
S
T
A
R
T
A
C
K
*1
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
A
C
K
S
T
O
P
DATA(n)
D7
D0
R A
/ C
W K
A
C
K
R
E
A
D
S LA V E
ADDRESS
S
T
O
P
D A TA (n )
1 0 1 0 A 2 A 1A 0
D7
D0
A
C
K
R A
/ C
W K
N o te)
R
E
A
D
SLAVE
ADDRESS
1 0 1 0 A2 A1A0
Note
D7
S
T
O
P
DATA(n+x)
DATA(n)
D0
R A
/ C
W K
D7
A
C
K
D0
A
C
K
A
C
K
Fig.46 Sequential read cycle (in the case of current read cycle)
In random read cycle, data of designated word address can be read.
When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next
address data can be read in succession.
Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at
SCL signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A 2A 1A 0
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13/40
2009.09 - Rev.D
Technical Note
Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48(a), Fig.48(b), and Fig.48(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Dummy clock14
SCL
Start2
13
Normal command
14
SDA
Normal command
Dummy clock9
Start
SCL
Start
Normal command
SDA
Normal command
Start9
SCL
Normal command
SDA
Normal command
Write command
S
T
O
P
S
T Slave
A
R address
T
S
T Slave
A
R address
T
A
C
K
H
A
C
K
H
tWR
Second write command
S
T Slave
A
R address
T
A
C
K
H
S
T Slave
A
R address
T
A
C Word
K address
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
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14/40
2009.09 - Rev.D
Technical Note
Rise of SDA
SDA
D1
D0
ACK
ACK
D0
Enlarged view
SDA
Enlarged view
SDA
S
T Slave
A address
R
T
A
C Word
K address
L
A
C D7 D6 D5 D4 D3 D2 D1 D0
K
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
WP
SCL
SDA
Start condition
Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
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15/40
2009.09 - Rev.D
Technical Note
BR24LXX
RPU
0.8Vcc-VIH
IL
RPU
SDA terminal
A
IL
0.83-0.73
1010-6
IL
Bus line
capacity
CBUS
300 [k]
RPU
VC-VOL
IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
VOLMAX VIL-0.1 VCC
Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC
from (1)
3-0.4
RPU
310 -3
867 []
And
VOL = 0.4 [V]
VIL = 0.33
= 0.9 [V]
Therefore, the condition (2) is satisfied.
Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in
consideration of drive performance of output port of microcontroller.
A0, A1, A2, WP process
Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And,
pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with N.C.PIN
BR24L16/F/FJ/FV/FVT/FVM/FVJ-W
A0, A1, A2
BR24L08/F/FJ/FV/FVT/FVM/FVJ/NUX-W
A0, A1
BR24L04/F/FJ/FV/FVT/FVM/FVJ/NUX-W
A0
Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect
it to pull down or GND.
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16/40
2009.09 - Rev.D
Technical Note
SCL
RPU
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
EEPROM
Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
(2)The bus electric potential
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC
(VCCVOL)RS
RPU+RS
RPU A
RS
VOL
1.1VCCVIL
IOL
from(2),
0.330.40.13
1.130.33
RS
EEPROM
Microcontroller
RPU
Bus line
capacity CBUS
VIL
VOL+0.1VCCVIL
VILVOL0.1VCC
RS
20103
1.67k
Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
RPU
'L' output
RS
Over current
VCC
RS
RS
VCC
I
'H' output
RS
Microcontroller
EEPROM
3
-3
1010
300
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17/40
2009.09 - Rev.D
Technical Note
Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Vbot
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
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18/40
2009.09 - Rev.D
Technical Note
VCC
tLOW
SCL
SDA
After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
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2009.09 - Rev.D
Technical Note
16Byte
32Byte
64Byte
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
BR24S series
Capacity
Bit
format
Type
Power source
voltage
SOP8
SOP-J8
8Kbit
1K8
BR24S08-W
16Kbit
1.75.5V
2K8
BR24S16-W
1.75.5V
32Kbit
4K8
BR24S32-W
1.75.5V
64Kbit
8K8
BR24S64-W
1.75.5V
128Kbit
16K8
BR24S128-W
1.75.5V
256Kbit
32K8
BR24S256-W
1.75.5V
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20/40
MSOP8
TSSOP-B8J
VSON008
X2030
SSOP-B8 TSSOP-B8
2009.09 - Rev.D
Technical Note
symbol
Impressed voltage
VCC
Limits
Unit
-0.3+6.5
450 (SOP8) *1
450 (SOP-J8) *2
300 (SSOP-B8) *3
Permissible dissipation
330 (TSSOP-B8) *4
Pd
310 (MSOP8)
mW
*5
310 (TSSOP-B8J) *6
300 (VSON008X2030) *7
Storage temperature range
Tstg
-65+125
Topr
-40+85
-0.3Vcc+1.0
Terminal voltage
Parameter
Number of data rewrite times *1
Data hold years
Unit
Min.
Typ.
Max.
1,000,000
Times
40
Years
*1
Symbol
Limits
Vcc
1.75.5
Input voltage
VIN
0Vcc
Electrical characteristics
(Unless otherwise specified, T=-40+85, Vcc=1.75.5V)
Limits
Parameter
Symbol
Min
Typ.
Max.
Unit
Unit
V
Condition
VIH1
0.7Vcc
Vcc+1.0
VIL1
-0.3
0.3Vcc
VOL1
0.4
VOL2
0.2
ILI
-1
VIN=0Vcc
ILO
-1
VOUT=0Vcc (SDA)
2.0
2.5
ICC2
0.5
mA
ISB
2.0
Current consumption
at action
Standby Current
ICC1
mA
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2009.09 - Rev.D
Technical Note
Symbol
Limits
Min.
Typ.
Max.
Unit
SCL Frequency
fSCL
400
kHz
tHIGH
0.6
tLOW
1.2
tR
0.3
*1
tF
0.3
tHD:STA
0.6
tSU:STA
0.6
tHD:DAT
ns
tSU:DAT
100
ns
tPD
0.1
0.9
tDH
0.1
tSU:STO
0.6
tBUF
1.2
tWR
ms
*1
tI
0.1
WP hold time
tHD:WP
ns
WP setup time
tSU:WP
0.1
WP valid time
tHIGH:WP
1.0
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2009.09 - Rev.D
Technical Note
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tSU:STA
tHD:STA
tSU:STO
SDA
()
(Input)
SDA
tPD
tBUF
tDH
SDA
()
(Output)
START BIT
STOP BIT
SCL
SCL
DATA(1)
SDA
D0
ACK
WRITE DATA(n)
SDA
tWR
STOP
CONDITION
D1
DATA(n)
D0
ACK
ACK
WR
START
CONDITION
Stop
condition
WP
HDWP
tSUWP
SCL
DATA(n)
DATA(1)
SDA
D1
D0
ACK
ACK
tHIGH:WP
tWR
tWR
WP
At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP= 'LOW'.
By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data
of address under access is not guaranteed, therefore write it once again.
A0
8Kbit256Kbit
EEPROM array
Vcc
WP
SCL
SDA
*1
10bit
11bi t
12bit
13bit
14bit
15bit
*2
A1
A2
Adddress
decoder
8bit
*1
10bit
11bit
12bit
13bit
14bit
15bit
START
*2
Data
register
Slave - word
address register
STOP
Control circuit
ACK
GND
High voltage
generating circuit
10bit: BR24S08-W
11bit: BR24S16-W
12bit: BR24S32-W
13bit: BR24S64-W
14bit: BR24S128-W
15bit: BR24S256-W
Power source
voltage detection
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2009.09 - Rev.D
Technical Note
A1
A2
GND
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
Vcc
WP
SCL
SDA
Function
Terminal
name
Input/
Output
BR24S08-W
BR24S16-W
BR24S32/64/128/256-W
A0
Input
Don't use
Don't use
A1
Input
Don't use
Don't use
A2
Input
Don't use
GND
SDA
Input / Output
SCL
Input
WP
Input
Vcc
5
4
3
SPEC
2
1
1
L OUTPUT VOLTAGE : VOL[V]
Ta=-40
Ta=25
Ta=85
Ta=-40
Ta=25
Ta=85
5
4
3
2
1
SPEC
0
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
SPEC
0.2
0
2
3
4
5
L OUTPUT CURRENT : IOL[mA]
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2
3
4
5
6
7
L OUTPUT CURRENT : IOL[mA]
SPEC
1
0.8
0.6
Ta=-40
Ta=25
Ta=85
0.4
0.2
SPEC
1
0.8
0.6
Ta=-40
Ta=25
Ta=85
0.4
0.2
0
0
1
1.2
OUTPUT LEAK CURRENT : ILO[uA]
0.8
SPEC
0.2
1.2
0.4
0.4
Ta=-40
Ta=25
Ta=85
0.6
0
0
0.6
Ta=-40
Ta=25
Ta=85
0.8
2
3
4
5
SUPPLYVOLTAGE : Vcc[V]
24/40
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
2009.09 - Rev.D
Technical Note
Ta=-40
Ta=25
Ta=85
0.5
2.5
2
Ta=-40
Ta=25
Ta=85
1.5
1
0.5
0.2
0.1
1.5
Ta=-40
Ta=25
Ta=85
1000
SPEC
100
0
0
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
Ta=-40
Ta=25
Ta=85
10
SPEC
4
3
Ta=-40
Ta=25
Ta=85
1
0
0
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
-50
Ta=-40
Ta=25
Ta=85
4
3
Ta=-40
Ta=25
Ta=85
2
1
SPEC
0
-50
Ta=-40
Ta=25
Ta=85
200
SPEC
100
Ta=-40
Ta=25
Ta=85
-200
0
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
Ta=-40
Ta=25
Ta=85
0.2
0
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2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
200
SPEC
100
0
SPEC
2
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
25/40
Ta=-40
Ta=25
Ta=85
-100
-200
0
Ta=-40
Ta=25
Ta=85
300
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
300
-100
0.4
50
SPEC
0.6
-0.2
-200
-200
2
1
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
0.8
SPEC
-150
-100
-150
-100
0.2
SPEC
SPEC
0.4
50
0.6
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
Ta=-40
Ta=25
Ta=85
0.8
0.1
START CONDITION
SET UP TIME : tSU:STA[us]
0.5
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
Ta=-40
Ta=25
Ta=85
0.3
10000
SPEC
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
2.5
0.4
0
0
0.5
CURRENT CONSUMPTION
AT READING : Icc2[mA]
SPEC
CURRENT CONSUMPTION
AT WRITING : Icc1[mA]
1.5
1
SPEC
CURRENT CONSUMPTION
AT WRITING : Icc1[mA]
0.6
3.5
2.5
Ta=-40
Ta=25
Ta=85
SPEC
2
0
0
2009.09 - Rev.D
Technical Note
4
3
2
SPEC
SPEC
5
4
3
2
Ta=-40
Ta=25
Ta=85
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
0.4
0.3
0.2
SPEC
0.1
0
1
0.4
0.3
0.2
SPEC
0.1
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
0.5
0.4
0.3
Ta=-40
Ta=25
Ta=85
0.2
SPEC
0.1
0
0.6
Ta=-40
Ta=25
Ta=85
0.5
0.2
0
0
0.4
NOISE REDUCTION
EFFECTIVE TIME : tl(SAD L)[us]
0.5
Ta=-40
Ta=25
Ta=85
0.6
0.6
Ta=-40
Ta=25
Ta=85
NOISE REDUCTION
EFECTIVE TIME : tl(SDA H)[us]
NOISE REDUCTION
EFECTIVE TIME : tl(SCL L)[us]
0.6
SPEC
0.8
1.2
WP EFFECTIVE TIME : tHIGH : WP[us]
0.2
WP SET UP TIME : tSU : WP[us]
NOISE REDUCTION
EFECTIVE TIME : tl(SCL H) [us]
Ta=-40
Ta=25
Ta=85
INTERNAL WRITING
CYCLE TIME : tWR[ms]
SPEC
0.1
0
-0.1
Ta=-40
Ta=25
Ta=85
-0.2
-0.3
-0.4
-0.5
-0.6
SPEC
1
0.8
0.6
0.4
Ta=-40
Ta=25
Ta=85
0.2
0
2
3
4
5
SUPPLY VOLTAGE : Vcc[V]
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3
4
5
SUPPLYVOLTAGE : Vcc[V]
26/40
2009.09 - Rev.D
Technical Note
1-7
SCL
S
START ADDRESS
condition
R/W
ACK
1-7
DATA
1-7
ACK
DATA
ACK
P
STOP
condition
A0
A1
A2
GND
Maximum number of
connected buses
Slave address
BR24S08-W
1 0 1
A2 P1 P0
R/W
BR24S16-W
1 0 1
P2 P1 P0
R/W
BR24S32-W, BR24S64-W
BR24S128-W, BR24S256-W
1 0 1
A2 A1 A0
R/W
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
BR24S128-W
BR24S256-W
Vcc
WP
SCL
SDA
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2009.09 - Rev.D
Technical Note
Write Command
Write cycle
Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity.
Up to 64 arbitrary bytes can be written. (In the case of BR24S128/256-W)
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
WA
7
1 0 1 0 A2 A1 A0
DATA
WA
0
D7
D0
A
C
K
R A
/ C
W K
Note)
S
T
O
P
A
C
K
W
R
I
T
E
SLAVE
ADDRESS
WA WA WAWA
14 13 12 11
1 0 1 0 A2 A1 A0
R A
/ C
W K
Note)
2nd WORD
ADDRESS
1st WORD
ADDRESS
WA
0
*1
D0
D7
A
C
K
A
C
K
*1
S
T
O
P
DATA
A
C
K
W
R
I
T
E
SLAVE
ADDRESS
W ORD
A D D R E S S (n )
WA
7
1 0 1 0 A 2A 1A 0
WA
0
R A
/ C *1
W K
)
Note)
D A T A (n )
D7
D A T A (n + 1 5 )
D0
A
C
K
S
T
O
P
*2
D0
A
C
K
A
C
K
SLAVE
ADDRESS
W
R
I
T
E
R A
/ C
W K
*1
D A T A (n )
WA
0
A
C
K
S
T
O
P
*2
2nd W ORD
A D D R E S S (n )
W A W AW A W A
1 4 13 1 2 11
1 0 1 0 A 2A 1A 0
N o te )
1 st W O R D
A D D R E S S (n )
D7
D A TA (n + 3 1 )
D0
A
C
K
D0
A
C
K
A
C
K
*1
1 0 1 0 A 2A 1A 0
*1
*2
*3
In BR24S16-W, A2 becomes P2
In BR24S08/16-W, A1 becomes P1
In BR24S08/16-W, A0 becomes P0
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2009.09 - Rev.D
Technical Note
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
1 0 1 0 P2 P1 P0
WORD
ADDRESS
DATA(n)
WA
0
WA
7
R A
/ C
W K
note)
DATA(n+15)
D7
D0
A
C
K
Fig.38
S
T
A
R
T
S
T
O
P
D0
A
C
K
1 0 1 0
A
C
K
Next command
tWR(maximum5ms)
Command is not accepted for this
period.
A t S TO P (stop bit)
w rite starts.
SDA
L IN E
S
T
A
R
T
SLAVE
ADDRESS
W
R
I
T
E
1 0 1 0 A 2A 1A 0
note )
1 st W O R D
A D D R E S S (n )
2nd W ORD
A D D R E S S (n )
W A W AW A W A
WA
0
14 13 12 11
R A
/ C
W K
*1
A
C
K
*2
D A TA (n+ 31 )
D A T A (n )
D7
A
C
K
D0
S
T
A
R
T
S
T
O
P
1 0 1 0
D0
A
C
K
A
C
K
*1
N e xt co m m a n d
tW R (ma ximu m : 5 m s)
C o m m an d is n ot a ccep te d for
th is period .
Fig.39
16Byte
32Byte
Product number
BR24S08-W
BR24S16-W
BR24S32-W
BR24S64-W
64Byte
BR24S128-W
BR24S256-W
The above numbers are maximum bytes for respective types. Any bytes below these can be written.
In the case of BR24S256-W, 1 page = 64bytes, but the page write cycle write time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum 64byte = 320ms(Max.).
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2009.09 - Rev.D
Technical Note
WA7 ----0
----0
----0
-----
WA4
0
0
0
WA3
0
0
0
WA2 WA1
0
0
0
0
0
1
---------
---------
0Eh
0
0
0
-------------
WA0
0
1
0
0
0
0
1
1
0
1
1
0
1
1
0
0
1
0
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30/40
2009.09 - Rev.D
Technical Note
Read Command
Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S
T
A
R
T
W
R
I
T
E
SLAVE
ADDRESS
SDA
L IN E
S
T
A
R
T
W ORD
A D D R E S S (n)
WA
7
1 0 1 0 A 2 A 1A 0
WA
0
R A
/ C
W K
N o te)
R
E
A
D
S LA V E
ADDRESS
D A TA (n)
1 0 1 0 A 2 A 1A 0
A
C
K
S
T
O
P
D0
D7
A
C
K
R A
/ C
W K
SLAVE
ADDRESS
SDA
LINE
W
R
I
T
E
1st WORD
ADDRESS
1 0 1 0 A2A1A0
Note)
A
C
K
*1
R
E
A
D
SLAVE
ADDRESS
S
T
O
P
DATA(n)
*1
WA
0
WA WA WAWA
14 13 12 11
R A
/ C
W K
S
T
A
R
T
2nd WORD
ADDRESS
1 0 1 0 A2A1A0
A
C
K
D7
D0
R A
/ C
W K
A
C
K
R
E
A
D
S LA V E
ADDRESS
1 0 1 0 A 2 A 1A 0
D A TA (n )
D7
D0
A
C
K
R A
/ C
W K
N ote )
S
T
O
P
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 A1A0
Note
D7
D0
R A
/ C
W K
S
T
O
P
DATA(n+x)
DATA(n)
D7
A
C
K
D0
A
C
K
A
C
K
Fig.43 Sequential read cycle (in the case of current read cycle)
In random read cycle, data of designated word address can be read.
When the command just before current read cycle is random read cycle, current read cycle (each including sequential read
cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address
data can be read in succession.
Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input
'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
*1 *2 *3
1 0 1 0 A2 A1A0
*1
*2
*3
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31/40
2009.09 - Rev.D
Technical Note
Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.45(a), Fig.45(b), Fig.45(c).) In dummy
clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may
be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
Dummy clock14
SCL
13
Start2
Normal command
14
Normal command
SDA
SCL
Start
Dummy clock9
Normal command
Normal command
SDA
SCL
Normal command
Normal command
SDA
Write command
S
T
O
P
S
T
A
R
T
Slave
address
S
T
A Slave
R address
T
A
C
K
H
A
C
K
H
tWR
Second write command
S
T Slave
A
R address
T
A
C
K
H
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
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32/40
2009.09 - Rev.D
Technical Note
SCL
SCL
Rise of SDA
SDA
D0
D1
SDA
ACK
ACK
D0
Enlarged view
SDA
S
T Slave
A
R address
T
Enlarged view
A
A
C Word C
K address K D7 D6 D5 D4 D3 D2 D1 D0
L
L
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
WP
Data is not written.
SCL
SDA
Start condition
Fig.48 Case of cancel by start, stop condition during slave address input
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33/40
2009.09 - Rev.D
Technical Note
RPU
IL
Ex.) When Vcc = 3V, IL=10A, VIH = 0.7Vcc
from(2)
0.83 - 0.73
RPU
-6
1010
300 k
Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V
and IOLMAX=3mA.
VCC - VOL
IOL
RPU
VCC - VOL
IOL
RPU
Bus line
capacity
CBUS
(2)VOLMAX =0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc.
VOLMAX VIL-0.1 Vcc
Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from(1),
30.4
RPU
310
867
And
VOL=0.4V
VIL=0.33
=0.9V
Therefore, the condition (2) is satisfied.
Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in
consideration of drive performance of output port of microcontroller.
A0, A1, A2, WP process
Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. And,
pins(Don't use PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with Don't use PIN
BR24S08F/FJ/FV/FVT/FVM/FVJ/NUX-W
A0, A1
BR24S16F/FJ/FV/FVT/FVM/FVJ/NUX-W
A0, A1, A2
Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect
it to pull down or GND.
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34/40
2009.09 - Rev.D
Technical Note
SCL
RPU
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontre
EEPROM
Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should
(2)The bus electric potential
sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC
RPU
RS
(VCCVOL)RS
RPU+RS
A
VOL
RS
VILVOL0.1VCC
1.1VCCVIL
IOL
from(2),
RS
EEPROM
Microcontroller
Bus line
capacity CBUS
VIL
VOL+0.1VCCVIL
0.330.40.13
1.130.33
1.67k
RPU
RPU=20k
20103
RPU
RS
VCC
I
'L' output
RS
Over current
RS
'H' output
Microcontroller
VCC
RS
3
1010-3
EEPROM
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2009 ROHM Co., Ltd. All rights reserved.
35/40
2009.09 - Rev.D
Technical Note
tR
VCC
tOFF
tR
tOFF
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
Vbot
VCC
tLOW
SCL
SDA
After Vcc becomes stable
tDH
tSU:DAT
tSU:DAT
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2009.09 - Rev.D
Technical Note
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37/40
2009.09 - Rev.D
Technical Note
Part No.
BUS type
Operating
temperature/
Power source
voltage
24I C
Capacity
01=1K
02=2K
04=4K
L: -40~+85/ 08=8K
1.8V ~ 5.5V
S: -40~+85/
1.7V ~ 5.5V
Package
16=16K
32=32K
64=64K
128=128K
256=256K
F : SOP8
FJ : SOP-J8
FV : SSOP-B8
FVM : MSOP8
FVT :TSSOP-B8
FVJ :TSSOP-B8J
NUX :
VSON008X2030
forming specification
E2: Embossed tape and reel
TR: Embossed tape and reel
Package specifications
SOP8
<Tape and Reel information>
+6
4 4
6.20.3
4.40.2
0.3MIN
1 2
0.90.15
5.00.2
(MAX 5.35 include BURR)
Tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
0.595
1.50.1
+0.1
0.17 -0.05
0.11
1.27
0.420.1
1pin
Reel
(Unit : mm)
Direction of feed
SOP-J8
<Tape and Reel information>
4.90.2
(MAX 5.25 include BURR)
+6
4 4
6
0.45MIN
3.90.2
6.00.3
Tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
0.545
0.20.1
0.175
1.3750.1
1.27
0.420.1
0.1 S
1pin
Reel
(Unit : mm)
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Direction of feed
2009.09 - Rev.D
Technical Note
SSOP-B8
<Tape and Reel information>
3.0 0.2
(MAX 3.35 include BURR)
0.3MIN
4.40.2
6.40.3
8 76 5
Tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
1.150.1
1 23 4
0.15 0.1
0.1
S
0.1
+0.06
0.22 -0.04
(0.52)
0.08
0.65
1pin
Reel
(Unit : mm)
Direction of feed
TSSOP-B8
<Tape and Reel information>
3.0 0.1
(MAX 3.35 include BURR)
8
44
3000pcs
1PIN MARK
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
1.00.2
0.50.15
6.40.2
4.40.1
1
+0.05
0.145 0.03
S
0.10.05
1.2MAX
Quantity
Direction
of feed
0.525
1.00.05
Tape
0.08 S
+0.05
0.245 0.04
0.08
Direction of feed
1pin
0.65
Reel
(Unit : mm)
TSSOP-B8J
<Tape and Reel information>
3.0 0.1
(MAX 3.35 include BURR)
5
4.90.2
0.450.15
2
1PIN MARK
Tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
0.950.2
+0.05
0.145 0.03
0.525
S
0.10.05
0.850.05
1.1MAX
3.00.1
44
0.08 S
+0.05
0.32 0.04
0.08
1pin
0.65
Reel
(Unit : mm)
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Direction of feed
2009.09 - Rev.D
Technical Note
MSOP8
<Tape and Reel information>
2.80.1
4.00.2
8 7 6 5
0.60.2
+6
4 4
0.290.15
2.90.1
(MAX 3.25 include BURR)
Tape
Quantity
3000pcs
Direction
of feed
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
1 2 3 4
1PIN MARK
1pin
+0.05
0.145 0.03
0.475
+0.05
0.22 0.04
0.080.05
0.750.05
0.9MAX
0.08 S
Direction of feed
0.65
Reel
(Unit : mm)
VSON008X2030
<Tape and Reel information>
3.00.1
2.00.1
0.6MAX
1PIN MARK
0.25
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
(0.12)
+0.03
0.02 0.02
4000pcs
0.5
1
1.40.1
0.30.1
C0.25
1.50.1
Quantity
Direction
of feed
0.08 S
Tape
+0.05
0.25 0.04
1pin
Reel
(Unit : mm)
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Direction of feed
2009.09 - Rev.D
Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (Specific Applications), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHMs Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASS
CLASSb
CLASS
CLASS
CLASS
CLASS
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHMs Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
Notice - GE
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - GE
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHMs Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHMs Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an as is basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice WE
Rev.001