RTL Design Verification Engineer in Austin TX Resume Sumaira Khowaja
RTL Design Verification Engineer in Austin TX Resume Sumaira Khowaja
Email: [email protected]
SUMMARY
EDA Tools & Simulators
VCS, Verdi, DVE, Cadence Virtuoso Layout Schematic & Analog Mixed Signal suite,
Encounter RTL Compiler, HSpice, Xilinx ISE.
Programming/Scripting
Assembly, C/C++, Perl, Shell, Make
HDL
Verilog, VHDL
Computer Software & OS
Linux, Windows
Version Control Systems
Git, Clearcase
Six Sigma Tools
Lean, 5S, Pareto, FMEA, Cause & Effect, Root Cause & Fish Bone Analysis.
EDUCATION
MS Electrical Engineering, The University of Texas at San Antonio
B.E Electronics, Mehran University of Engineering & Technology, Pakistan.
Electronics Department.
PROFESSIONAL EXPERIENCE
Modeling and Simulation of a high tech IT City to be made in Karachi, Pakistan by Government of Sindh. The Urban Design
simulator used was Any Logic Software and back end coding was done in Java.
Modeled the different parameters of the IT City with respect to Utilities, Employment, Demographics and Transportation. The
software calculates parameters based on inputs provided and simulates the values into future, resulting from city expansion and
business growth.
Utilities model includes entire Electricity, Gas and Sewage consumption parameters of the IT City. Alternate Energy sources
such as Solar power are also incorporated. Employment and Demographics model takes inputs such as the number, type, nature
and Floor Area Ratio (FAR) of buildings in the IT city and returns the potential number of Employment opportunities created.
Transportation model includes simulation of traffic flow within and from outside the city, congestion control, alternate routes,
collisions and other scenarios.
Part of Post-Si group developing test and automation software and debugging of Intels ATOM based SoCs.
Working in Front End Design Automation (CAD) group supporting tools, flow, methodology and functional verification issues
for Intel Mobile SoCs and ATOM Core.
Owner for functional verification tools including Synopsys VCS, Verdi, DVE, Coverage. Debug simulation failures and tool
bugs during full chip and IP level testing and integration, carry out version migrations, provide continuous support to RTL and
Validation teams on simulation and tool bugs and test new technologies for compile and run time improvement i.e partition
compile, precompiled IP.
Get timing feedback and incorporate necessary changes in RTL.
Emulation model bring up tends to be a time consuming process in project lifetime and exposes new bugs in the RTL which are
undiscovered at simulation time. I solve this by trailblazing and introducing new technology into the project called Congruence
, at simulation time, which makes the RTL model behave as if it were running on emulator and catches emulation bugs early on
in the project lifecycle , saving months of time and $$$.
Led Front End RTL Model migration from Red Hat to SLES11 machines for Intel Mobile SoC project.
In depth knowledge of x86 processor.
Experience in functional verification and verification methodologies i.e OVM
Implemented paging structures i.e: page Directory and page table for virtual to physical address translation, tested its
functionality using a test stub, illustrated sequence of steps occurring on a page fault.
Design, Synthesis, Verification and Layout of a 16 bit CLA adder and Ripple Carry Adder
Designed a 16 bit Carry Look Ahead Adder and a 16 bit Ripple Carry Adder in Verilog HDL and simulated in Xilinx ISE.
Designed a test bench with random pattern generator to generate stimulus to verify the design.
Synthesized the code to generate the netlist using Cadence RTL Compiler.
Generated Schematic and GDS2 Layout of the design using Cadence Encounter tool.
Designed a high gain CMOS Operational Amplifier using Cadence Virtuoso tool
Obtained a differential mode Voltage gain of 95.6dB.
Implemented the design in two stages: The first stage was an active load differential Amplifier, the second stage was a
Common Source stage.
Biasing was done using Current Mirror Circuit.
Analog IC Design: Designed numerous Analog circuits including Operational Amplifier, High Gain Differential Op
Amp, Inverting Amp, Feedback Amplifier, Cascade Amp and Two Stage Amplifier using Cadence Simulator.
Intelligent ECG Recognition System using Neural Network: Undergrad Senior Project. Trained Artificial Neural
Network models to distinguish between normal and diseased ECG Patterns. Employed Signal Processing, Image
Recognition, Noise Filtering, Base line wandering and ANN Learning Algorithms. The simulation tool was MATLAB.
US Permanent Resident