Interfacing LCD With F Pga
Interfacing LCD With F Pga
Akhmad Hendriawan
[email protected]
Block Diagram
Pin Description
LCD Command
Implement to FPGA
Behaviour Simulation
It shown that thereis many unknown data that differ from behaviour simulation
Unknown Condition
My testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
en => en,
--USE ieee.numeric_std.ALL;
rs => rs,
ENTITY LCDTestBench IS
END LCDTestBench;
clock_process :process
COMPONENT LCDTest
PORT(
dataLCD : OUT std_logic_vector(3 downto 0);
en : OUT std_logic;
rs : OUT std_logic;
reset : IN std_logic;
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
clock : IN std_logic
);
END COMPONENT;
-- Stimulus process
stim_proc: process
--Inputs
begin
--
--
--Outputs
signal dataLCD : std_logic_vector(3 downto 0);
signal en : std_logic;
signal rs : std_logic;
--
wait;
wait for 500ns;
Onother approach(succeed)
LCD Initializations
8 bit instead of 4 bit
TestBench Simulation
Testing LCD controller with logic analyzer I've got good Result
OK
VHDL
library IEEE;
begin
use IEEE.STD_LOGIC_1164.ALL;
PSC : process(clk)
use IEEE.std_logic_unsigned.all;
--use IEEE.NUMERIC_STD.ALL;
prescaller := prescaller + 1;
else
prescaller := 0;
pscOut
library UNISIM;
end if;
use UNISIM.VComponents.all;
end if;
BUFG_inst : BUFG
reset : in std_logic;
port map(
Rs
: out STD_LOGIC;
O => pscClk,
En
: out STD_LOGIC;
I => pscOut
clk
: in STD_LOGIC);
);
end ROM;
MYCNT : process(pscClk,reset)
architecture Behavioral of ROM is
begin
:= '0';
:= '0';
cntOut <= 0;
end if;
end if;
end process MYCNT;
case cntOut is
when 0 => --delay
end case;
end if;
end process ROM;
end Behavioral;
end if;
end if;
end process MYCNT;
end case;
end if;