Xeon E5 1600 2600 Vol 2 Datasheet
Xeon E5 1600 2600 Vol 2 Datasheet
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Contents
1
Introduction .............................................................................................................. 9
1.1
Document Terminology ........................................................................................ 9
1.2
Related Documents ........................................................................................... 12
1.3
Register Terminology ......................................................................................... 12
3.5.8
4
Figures
2-1
2-2
3-1
3-2
3-3
Tables
1-1
1-2
1-3
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
Revision History
Revision
Number
Description
Date
001
Initial Release
March 2012
002
May 2012
003
May 2012
Introduction
Introduction
This is Volume 2 of the datasheet document that provides register information for the e
Intel Xeon Processor E5 Product Family. This document is intended to be distributed
as a part of the complete datasheet document. Throughout this document, Intel Xeon
Processor E5 Product Family may be referred to as simply the processor.
The Intel Xeon Processor E5 Product Family contain one or more PCI devices within a
single physical component. The configuration registers for these devices are mapped as
devices residing on the PCI Bus assigned for the processor socket. This document
describes these configuration space registers or device-specific control and status
registers (CSRs) only. This document does NOT include Model Specific Registers
(MSRs).
The Intel Xeon Processor E5 Product Family implement several key technologies:
Four channel Integrated Memory Controller supporting DDR3
Integrated I/O with up to 40 lanes for PCI Express* Generation 3.0
Point-to-point link interface based on Intel QuickPath Interconnect (Intel QPI).
Reference to this interface may sometimes be abbreviated with Intel QuickPath
Interconnect throughout this document. Note that the Intel Xeon E5-1600 product
family is for single socket platforms, thus it has no Intel QPI links.
The processor is optimized for performance with the power efficiencies of a low-power
microarchitecture to enable smaller, quieter systems.
Intel Xeon Processor E5 Product Family are multi-core processors, based on 32-nm
process technology. Processor features vary by SKU and include up to two Intel
QuickPath Interconnect point to point links capable of up to 8.0 GT/s, up to 20 MB of
shared cache, and an integrated memory controller. The processors support all the
existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3)
and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced
Technologies: Execute Disable Bit, Intel 64 Technology, Enhanced Intel SpeedStep
Technology, Intel Virtualization Technology (Intel VT), and Intel Hyper-Threading
Technology (Intel HT Technology).
1.1
Document Terminology
A # symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested.
Table 1-1.
Description
DDR3
Third generation Double Data Rate SDRAM memory technology that is the
successor to DDR2 SDRAM
DMA
DMI2
DTS
ECC
Introduction
Table 1-1.
10
Description
Enhanced Intel
SpeedStep Technology
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel 64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
Functional Operation
Responsible for memory transaction through the Ring and handles incoming/
outgoing memory transactions
Integrated Memory
Controller (IMC)
Intel 64 Technology
Intel Turbo Boost Technology is a way to automatically run the processor core
faster than the marked frequency if the part is operating under power, temperature, and current specifications limits of the Thermal Design Power (TDP). This
results in increased performance of both single and multi-threaded applications.
Intel TXT
Intel Virtualization
Technology (Intel VT)
Intel VT-d
Intel Virtualization Technology (Intel VT) for Directed I/O. Intel VT-d is a
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
Jitter
Any timing variation of a transition edge or edges from the defined Unit Interval
(UI).
IOV
I/O Virtualization
LGA2011 Socket
The 2011-land FC-LGA package mates with the system board through this
surface mount, 2011-contact socket.
NCTF
Non-Critical to Function: NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
NEBS
Network Equipment Building System. NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United
States.
NTB
Non-Transparent Bridge
Intels 32-nm processor design, follow-on to the 32-nm 2nd Generation Intel
Core Processor Family design. It is the first processor for use in Intel Xeon
processor E5-1600 and E5-2600 product families-based platforms. Intel
Xeon processor E5-1600 product family and Intel Xeon processor E5-2600
product family supports Efficient Performance server, workstation and HPC
platforms.
PCH
Platform Controller Hub. The next generation chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PCU
Introduction
Table 1-1.
Description
The third generation PCI Express specification that operates at twice the speed of
PCI Express 2.0 (8 Gb/s); however, PCI Express 3.0 is completely backward
compatible with PCI Express 1.0 and 2.0.
PECI
Processor
Processor Core
The term processor core refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Rank
RP
Ring
SCI
SSE
Server SKU
SMBus
System Management Bus. A two-wire interface through which simple system and
power management related devices can communicate with the rest of the
system. It is based on the principals of the operation of the I2C* two-wire serial
bus from Philips Semiconductor.
Storage Conditions
TAC
TDP
Uncore
The portion of the processor comprising the shared cache, IMC , IIO and Intel
QuickPath Interconnect Link interface
Unit Interval
UI
= t n- t
-1
VCC
VSS
Processor ground
x1
x4
x8
x16
11
Introduction
1.2
Related Documents
Refer to the following documents for additional information.
Table 1-2.
Referenced Documents
Document
1.3
Location
http://www.intel.com
http://www.intel.com
http://www.intel.com
http://www.acpi.info
http://www.intel.com
http://www.pcisig.com/specifications
http://www.pcisig.com
http://www.pcisig.com/specifications
http://www.jedec.org
http://www.intel.com/products/
processor/manuals/index.htm
http://download.intel.com/
technology/computing/vptech/
Intel(r)_VT_for_Direct_IO.pdf
http://www.intel.com/
technology/security/
Register Terminology
The bits in configuration register descriptions will have an assigned attribute from the
following table. Bits without a Sticky attribute are set to their default value by a hard
reset.
Note:
The table below is a comprehensive list of all possible attributes and included for
completeness.
Table 1-3.
Read Only: These bits can only be read by software, writes have no effect. The value of the
bits is determined by the hardware only.
RW
RC
Read Clear Variant: These bits can be read by software, and the act of reading them
automatically clears them. HW is responsible for writing these bits, and therefore the -V
modifier is implied.
W1S
12
Description
Write 1 to Set :Writing a 1 to these bits will set them to 1. Writing 0 will have no effect.
Reading will return indeterminate values and read ports are not requited on the register. These
are not supported by critter, and today is only allowed in the Cbo.
Introduction
Table 1-3.
Description
WO
Write Only: These bits can only be written by microcode, reads return indeterminate values.
Microcode that wants to ensure this bit was written must read wherever the side-effect takes
place.
RW-O
Read / Write Once: These bits can be read by software. After reset, these bits can only be
written by software once, after which the bits becomes Read Only.
RW-L
Read / Write Lock: These bits can be read and written by software. Hardware can make
these bits Read Only via a separate configuration bit or other logic.
RW1C
Read / Write 1 to Clear: These bits can be read and cleared by software. Writing a 1 to a
bit clears it, while writing a 0 to a bit has no effect.
ROS
RO Sticky: These bits can only be read by software, writes have no effect. The value of the
bits is determined by the hardware only. These bits are only re-initialized to their default value
by a PWRGOOD reset.
RW1S
Read, Write 1 to Set: These bits can be read. Writing a 1 to a given bit will set it to 1. Writing
a 0 to a given bit will have no effect. It is not possible for software to set a bit to 0. The 1->0
transition can only be performed by hardware. These registers are implicitly -V.
RWS
R / W Sticky: These bits can be read and written by software. These bits are only reinitialized to their default value by a PWRGOOD reset.
RW1CS
R / W1C Sticky: These bits can be read and cleared by software. Writing a 1 to a bit clears
it, while writing a 0 to a bit has no effect. These bits are only re-initialized to their default
value by a PWRGOOD reset.
RW-LB
Read/Write Lock Bypass: Similar to RWL, these bits can be read and written by software.
HW can make these bits Read Only via a separate configuration bit or other logic. However,
RW-LB is a special case where the locking is controlled by the lock-bypass capability that is
controlled by the lock-bypass enable bits. Each lock-bypass enable bit enables a set of config
request sources that can bypass the lock. The requests sourced from the corresponding
bypass enable bits will be lock-bypassed (i.e. RW) while requests sourced from other sources
are under lock control (RO). The lock bit and bypass enable bit are generally defined with RWO
attributes. Sticky can be used with this attribute (RW-SWB). These bits are only reinitialized to
their default values after PWRGOOD. Note that the lock bits may not be sticky, and it is
important that they are written to after reset to guarantee that software will not be able to
change their values after a reset.
RO-FW
Read Only Forced Write: These bits are read only from the perspective of the cores.
However, microcode is able to write to these registers.
RWS-O
If a register is both sticky and once then the sticky value applies to both the register value
and the once characteristic. Only a PWRGOOD reset will reset both the value and the once
so that the register can be written to again.
RW-V
These bits may be modified by hardware. Software cannot expect the values to stay
unchanged. This is similar to volatile in software land.
RWS-L
If a register is both sticky and locked, then the sticky behavior only applies to the value. The
sticky behavior of the lock is determined by the register that controls the lock.
RV
Reserved: These bits are reserved for future expansion and their value must not be modified
by software. When writing these bits, software must preserve the value read. The bits are
read-only must return 0 when read.
13
Introduction
14
2.1
2.1.1
Figure 2-1.
Processor
DMI2 Host
Bridge or PCIe*
Root Port
(Device 0)
PCH
DMA
Engine
(Device 4)
PCIe Port 1
PCIe Port 2
PCIe Port 3d
(Dev#3, F#3)
PCIe Port 3c
(Dev#3, F#2)
PCIe Port 3b
(Dev#3, F#1)
PCIe Port 3a
(Dev#3, F#0)
PCIe Port 2d
(Dev#2, F#3)
PCIe Port 2c
(Dev#2, F#2)
PCIe Port 2b
(Dev#2, F#1)
PCIe Port 2a
(Dev#2, F#0)
PCIe Port 1b
(Dev#1, F#1)
PCIe Port 1a
(Dev#1, F#0)
Bus= CPUBUSNO(0)
PCIe Port 3
Device 0: DMI2 Root Port. Logically this appears as a PCI device residing on PCI
Bus 0. Device 0 contains the standard PCI header registers, extended PCI
configuration registers and DMI2 device specific configuration registers.
Device 1: PCI Express Root Port 1a and 1b. Logically this appears as a virtual
PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with the PCI Express Local
Bus Specification Revision 2.0. Device 1 contains the standard PCI Express/PCI
configuration registers including PCI Express Memory Address Mapping registers. It
15
also contains the extended PCI Express configuration space that include PCI
Express error status/control registers and Isochronous and Virtual Channel
controls.
Device 3: PCI Express Root Port 3a, 3b, 3c and 3d. Logically this appears as a
virtual PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with PCI Express
Local Bus Specification Revision 2.0. Device 3 contains the standard PCI Express/
PCI configuration registers including PCI Express Memory Address Mapping
registers. It also contains the extended PCI Express configuration space that
include PCI Express error status/control registers and Isochronous and Virtual
Channel controls.
Device 4: Intel QuickData Technology. This device contains the Standard PCI
registers for each of its functions. This device implements 8 functions for the 8 DMA
Channels and also contains Memory Map I/O registers.
Device 5: Integrated I/O Core. This device contains the Standard PCI registers for
each of its functions. This device implements three functions; Function 0 contains
Address Mapping, Intel Virtualization Technology (Intel VT) for Directed I/O
(Intel VT-d) related registers and other system management registers. Function 2
contains I/O RAS registers, Function 4 contains System Control/Status registers
and miscellaneous control/status registers on power management and throttling.
Function 6 contains the IIO Switch and IRP Performance monitor registers.
2
16
2.1.2
Figure 2-2.
Processor
Intel QPI
Link 0
(Device 8,
Function:
(0,3)
Intel QPI
Link 1
(Device 9,
Function:
(0,3)
CPU Interrupt
Handlin(UBOX)
(Device 11,
Function 0 and 3)
Core
Broadcast(CBO)
(Device 12,
Function 0-3,6 and
7), Device
13,Function 0-3,6)
Bus= CPUBUSNO(1)*
Power
Control
Unit(PCU)
(Device 10,
Function 03)
Performance
Monitoring
(Device
8,9,14,16 and
19)
Device 8: Intel QPI Link 0. Device 8, Function 0 and 3 contain the configurable
Intel QPI Link 0 registers
Device 9: Intel QPI Link 1. Device 8, Function 0 and 3 contain the configurable
Intel QPI Link 1 registers.
Device 10: Processor Power Control Unit. Device 10, Function 0-3 contains the
configurable PCU registers.
Device 11: Processor Interrupt Event Handling. Device 11, Function 3 contains the
Semaphore and Scratchpad configuration registers. Device 11, Function 0 contains
the processor Interrupt control registers.
Device 12: Processor Core Broadcast. Device 12, Function 0-3 contains the
Unicast configuration registers, Function 6 contains the Caching agent broadcast
configuration registers for the Memory Controller. Function 7 contains the System
Address Decode registers.
Device 13: Processor Core Broadcast. Device 13, Function 0-3 contain the Unicast
registers, Function 6 contains the Caching agent broadcast configuration registers
for the Memory Controller.
Device 14: Processor Home Agent. Device 14, Function 0 contains the processor
Home Agent Target Address configuration registers for the Memory Controller.
Device 14, Function 1 contains processor Home Agent performance monitoring
registers.
17
Device 15: Integrated Memory Controller. Device 15, Function 0 contains the
general and MemHot registers for the Integrated Memory Controller and resides.
Function 1 contains the RAS registers for Integrated Memory Controller. Device 15,
Function 2-5 contains the Target Address Decode, Channels Rank and Memory
Timing Registers.
Device 16: Integrated Memory Controller Channel 0, 1, 2 and 3. Device 16,
Function 0, 1, 4 and 5 contains the Thermal control registers for Integrated
Memory Controller. Channel 0, Channel 1, Channel 2, Channel 3. Device 16,
Function 2, 3, 6 and 7 contains the test registers for the Integrated Memory
Controller.
Device 19: Processor Performance Monitoring and Ring. Device 19, Function 4
contains the Intel QPI agent Ring registers. Device 19, Function 1 contains the
processor Ring to PCI Express performance monitoring registers. Device 19,
Function 5 contains the processor Ring to Intel QPI Link 0 performance monitoring
registers and resides. Device 19, Function 6 contains the processor Ring to Intel
QPI Link 1 performance monitoring registers.
2.2
2.2.1
CSR Access
Configuration space registers are accessed via the well known configuration transaction
mechanism defined in the PCI specification and this uses the bus:device:function
number concept to address a specific devices configuration space. Accesses to PCI
configuration registers is achieved via NcCfgRd/Wr transactions on the Ring or Intel
QPI.
All configuration register accesses are accessed through the UBox but might come from
a variety of different sources:
Local cores
Remote cores (over Intel QuickPath Interconnect)
PECI or JTAG
This unit supports PCI configuration space access as defined in the PCI Express Base
Specification, Revision 2.0. Configuration registers can be read or written in Byte,
WORD (16-bit), or DWORD (32-bit) quantities. Accesses larger than a DWORD to PCI
Express configuration space will result in unexpected behavior. All multi-byte numeric
fields use little-endian ordering (that is, lower addresses contain the least significant
parts of the field).
2.2.2
18
2.2.3
2.3
Configuration Mechanisms
The processor is the originator of configuration cycles. Internal to the processor,
transactions received through both of the below configuration mechanisms are
translated to the same format.
2.3.1
2.4
Device Mapping
Each component in the processor is uniquely identified by a PCI bus address consisting
of Bus Number, Device Number and Function Number. Device configuration is based on
the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus
assigned for the processor socket. Bus number is derived by the max bus range setting
and processor socket number.
Table 2-1.
DID
Device
Function
Comment
DMI2
3C00h
3C01h
3C02h,
3C03h
0 -1
3C04h,
3C05h,
3C06h,
3C07h
0 -3
3C08h,
3C09h,
3COAh,
3C0Bh
0-3
3C0D
19
Table 2-1.
20
Device
Function
3C0E
DID
Comment
3C0F
Core
3C28h
Core
3C2Ah
Core
3C2Ch
I/O APIC
Core
3C40h
3C20h,
3C21h,
3C22h,
3C23h,
3C24h,
3C25h,
3C26h,
3C27h
0-7
3C2E 3C2F
0-1
RAID 5/6
3C80h
3C90h
3C83h,
3C84h
3,4
3C93h,
3C94h
3,4
PCU
3CC0h,
3CC1h,
3CC2h
3CD0h
10
0-3
UBOX
3CE0h
11
UBOX
3CE3h
11
3CE8h
12
0-3
Unicast Registers
3CE8h
13
0-3
Unicast Registers
3CF4h
12
3CF6h
12
3CF5h
13
Broadcast Registers
3CA0h,
3C46h
14
0-1
3CA8h
15
3C71h
15
RAS Registers
3CAAh,
3CABh,
3CACh,
3CADh,
3CAEh
15
2 -6
3CB2h,
3CB3h,
3CB6h,
3CB7h
16
2, 3, 6, 7
3CB0h,
3CB1h,
3CB4h,
3CB5h
16
0, 1, 4, 5
3CB8h
17
DDRIO
Table 2-1.
Function
R2PCIe
Register Group
3CE4h
DID
19
R2PCIE
Comment
R2PCIe
3C43h
19
3C44h
19
3C45h
19
R3 Intel QPI
3CE6h
19
21
22
3.1
3.2
3.2.1
3.2.2
3.2.3
23
Figure 3-1.
DMI2 Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space
Extended
Configuration Space
0 xFFF
VSEC- AER
Capability
VSEC- REUT
Capability
0x 100
PCI Device
Dependent
PCIe Capability
0x40
CAP_ PTR
Type0 Header
0x00
Note:
24
PCI Header
Legacy
Configuration Space
PM Capability
VSEC stands for Vendor Specific Extended Capability. In DMI2 mode, AER appears as a vendor specific
extended capability.
Figure 3-2.
Ext ended
Configuration Space
0 xFFF
AER Capability
ACS
Capability
VSEC - REUT
Capability
0 x100
PCI Device
Dependent
PCIe Capability
MSI Capability
SVID / SDID Capability
0x 40
CAP_ PTR
P2 P Header
0x 00
PCI Header
Legacy
Configur ation Space
PM Capability
Figure 3-2 illustrates how each PCI Express/DMI2 ports configuration space appears to
software. Each PCI Express configuration space has three regions:
Standard PCI Header - This region is the standard PCI-to-PCI bridge header
providing legacy OS compatibility and resource management.
PCI Device Dependent Region - This region is also part of standard PCI
configuration space and contains basic PCI capability structures and other port
specific registers. For Intel Xeon processor E5 product family, the supported
capabilities are:
SVID/SDID Capability
Message Signalled Interrupts
Power Management
PCI Express Capability
PCI Express Extended Configuration Space - This space is an enhancement
beyond standard PCI and only accessible with PCI Express aware software.
25
3.2.4
Table 3-1.
DID
VID
PCISTS
PCICMD
CCR
BIST
HDR
RID
PLAT
CLSR
0h
80h
4h
84h
8h
88h
Ch
10h
8Ch
PXPCAP
14h
SDID
SVID
PXPNXTPTR
PXPCAPID
DEVCAP
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ROOTCON
30h
CAPPTR
DMIRCBAR
INTL
34h
DEVCAP2
B4h
B8h
3Ch
LNKCAP2
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
PMCAP
64h
PMCSR
E0h
E4h
68h
E8h
6Ch
70h
ECh
DEVSTS
DEVCTRL
74h
78h
7Ch
26
ACh
B0h
38h
INTPIN
90h
F0h
F4h
DEVCTRL2
F8h
FCh
Table 3-2.
100h
XPREUT_HDR_CAP
104h
XPREUT_HDR_LEF
108h
180h
PERFCTRLSTS
184h
188h
MISCCTRLSTS
10Ch
110h
18Ch
PCIE_IOU_BIF_CTRL
114h
194h
118h
198h
11Ch
19Ch
120h
1A0h
DMICTRL
124h
128h
1A4h
DMISTS
1A8h
12Ch
130h
1ACh
LNKSTS
LNKCON
APICBASE
1B0h
134h
1B4h
138h
1B8h
13Ch
APICLIMIT
190h
140h
1BCh
LNKSTS2
LNKCON2
1C0h
VSECHDR
144h
1C4h
VSHDR
148h
1C8h
UNCERRSTS
14Ch
UNCERRMSK
150h
ERRINJCAP
UNCERRSEV
154h
ERRINJHDR
CORERRSTS
158h
CORERRMSK
15Ch
ERRCAP
160h
HDRLOG0
164h
1E4h
HDRLOG1
168h
1E8h
1CCh
1D0h
1D4h
ERRINJCON
1D8h
1DCh
CTOCTRL
1E0h
HDRLOG2
16Ch
1ECh
HDRLOG3
170h
1F0h
RPERRCMD
174h
1F4h
RPERRSTS
178h
1F8h
ERRSID
17Ch
1FCh
27
Table 3-3.
200h
LER_CAP
XPCORERRMSK
204h
LER_HDR
284h
XPUNCERRSTS
208h
LER_CTRLSTS
288h
XPUNCERRMSK
20Ch
LER_UNCERRMSK
28Ch
XPUNCERRSEV
210h
LER_XPUNCERRMSK
290h
214h
LER_RPERRMSK
294h
XPUNCERR
PTR
UNCEDMASK
218h
298h
COREDMASK
21Ch
29Ch
RPEDMASK
220h
2A0h
XPUNCEDMASK
224h
2A4h
XPCOREDMASK
228h
2A8h
22Ch
2ACh
230h
2B0h
234h
2B4h
238h
2B8h
23Ch
2BCh
240h
2C0h
244h
2C4h
248h
2C8h
XPGLBERRPTR
XPGLBERRSTS
24Ch
2CCh
250h
2D0h
254h
2D4h
258h
2D8h
25Ch
2DCh
260h
2E0h
264h
2E4h
268h
2E8h
26Ch
270h
Table 3-4.
VID
PCISTS
2F0h
274h
2F4h
278h
2F8h
27Ch
2FCh
0h
PCICMD
CCR
28
2ECh
XPPMDFXMAT0
Device 0/Function 0 (PCIe* Root Port Mode), Device 1/Functions 0-1 (PCIe
Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/
Function 0-3 (PCIe Root Ports) Legacy Configuration Map (Sheet 1 of 2)
DID
BIST
280h
HDR
PLAT
80h
4h
84h
RID
8h
88h
CLSR
Ch
8Ch
Table 3-4.
Device 0/Function 0 (PCIe* Root Port Mode), Device 1/Functions 0-1 (PCIe
Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/
Function 0-3 (PCIe Root Ports) Legacy Configuration Map (Sheet 2 of 2)
10h
PXPCAP
14h
SUBBUS
SECBUS
SECSTS
IOLIM
MLIM
PBUS
18h
IOBAS
1Ch
MBAS
PLIM
20h
PBAS
LNKCAP
24h
PLIMU
2Ch
ROOTCAP
30h
ROOTSTS
34h
DEVCAP2
38h
INTPIN
INTL
3Ch
SNXTPTR
SCAPID
40h
SDID
SVID
DMIRCBAR1
MSINXTPTR
MSICAPID
A0h
SLTCON
A8h
ROOTCON
ACh
A4h
B0h
B4h
LNKCAP2
B8h
BCh
LNKCON2
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
MSIMSGCTL
9Ch
DEVCTRL2
LNKSTS2
98h
LNKCON
SLTCAP
SLTSTS
90h
94h
DEVCTRL
LNKSTS
28h
BCTRL
PXPCAPID
DEVCAP
DEVSTS
PBASU
CAPPTR
PXPNXTPTR
DCh
60h
PMCAP
E0h
MSGADR
64h
PMCSR
MSGDAT
68h
E8h
MSIMSK
6Ch
ECh
MSIPENDING
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
E4h
Notes:
1. DMIRCBAR - Device 0 Only
29
Table 3-5.
Device 0/Function 0 (PCIe Root Port Mode), Device 1/Functions 0-1 (PCIe
Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/
Function 0-3 (PCIe Root Ports) Extended Configuration Map 100 - 0x1FFh
XPREUT_HDR_EXT
100h
XPREUT_HDR_CAP
104h
XPREUT_HDR_LEF
108h
PERFCTRLSTS
180h
184h
MISCCTRLSTS
188h
10Ch
ACSCAPHDR
ACSCTRL
APICLIMIT
30
110h
ACSCAP
APICBASE
18Ch
PCIE_IOU_BIF_CTRL
114h
190h
194h
118h
198h
11Ch
19Ch
120h
1A0h
124h
1A4h
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
ERRCAPHDR
148h
1C8h
UNCERRSTS
14Ch
1CCh
UNCERRMSK
150h
ERRINJCAP
1D0h
UNCERRSEV
154h
ERRINJHDR
1D4h
CORERRSTS
158h
CORERRMSK
15Ch
ERRCAP
160h
HDRLOG0
164h
ERRINJCON
1D8h
1DCh
CTOCTRL
1E0h
1E4h
HDRLOG1
168h
1E8h
HDRLOG2
16Ch
1ECh
HDRLOG3
170h
1F0h
RPERRCMD
174h
1F4h
RPERRSTS
178h
1F8h
ERRSID
17Ch
1FCh
Table 3-6.
Device 0/Function 0 (PCIe Root Port Mode), Device 1/Functions 0-1 (PCIe
Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/
Function 0-3 (PCIe Root Ports) Extended Configuration Map - Offset 0x2000x2FCh
XPCORERRSTS
200h
280h
XPCORERRMSK
204h
LER_HDR
284h
XPUNCERRSTS
208h
LER_CTRLSTS
288h
XPUNCERRMSK
20Ch
LER_UNCERRMSK
28Ch
XPUNCERRSEV
210h
LER_XPUNCERRMSK
290h
XPUNCERR
PTR
214h
LER_RPERRMSK
294h
UNCEDMASK
218h
298h
COREDMASK
21Ch
29Ch
RPEDMASK
220h
2A0h
XPUNCEDMASK
224h
2A4h
XPCOREDMASK
228h
2A8h
22Ch
2ACh
230h
2B0h
234h
2B4h
238h
2B8h
23Ch
2BCh
240h
2C0h
244h
2C4h
248h
2C8h
XPGLBERRPTR
XPGLBERRSTS
24Ch
2CCh
PXP2CAP4
250h
2D0h
LNKCON34
254h
2D4h
LNERRSTS4
258h
2D8h
25Ch
2DCh
LN3EQ4
LN2EQ4
260h
2E0h
264h
2E4h
LN7EQ5
LN6EQ5
268h
2E8h
LN9EQ3
LN8EQ3
26Ch
LN11EQ3
LN10EQ3
270h
XPPMDFXMAT01
2F0h
274h
XPPMDFXMAT1
2F4h
LN14EQ3
278h
XPPMDFXMSK03
2F8h
27Ch
2FCh
LN1EQ
LN5EQ
LN13EQ
LN0EQ
LN4EQ
LN15EQ3
1.
2.
3.
4.
5.
LER_CAP
Applicable
Applicable
Applicable
Applicable
Applicable
to
to
to
to
to
Device
Device
Device
Device
Device
LN12EQ
2ECh
XPPMDFXMSK1
0,2,3/Function 0.
2/Function 0.
2,3/Function 0.
1-3.
1/Function 0 and Device 2,3/Function 0,2.
31
3.2.5
3.2.5.1
Register: VID
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.2
Bit
Attr
Default
15:0
RO
8086h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
00h
00h
00h
00h (PCIe Root Port Mode)
00h
Description
Vendor Identification Number
The value is assigned by PCI-SIG to Intel.
DID
Bus:
Bus:
Bus:
Bus:
Bus:
32
Device:
Device:
Device:
Device:
Device:
0
0
0
0
0
Device:
Device:
Device:
Device:
Device:
Bit
Attr
15:0
RO
Default
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
02h
02h
02h
02h (PCIe Root Port Mode)
02h
Description
Device Identification Number
Device IDs for PCI Express root ports are as follows:
0x3C00: Device 0 in DMI mode
0x3C01: the DMI port running in PCIe mode
0x3C02: Port 1a
0x3C03: Port 1b
0x3C04: Port 2a
0x3C05: Port 2b
0x3C06: Port 2c
0x3C07: Port 2d
0x3C08: Port 3a in PCIe mode
0x3C09: Port 3b
0x3C0A: Port 3c
0x3C0B: Port 3d
The value is assigned by Intel to each product. For IIO NTB Secondary Endpoint,
the device ID is 0x3C0F.
3.2.5.3
PCICMD
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
Device:
Device:
Device:
Device:
Device:
Attr
0
1
2
3
3
Default
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
04h
04h
04h
04h (PCIe Root Port Mode)
04h
Description
15:11
RV
0h
Reserved
10
RW
0b
INTxDisable
Interrupt Disable. Controls the ability of the PCI Express port to generate INTx
messages. This bit does not affect the ability of processor to route interrupt
messages received at the PCI Express port. However, this bit controls the
generation of legacy interrupts to the DMI for PCI Express errors detected
internally in this port (for example, Malformed TLP, CRC error, completion time
out, and so forth) or when receiving RP error messages or interrupts due to HP/PM
events generated in legacy mode within processor.
1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
RO
0b
RW
0b
RO
0b
RW
0b
RO
0b
RO
0b
RO
0b
33
PCICMD
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.4
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
04h
04h
04h
04h (PCIe Root Port Mode)
04h
Bit
Attr
Default
Description
RW
0b
RW
0b
RW
0b
IO Space Enable
1: Enables the I/O address range, defined in the IOBASE and IOLIM registers of
the PCI-to-PCI bridge header, for target decode from primary side.
0: Disables the I/O address range, defined in the IOBASE and IOLIM registers of
the PCI-to-PCI bridge header, for target decode from primary side.
Notes: This bit is not ever used by hardware to decode transactions from the
secondary side of the root port. NTB does not support I/O space accesses.
Hardwired to 0
PCISTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
34
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
06h
06h
06h
06h (PCIe Root Port Mode)
06h
Bit
Attr
Default
Description
15
RW1C
0b
PCISTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
06h
06h
06h
06h (PCIe Root Port Mode)
06h
Bit
Attr
Default
Description
14
RW1C
0b
13
RW1C
0b
12
RW1C
0b
11
RW1C
0b
10:9
RO
0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
RW1C
0b
RO
0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
RO
0b
Reserved
RO
0b
RO
1b
Capabilities List
This bit indicates the presence of a capabilities list structure
35
PCISTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.5
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
06h
06h
06h
06h (PCIe Root Port Mode)
06h
Attr
Default
Description
RO-V
0b
INTx Status
This Read-only bit reflects the state of the interrupt in the PCI Express Root Port.
Only when the Interrupt Disable bit in the command register is a 0 and this
Interrupt Status bit is a 1, will this device generate INTx interrupt. Setting the
Interrupt Disable bit to a 1 has no effect on the state of this bit.This bit does not
get set for interrupts forwarded to the root port from downstream devices in the
hierarchy. When MSI are enabled, Interrupt status should not be set.
The intx status bit should be deasserted when all the relevant events (RAS errors/
HP/link change status/PM) internal to the port using legacy interrupts are cleared
by software.
2:0
RV
0h
Reserved
0
0
0
0
0
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
7:0
RO
00h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
0-3
Offset:
Offset:
Offset:
Offset:
Offset:
08h
08h
08h
08h (PCIe Root Port Mode)
08h
Description
Revision Identification
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register
in any Intel Xeon Processor E5 Family function.
Implementation Note:
Read and write requests from the host to any RID register in any Intel Xeon
Processor E5 Family function are re-directed to the IIO cluster. Accesses to the
CCR field are also redirected due to DWORD alignment. It is possible that JTAG
accesses are direct, so will not always be redirected.
CCR
Bus:
Bus:
Bus:
Bus:
Bus:
36
0
1
2
3
3
Bit
RID
Bus:
Bus:
Bus:
Bus:
Bus:
3.2.5.6
Device:
Device:
Device:
Device:
Device:
0
0
0
0
0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
09h
09h
09h
09h (PCIe Root Port Mode)
09h
Bit
Attr
Default
Description
23:16
RO
06h
Base Class
For Root ports (including the root port mode operation of DMI and NTB ports) this
field is hardwired to 06h, indicating it is a Bridge Device.
15:8
RO
04h
Sub-Class
For Root ports, this field defaults to 04h indicating PCI-PCI bridge. This register
changes to the sub class of 00h to indicate Host Bridge, when bit 0 in the
MISCCTRLSTS register is set.
7:0
RO
00h
3.2.5.7
CLSR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.8
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
7:0
RW
0h
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
0Ch
0Ch
0Ch
0Ch (PCIe Root Port Mode)
0Ch
Description
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for Intel
Xeon Processor E5 Family is always 64B. IIO hardware ignores this setting.
PLAT
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.9
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
7:0
RO
0h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
0Dh
0Dh
0Dh
0Dh (PCIe Root Port Mode)
0Dh
Description
Primary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
HDR
Bus: 0
Device: 0
Bit
Attr
Default
RO
0b
6:0
RO-V
00h
Function: 0
Offset: 0Eh
Description
Multi-function Device
This bit defaults to 0 for Device#0.
Configuration Layout
This field identifies the format of the configuration header layout.
In DMI mode, default is 00h indicating a conventional type 00h PCI header.
In PCIe mode, the default is 01h, corresponding to Type 1 for a PCIe root port.
37
3.2.5.10
HDR
Bus:
Bus:
Bus:
Bus:
3.2.5.11
0
0
0
0
Device:
Device:
Device:
Device:
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
0Eh
0Eh
0Eh (PCIe Root Port Mode)
0Eh
Attr
Default
Description
RO-V
1b
Multi-function Device
This bit defaults to 1 for Devices 1-3 since these are multi-function devices.
BIOS can individually control the value of this bit in Function 0 of these devices,
based on HDRTYPCTRL register. BIOS will write to that register to change this field
to 0 in Function 0 of these devices, if it exposes only Function 0 in the device to
OS.
Note:
In product SKUs where only Function 0 of the device is exposed to any software
(BIOS/OS), BIOS would have to still set the control bits mentioned above to set
the this bit in this register to be compliant per PCI rules.
6:0
RO
01h
Configuration Layout
This field identifies the format of the configuration header layout. It is Type1 for all
PCI Express root ports. The default is 01h, indicating a PCI to PCI Bridge.
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
7:0
RO
0h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
0Fh
0Fh
0Fh
0Fh (PCIe Root Port Mode)
0Fh
Description
BIST Tests
Not supported. Hardwired to 00h.
PBUS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
38
Function:
Function:
Function:
Function:
Bit
BIST
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.12
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
7:0
RW
00h
3.2.5.13
SECBUS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.14
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
7:0
RW
00h
SUBBUS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.15
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
7:0
RW
00h
IOBAS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
7:4
RW
Fh
3:2
RW-L
3h
1:0
RO
0h
39
3.2.5.16
IOLIM
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.17
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
7:4
RW
0h
3:2
RW-L
0h
1:0
RO
0h
SECSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
40
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15
RW1C
0b
14
RW1C
0b
13
RW1C
0b
12
RW1C
0b
SECSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.18
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
11
RW1C
0b
10:9
RO
00b
RW1C
0b
RO
0b
RV
0h
Reserved
RO
0b
4:0
RV
0h
Reserved
MBAS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15:4
RW
FFFh
3:0
RV
0h
Reserved
41
3.2.5.19
MLIM
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.20
Device:
Device:
Device:
Device:
Device:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Attr
Default
Description
15:4
RW
000h
3:0
RV
0h
Reserved
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
15:4
RW
FFFh
3:0
RO
1h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Prefetchable Memory Base Address
Corresponds to A[31:20] of the prefetchable memory address ranges base
address of the PCI Express port. See also the PLIMU register description.
Prefetchable Memory Base Address Capability
IIO sets this bit to 01h to indicate 64-bit capability.
PLIM
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
42
Function:
Function:
Function:
Function:
Function:
Bit
PBAS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.21
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
15:4
RW
000h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Prefetchable Memory Limit Address
Corresponds to A[31:20] of the prefetchable memory address ranges limit
address of the PCI Express port. See also the PLIMU register description.
PLIM
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.22
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
3:0
RO
1h
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Prefetchable Memory Limit Address Capability
IIO sets this field to 01h to indicate 64-bit capability.
PBASU
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.23
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
Bit
Attr
31:0
RW
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Default
Offset:
Offset:
Offset:
Offset:
Offset:
Description
PLIMU
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
31:0
RW
000000
00h
43
3.2.5.24
SVID
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.25
Device:
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
15:0
RW-O
8086h
Bit
Attr
Default
15:0
RW-O
00h
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Subsystem Vendor ID
Assigned by PCI-SIG for the subsystem vendor. This defaults to 8086 but can be
changed by BIOS.
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Subsystem Device ID
Assigned by the subsystem vendor to uniquely identify the subsystem
Device: 0
Bit
Attr
Default
7:0
RO
90h
Function: 0
Offset: 34h
Description
Capability Pointer
Points to the first capability structure for the device.
In DMI mode, it points to the PCIe capability.
In PCIe mode, it points to the SVID/SDID capability.
CAPPTR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
44
0
0
0-1
0-3
0
1-3
Description
Device:
Device:
Device:
Device:
Device:
Device:
CAPPTR
Bus: 0
3.2.5.27
Function:
Function:
Function:
Function:
Function:
Function:
SDID
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.26
0
0
1
2
3
3
Device:
Device:
Device:
Device:
1
2
3
3
Function:
Function:
Function:
Function:
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
34h
34h
34h (PCIe Root Port Mode)
34h
Bit
Attr
Default
Description
7:0
RO
40h
Capability Pointer
Points to the first capability structure for the device which is the SVID/SDID
capability.
Notes:
The attribute of B0, D3, F0 in root port mode is RW-O. For other devices, it is RO.
3.2.5.28
INTL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.29
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
3Ch
3Ch
3Ch
3Ch (PCIe Root Port Mode)
3Ch
Bit
Attr
Default
Description
7:0
RW
00h
Interrupt Line
This is RW only for compatibility reasons. IIO h/w does not use it for any reason.
INTPIN
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.30
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
3Dh
3Dh
3Dh
3Dh (PCIe Root Port Mode)
3Dh
Bit
Attr
Default
Description
7:0
RW-O
01h
Interrupt Pin
The only allowed values in this register are 00h and 01h.
BIOS will leave the register at its default value unless it chooses to fully defeature
INTx generation from a root port. For the latter scenario, BIOS will write a value of
00h before OS takes control. OS when it reads this register to be 00h understands
that the root port does not generate any INTx interrupt. This helps simplify some
of the BIOS ACPI tables relating to interrupts, when INTx interrupt generation
from a root port is not enabled in the platform.
Note that when BIOS writes a value of 00h in this register, that in itself does not
disable INTx generation in hardware. Disabling INTx generation in hardware has
to be achieved through the INTx Disable bit in the PCICMD: PCI Command
Register register. Also, reader is referred to the MSI enable bit in MSICTRL: MSI
Control for a description of how software selects MSI vs. INTx interrupt for the
system interrupt method.
IIO hardware does not use this bit for anything.
For DMI mode operation, it is not applicable, since Device#0 does not generate
any INTx interrupts on its own while in DMI mode.
BCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15:12
RV
0h
Reserved
11
RO
0b
10
RO
0b
RO
0b
45
BCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
46
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RO
0b
RO
0b
RW
0b
RO
0b
RW
0b
RW
0b
VGA Enable
Controls the routing of Intel Xeon Processor E5 Family initiated transactions
targeting VGA compatible I/O and memory address ranges. This bit must only be
set for one p2p port in the entire system.
Note: When Device 3 Function 0 is in NTB mode, then the Device 3 Function 0
version of this bit must be left at default value. VGA compatible devices
are not supported on the secondary side of the NTB.
RW
0b
ISA Enable
Modifies the response by the root port to an I/O access issued by the core that
target ISA I/O addresses. This applies only to I/O addresses that are enabled by
the IOBASE and IOLIM registers.
1: The root port will not forward to PCI Express any I/O transactions addressing
the last 768 bytes in each 1 KB block even if the addresses are within the range
defined by the IOBASE and IOLIM registers.
0: All addresses defined by the IOBASE and IOLIM for core issued I/O transactions
will be mapped to PCI Express.
RW
0b
RW
0b
3.2.5.31
SCAPID
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.32
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
7:0
RO
0Dh
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Capability ID
Assigned by PCI-SIG for subsystem capability ID
SNXTPTR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.33
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
7:0
RO
60h
Next Ptr
This field is set to 60h for the next capability list (MSI capability structure) in the
chain.
DMIRCBAR
Bus: 0
Device: 0
Function: 0
Offset: 50h
Bit
Attr
Default
Description
31:12
RW-LB
00000h
11:1
RV
0h
Reserved
RW-LB
0b
DMIRCBAR Enable
0: DMIRCBAR is disabled and does not claim any memory
1: DMIRCBAR memory mapped accesses are claimed and decoded
Notes:
Accesses to registers pointed to by the DMIRCBAR, via JTAG mini-port are not
gated by this enable bit, that is, accesses these registers are honored regardless
of the setting of this bit.
BIOS sets this bit only when it wishes to update the registers in the DMIRCBAR. It
must clear this bit when it has finished changing values. This is required to ensure
that the registers cannot be changed during an LT lock. This bit is protected by LT
mode, but the registers in DMIRCBAR are not protected except by this bit.
47
3.2.5.34
MSICAPID
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.35
Bit
Attr
Default
7:0
RO
05h
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Capability ID
Assigned by PCI-SIG for MSI (root ports).
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
7:0
RW-O
90h
Next Ptr
This field is set to 90h for the next capability list (PCI Express capability structure)
in the chain.
0_3_0_Port3_NTB: Attr: RW-O Default: 80h
MSIMSGCTL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
48
0
1
2
3
3
MSINXTPTR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.36
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
1
2
3
Function:
Function:
Function:
Function:
0
0-1
0-3
1- 3
Offset:
Offset:
Offset:
Offset:
Attr
Default
Description
15:9
RV
0h
Reserved
RO
1b
RO
0b
6:4
RW
000b
3:1
RO
001b
MSIMSGCTL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.37
Device:
Device:
Device:
Device:
0
1
2
3
Function:
Function:
Function:
Function:
0
0-1
0-3
1- 3
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RW
0b
MSI Enable
Software sets this bit to select INTx style interrupt or MSI interrupt for root port
generated interrupts.
0: INTx interrupt mechanism is used for root port interrupts, provided the
override bits in Section 3.2.5.88, MISCCTRLSTS: Misc. Control and Status on
page 89) allow it.
1: MSI interrupt mechanism is used for root port interrupts, provided the override
bits in MISCCTRLSTS allow it.
Note there bits 4:2 and bit 2 MISCCTRLSTS can disable both MSI and INTx
interrupt from being generated on root port interrupt events.
MSIMSGCTL
Bus: 0
Device: 3
Function: 0
Bit
Attr
Default
Description
15:9
RV
0h
Reserved
RO
1b
RO
0b
6:4
RW
000b
3:1
RO
001b
49
MSIMSGCTL
Bus: 0
3.2.5.38
Device: 3
Function: 0
Bit
Attr
Default
Description
RW
0b
MSI Enable
The software sets this bit to select platform-specific interrupts or transmit MSI
messages.
0: Disables MSI from being generated.
1: Enables the PCI Express port to use MSI messages for RAS, provided bit 4 in
MISCCTRLSTS is clear and also enables the Express port to use MSI messages for
PM and HP events at the root port provided these individual events are not
enabled for ACPI handling.
Note:
Software must disable INTx and MSI-X for this device when using MSI.
3.2.5.39
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
31:20
RW
000h
Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address. This field
is R/W for compatibility reasons only.
19:2
RW
00000h
Address ID
The definition of this field depends on whether interrupt remapping is enabled or
disabled.
1:0
RV
0h
Reserved
MSGDAT
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
50
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
31:16
RV
0000h
Reserved
15:0
RW
0000h
Data
The definition of this field depends on whether interrupt remapping is enabled or
disabled.
3.2.5.40
MSIMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
3.2.5.41
Device:
Device:
Device:
Device:
Device:
Attr
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Default
Offset:
Offset:
Offset:
Offset:
Offset:
Description
31:2
RV
0h
Reserved
1:0
RW
0h
Mask Bits
Relevant only when MSI is enabled and used for interrupts generated by the root
port. For each Mask bit that is set, the PCI Express port is prohibited from sending
the associated message. When only one message is allocated to the root port by
software, only mask bit 0 is relevant and used by hardware.
MSIPENDING
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
3.2.5.42
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Attr
Default
Description
31:2
RV
0h
Reserved
1:0
RO-V
0h
Pending Bits
Relevant only when MSI is enabled and used for interrupts generated by the root
port. When MSI is not enabled or used by the root port, this register always reads
a value 0. For each Pending bit that is set, the PCI Express port has a pending
associated message. When only one message is allocated to the root port by
software, only pending bit 0 is set/cleared by hardware and pending bit 1 always
reads 0.
Hardware sets this bit whenever it has an interrupt pending to be sent. This bit
remains set till either the interrupt is sent by hardware or the status bits
associated with the interrupt condition are cleared by software.
PXPCAPID
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
7:0
RO
10h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
90h
90h
90h
90h (PCIe Root Port Mode)
90h
Description
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
51
3.2.5.43
PXPNXTPTR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.44
Bit
Attr
Default
7:0
RO
E0h
0
1
2
3
Function:
Function:
Function:
Function:
0
0-1
0-3
1-3
Offset:
Offset:
Offset:
Offset:
91h
91h
91h
91h
Description
Next Ptr
This field is set to the PCI PM capability.
PXPCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
52
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
92h
92h
92h
92h (PCIe Root Port Mode)
92h
Bit
Attr
Default
Description
15:14
RV
0h
13:9
RO
00h
RW-O
0b
Slot Implemented
Applies only to the root ports.
1: indicates that the PCI Express link associated with the port is connected to a
slot.
0: indicates no slot is connected to this port.
Notes:
This register bit is of typwrite once and is set by BIOS.
When the Bus 0, Device 3, Function 0 is configured in NTB mode, set it to 0 as no
slot connection.
7:4
RO
4h
Device/Port Type
This field identifies the type of device. It is set to 4h for all the Express ports.
1) Configured in PCIe root mode: 4h.
Note: When Bus 0, Device 3, Function 0 is configured in NTB mode, its type
value is 0, which indicates a PCI Express endpoint. Please refer to
Section 3.3, Non Transparent Bridge Registers .
3:0
RW-O
2h
Capability Version
This field identifies the version of the PCI Express capability structure, which is 2h
as of now. This register field is left as RW-O to cover any unknowns with PCIe 3.0.
Reserved
3.2.5.45
DEVCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
3.2.5.46
Device:
Device:
Device:
Device:
Device:
Attr
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Default
94h
94h
94h
94h (PCIe Root Port Mode)
94h
Description
31:28
RV
0h
Reserved
27:26
RO
0h
25:18
RO
00h
17:16
RV
0h
Reserved
15
RO
1b
14
RO
0b
13
RO
0b
12
RO
0b
11:9
RO
000b
8:6
RO
000b
Reserved
RO
0b
4:3
RO
0h
2:0
RO
0h
DEVCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
Device:
Device:
Device:
Device:
Device:
Device:
Attr
0
0
1
2
3
3
Default
15
RV
0h
14:12
RO
000b
11
RO
0b
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Reserved
Max_Read_Request_Size
PCI Express/DMI ports in Processor do not generate requests greater than 64B
and this field is RO.
Enable No Snoop
Not applicable to DMI or PCIe root ports since they never set the No Snoop bit for
transactions they originate (not forwarded from peer) to PCI Express/DMI. This bit
has no impact on forwarding of NoSnoop attribute on peer requests.
53
DEVCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
54
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
10
RO
0b
RO
0b
RO
0h
7:5
RW
000b
RO
0b
RW
0b
RW
0b
RW
0b
DEVCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.47
Device:
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
RW
0b
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Correctable Error Reporting Enable
Controls the reporting of correctable errors that IIO detects on the PCI Express/
DMI interface
0: Reporting of link Correctable error detected by the port is disabled
1: Reporting of link Correctable error detected by port is enabled
Refer to PCI Express Base Specification, Revision 2.0 for complete details of how
this bit is used in conjunction with other bits to report errors.
This bit is not used to control the reporting of other internal component
correctable errors (at the port unit) in any way.
DEVSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
Device:
Device:
Device:
Device:
Device:
Device:
Attr
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Default
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Description
15:6
RV
0h
Reserved
RO
0h
Transactions Pending
Does not apply to Root/DMI ports, that is, bit hardwired to 0 for these devices.
RO
0b
RW1C
0b
RW1C
0b
RW1C
0b
55
DEVSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.48
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RW1C
0b
56
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
31:24
RW-O
0h
Port Number
This field indicates the PCI Express port number for the link and is initialized by
software/BIOS. IIO hardware does nothing with this bit.
23:22
RV
0h
Reserved
21
RO-V
1b
20
RO
1b
19
RO
1b
18
RO
0b
17:15
RW-O
010b
L1 Exit Latency
This field indicates the L1 exit latency for the given PCI Express port. It indicates
the length of time this port requires to complete transition from L1 to L0.
000: Less than 1us
001: 1 us to less than 2 us
010: 2 us to less than 4 us
011: 4 us to less than 8 us
100: 8 us to less than 16 us
101: 16 us to less than 32 us
110: 32 us to 64 us
111: More than 64 us
This register is made writable once by BIOS so that the value is settable.
LNKCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.49
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
14:12
RW-O
011b
11:10
RW-O
11b
9:4
RW-O
100b
3:0
RW-O
0011b/
0010b
57
LNKCON
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
58
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15:12
RV
0h
Reserved
11
RW
0b
10
RW
0b
RW
0b
RO
0b
RW
0b
Extended Synch
This bit when set forces the transmission of additional ordered sets when exiting
L0s and when in recovery. See PCI Express Base Specification, Revision 2.0 for
details.
RW
0b
WO
0b
Retrain Link
A write of 1 to this bit initiates link retraining in the given PCI Express/DMI port by
directing the LTSSM to the recovery state if the current state is [L0 or L1]. If the
current state is anything other than L0, L1 then a write to this bit does nothing.
This bit always returns 0 when read.It is permitted to write 1b to this bit while
simultaneously writing modified values to other fields in this register. If the LTSSM
is not already in Recovery or Configuration, the resulting Link training must use
the modified values. If the LTSSM is already in Recovery or Configuration, the
modified values are not required to affect the Link training that's already in
progress.
LNKCON
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.50
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RW
0b
Link Disable
This field controls whether the link associated with the PCI Express/DMI port is
enabled or disabled. When this bit is a 1, a previously configured link would return
to the disabled state as defined in the PCI Express Base Specification, Revision
2.0. When this bit is clear, an LTSSM in the disabled state goes back to the detect
state.
0: Enables the link associated with the PCI Express port
1: Disables the link associated with the PCI Express port
RO
0b
RV
0h
Reserved
1:0
RW-V
00b
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15
RW1C
0b
14
RW1C
0b
13
RO-V
0b
59
LNKSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.51
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
12
RW-O
1b
11
RO-V
0b
Link Training
This field indicates the status of an ongoing link training session in the PCI Express
port
0: LTSSM has exited the recovery/configuration state.
1: LTSSM is in recovery/configuration state or the Retrain Link was set but training
has not yet begun.
The IIO hardware clears this bit once LTSSM has exited the recovery/configuration
state. Refer to PCI Express Base Specification, Revision 2.0 for details of which
states within the LTSSM would set this bit and which states would clear this bit.
10
RO
0b
Reserved
9:4
RO-V
00h
3:0
RO-V
1h
60
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:19
RW-O
0h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Description
Physical Slot Number
This field indicates the physical slot number of the slot connected to the PCI
Express port and is initialized by BIOS.
SLTCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
18
RO
0b
17
RW-O
0b
16:15
RW-O
0b
14:7
RW-O
00h
RW-O
0b
Hot-plug Capable
This field defines hot-plug support capabilities for the PCI Express port.
0: indicates that this slot is not capable of supporting hot-plug operations.
1: indicates that this slot is capable of supporting hot-plug operations
This bit is programed by BIOS based on the system design. This bit must be
programmed by BIOS to be consistent with the VPP enable bit for the port.
RW-O
0b
Hot-plug Surprise
This field indicates that a device in this slot may be removed from the system
without prior notification. This field is initialized by BIOS.
0: indicates that hot-plug surprise is not supported
1: indicates that hot-plug surprise is supported
Generally this bit is not expected to be set because the only know usage case for
this is the ExpressCard FF. But that is not really expected usage in Processor
context. But this bit is present regardless to allow a usage if it arises.
This bit is used by IIO hardware to determine if a transition from DL_Active to
DL_Inactive is to be treated as a surprise down error or not. If a port is associated
with a hot-pluggable slot and the hot-plug surprise bit is set, then any transition
to DL_Inactive is not considered an error. Refer to PCI Express Base Specification,
Revision 2.0 for further details.
61
SLTCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.52
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RW-O
0b
RW-O
0b
RW-O
0b
RW-O
0b
RW-O
0b
62
SLTCON
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15:13
RV
0h
Reserved
12
RWS
0b
11
RW
0b
10
RWS
1b
9:8
RW
3h
7:6
RW
3h
RW
0b
63
SLTCON
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.53
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RW
0b
RW
0h
RW
0h
RW
0h
RW
0h
64
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15:9
RV
0h
Reserved
RW1C
0b
SLTSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RO
0b
RO
0b
RO
0b
RW1C
0b
Command Completed
This bit is set by IIO when the hot-plug command has completed and the hot-plug
controller is ready to accept a subsequent command. It is subsequently cleared by
software after the field has been read and processed. This bit provides no
guarantee that the action corresponding to the command is complete.Any write to
PCI Express Slot Control Register (SLTCON) (regardless of the port is capable or
enabled for hot-plug) is considered a hot-plug command.
If the port is not hot-plug capable or hot-plug enabled, then the hot-plug
command does not trigger any action on the VPP port but the command is still
completed via this bit.
RW1C
0b
RW1C
0b
RW1C
0b
RW1C
0b
65
3.2.5.54
66
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
ACh
ACh
ACh
ACh (PCIe Root Port Mode)
ACh
Bit
Attr
Default
Description
15:5
RV
0h
Reserved
RW
0b
RW
0b
RW
0b
RW
0b
ROOTCON
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.55
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
ACh
ACh
ACh
ACh (PCIe Root Port Mode)
ACh
Bit
Attr
Default
Description
RW
0b
ROOTCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.56
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
15:1
RV
0h
Reserved
RO
1b
ROOTSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
31:18
RV
0h
Reserved
17
RO-V
0b
PME Pending
This field indicates that another PME is pending when the PME Status bit is set.
When the PME Status bit is cleared by software; the pending PME is delivered by
hardware by setting the PME Status bit again and updating the Requestor ID
appropriately. The PME pending bit is cleared by hardware if no more PMEs are
pending.
67
ROOTSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.57
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
16
RW1C
0b
PME Status
This field indicates a PM_PME message (either from the link or internally from
within that root port) was received at the port.1: PME was asserted by a requester
as indicated by the PME Requester ID field
This bit is cleared by software by writing a 1. Note that the root port itself could
be the source of a PME event when a hot-plug event is observed when the port is
in D3hot state.
15:0
RO-V
0000h
PME Requester ID
This field indicates the PCI requester ID of the last PME requestor. If the root port
itself was the source of the (virtual) PME message, then a RequesterID of
CPUBUSNO0:DevNo:FunctionNo is logged in this field.
DEVCAP2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
68
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
B4h
B4h
B4h
B4h (PCIe Root Port Mode)
B4h
Bit
Attr
Default
Description
31:14
RV
0h
13:12
RW-O
01b
11
RW-O
0b
10
RO
0b
RW-O
0b
RW-O
0b
RW-O
0b
RO
0b
Reserved
TPH Completer Supported
Indicates the support for TLP Processing Hints. Processor does not support the
extended TPH header.
00: TPH and Extended TPH Completer not supported.
01: TPH Completer supported; Extended TPH Completer not supported.
10: Reserved.
11: Both TPH and Extended TPH Completer supported.
DEVCAP2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.58
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
B4h
B4h
B4h
B4h (PCIe Root Port Mode)
B4h
Bit
Attr
Default
Description
RW-O
1b
RO
1b
3:0
RO
Eh
DEVCTRL2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Attr
Default
Description
15:6
RV
0h
Reserved
RO
0b
RW
69
DEVCTRL2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.59
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
3:0
RW
0h
LNKCAP2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
70
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Attr
0
1
2
3
3
Default
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
BCh
BCh
BCh
BCh (PCIe Root Port Mode)
BCh
Description
31:8
RV
0h
Reserved
7:1
RW-O
3h
RV
0h
Reserved
3.2.5.60
LNKCON2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Attr
Default
Description
15:13
RO
0b
12
RWS
0b
15:12
RWS
0000b
11
RWS
0b
Compliance SOS
When set to 1b, the LTSSM is required to send SKP Ordered Sets periodically in
between the (modified) compliance patterns.
10
RWS
0b
9:7
RWS-V
000b
RW-O
0b
Transmit Margin
This field controls the value of the nondeemphasized voltage level at the
Transmitter pins.
Selectable De-emphasis
When the Link is operating at 5.0 GT/s speed, this bit selects the level of deemphasis for an Upstream component.Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, the setting of this bit has no effect.
71
LNKCON2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.61
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
RWS
0b
RWS-V
0b
Enter Compliance
Software is permitted to force a link to enter Compliance mode at the speed
indicated in the Target Link Speed field by setting this bit to 1b in both
components on a link and then initiating a hot reset on the link.
3:0
RWS-V
2b
3:0
RWS-V
3b
Description
LNKSTS2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
72
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Attr
Default
Description
15:6
RV
0h
Reserved
RW1CS
0b
RO-V
0b
LNKSTS2
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.62
Device:
Device:
Device:
Device:
Device:
Device:
0
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
Function:
0
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
RO-V
0b
RO-V
0b
RO-V
0b
Equalization Complete
When set to 1b, this indicates that the Transmitter Equalization procedure has
completed.
RO-V
0b
software compliance.
PMCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
E0h
E0h
E0h
E0h (PCIe Root Port Mode)
E0h
Bit
Attr
Default
Description
31:27
RO-V
0h
PME Support
Indicates the PM states within which the function is capable of sending a PME
message.NTB secondary side does not forward PME messages.
In PCIe Mode, Bits 31, 30 and 27 must be set to \q1\q for PCI-PCI bridge
structures representing ports on root complexes. In DMI mode, PME generation is
not supported.
Bit 31 = D3cold
Bit 30 = D3hot
Bit 29 = D2
Bit 28 = D1
Bit 27 = D0
26
RO
0b
D2 Support
IIO does not support power management state D2.
25
RO
0b
D1 Support
IIO does not support power management state D1.
24:22
RO
000b
21
RO
0b
20
RV
0h
Reserved
AUX Current
Device does not support auxiliary current
73
PMCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.63
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
E0h
E0h
E0h
E0h (PCIe Root Port Mode)
E0h
Bit
Attr
Default
Description
19
RO
0b
18:16
RO
011b
15:8
RO
00h
7:0
RO
01h
Capability ID
Provides the PM capability ID assigned by PCI-SIG.
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
Version
This field is set to 3h (PM 1.2 compliant) as version number for all PCI Express
ports.
74
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
E4h
E4h
E4h
E4h (PCIe Root Port Mode)
E4h
Bit
Attr
Default
Description
31:24
RO
00h
23
RO
0h
22
RO
0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
21:16
RV
0h
Reserved
15
RW1CS
0h
PME Status
Applies only to RPs. This PME Status is a sticky bit. This bit is set, independent of
the PMEEN bit defined below, on an enabled PCI Express hotplug event provided
the RP was in D3hot state. Software clears this bit by writing a '1' when it has
been completed. Refer to PCI Express Base Specification, Revision 2.0 for further
details on wake event generation at a RP.
14:13
RO
0h
Data Scale
Not relevant for IIO
12:9
RO
0h
Data Select
Not relevant for IIO
RWS
0h
PME Enable
Applies only to root ports. This field is a sticky bit and when set, enables a virtual
PM_PME message to be generated internally on an enabled PCI Express hotplug
event. This virtual PM_PME message then sets the appropriate bits in the
ROOTSTS register (which can then trigger an MSI/INT or cause a _PMEGPE
event).
0: Disable ability to send PME messages when an event occurs
1: Enables ability to send PME messages when an event occurs
7:4
RV
0h
Reserved
Data
Not relevant for IIO
PMCSR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.64
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
E4h
E4h
E4h
E4h (PCIe Root Port Mode)
E4h
Bit
Attr
Default
Description
RW-O
1b
Indicates IIO does not reset its registers when it transitions from D3hot
to D0
RV
0h
Reserved
1:0
RW
0h
Power State
This 2-bit field is used to determine the current power state of the function and to
set a new power state as well. 00: D0
01: D1 (not supported by IIO)
10: D2 (not supported by IIO)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not change
from the existing power state (which is either D0 or D3hot) and nor do these
bits1:0 change value.
All devices will respond to only Type 0 configuration transactions when in D3hot
state (RP will not forward Type 1 accesses to the downstream link) and will not
respond to memory/IO transactions (that is, D3hot state is equivalent to MSE/
IOSE bits being clear) as target and will not generate any memory/IO/
configuration transactions as initiator on the primary bus (messages are still
allowed to pass through).
XPREUT_HDR_EXT
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
31:20
RO
110h
19:16
RO
1h
PcieCapVersion
Capability Version: This field is a PCI-SIG defined version number that indicates
the nature and format of the extended capability. This indicates the version of the
REUT Capability.
15:0
RO
Bh
PcieCapID
PCIe Extended CapID: This field has the value 0Bh to identify the CAP_ID
assigned by the PCI SIG indicating a vendor specific capability.
PcieNextPtr
Next Capability Pointer This field contains the offset to the next PCI capability
structure or 00h if no other items exist in the linked list of capabilities.
In DMI Mode, it points to the Vendor Specific Error Capability.
In PCIe Mode, it points to the ACS Capability.
75
3.2.5.65
XPREUT_HDR_EXT
Bus: 0
Device: 0
3.2.5.66
Attr
Default
Description
31:20
RO-V
144h
19:16
RO
1h
PcieCapVersion
Capability Version: This field is a PCI-SIG defined version number that indicates
the nature and format of the extended capability. This indicates the version of the
REUT Capability.
15:0
RO
Bh
PcieCapID
PCIe Extended CapID: This field has the value 0Bh to identify the CAP_ID
assigned by the PCI SIG indicating a vendor specific capability.
PcieNextPtr
Next Capability Pointer This field contains the offset to the next PCI capability
structure or 00h if no other items exist in the linked list of capabilities.
In DMI Mode, it points to the Vendor Specific Error Capability
In PCIe Mode, it points to the ACS Capability.
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
104h
104h
104h
104h (PCIe Root Port Mode)
104h
Bit
Attr
Default
Description
31:20
RO
Ch
VSECLength
VSEC Length This field defines the length of the REUT capability body. The size of
the leaf body is 12 bytes including the _EXT, _CAP and _LEF registers.
19:16
RO
0h
VSECIDRev
REUT VSECID Rev This field is defined as the version number that indicates the
nature and format of the VSEC structure. Software must quality the Vendor ID
before interpreting this field.
15:0
RO
0002h
VSECID
REUT Engine VSECID This field is a Intel-defined ID number that indicates the
nature and format of the VSEC structure. Software must qualify the Vendor ID
before interpreting this field.
Notes:
A value of 00h is reserved
A value of 01h is the ID Council defined for REUT engines.
A value of 02h is specified for the REUT leaf capability structure which resides in
each link which in supported by a REUT engine.
XPREUT_HDR_LEF
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
76
Bit
XPREUT_HDR_CAP
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
3.2.5.67
Function: 0
Bit
Attr
Default
31:16
RV
0h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
108h
108h
108h
108h (PCIe Root Port Mode)
108h
Description
Reserved
XPREUT_HDR_LEF
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
3.2.5.68
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
108h
108h
108h
108h (PCIe Root Port Mode)
108h
Bit
Attr
Default
Description
15:8
RO
30h
LeafReutDevNum
This field identifies the PCI Device/Function # where the REUT engine associated
with this link resides.
Device6 & function0 = 30h
Device6 & function1 = 31h
Device6 & function3 = 33h
Device7 & function0 = 38h
7:0
RO
2h
LeafReutEngID
This field identifies the REUT engine associated with the link (same as the REUT
ID).
ACSCAPHDR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.69
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:20
RO
148h
19:16
RO
1h
15:0
RO
000Dh
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
110h(PCIe MODE)
110h
110h
110h (PCIe Root Port Mode)
110h
Description
Next Capability Offset
This field points to the next Capability in extended configuration space.
In PCIe Mode, it points to the Advanced Error Capability.
Capability Version
Set to 1h for this version of the PCI Express logic
PCI Express Extended CAP ID
Assigned for Access Control Services capability by PCISIG.
ACSCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Bit
Attr
Default
15:8
RO
0h
Offset:
Offset:
Offset:
Offset:
Offset:
114h(PCIe MODE)
114h
114h
114h (PCIe Root Port Mode)
114h
Description
RV
0b
Reserved
RO
0b
RO
0b
77
ACSCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.70
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
114h(PCIe MODE)
114h
114h
114h (PCIe Root Port Mode)
114h
Bit
Attr
Default
RO
1b
RO
1b
RO
1b
RO
1b
RO
1b
Description
ACSCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
78
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
116h(PCIe MODE)
116h
116h
116h (PCIe Root Port Mode)
116h
Attr
Default
Description
15:7
RV
0h
Reserved
RO
0b
RO
0b
RW
0b
RW
0b
RW
0b
RW
0b
ACSCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.71
Device:
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
116h(PCIe MODE)
116h
116h
116h (PCIe Root Port Mode)
116h
Bit
Attr
Default
Description
RW
0b
APICBASE
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
3.2.5.72
0
1
2
3
3
Attr
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Default
15:12
RV
0h
11:1
RW
000h
RW
0h
Offset:
Offset:
Offset:
Offset:
Offset:
140h
140h
140h
140h (PCIe Root Port Mode)
140h
Description
Reserved
Bits 19:9 of the APIC base Applies only to root ports.
Bits 31:20 are assumed to be 0xFECh. Bits 8:0 are a dont care for address
decode. Address decoding to the APIC range is done as APICBASE.ADDR[31:8]
<= A[31:8] <= APICLIMIT.ADDR[31:8].
Outbound accesses to the APIC range are claimed by the root port and forwarded
to PCIe, if bit 0 is set, even if the MSE bit of the root port is clear or the root port
itself is in D3hot state.
APIC range enable
enables the decode of the APIC window
APICLIMIT
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
15:12
RV
0h
11:1
RW
000h
RV
0h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
142h
142h
142h
142h (PCIe Root Port Mode)
142h
Description
Reserved
Bits 19:9 of the APIC limit
Applies only to root ports.
Bits 31:20 are assumed to be 0xFECh. Bits 8:0 are a dont care for address
decode. Address decoding to the APIC range is done as APICBASE.ADDR[31:8]
<= A[31:8] <= APICLIMIT.ADDR[31:8].
Outbound accesses to the APIC range are claimed by the root port and forwarded
to PCIe, if the range is enabled, even if the MSE bit of the root port is clear or the
root port itself is in D3hot state.
Reserved
79
3.2.5.73
VSECHDR
Bus: 0
3.2.5.74
Offset: 144h
Attr
Default
Description
31:20
RO
1D0h
19:16
RO
1h
15:0
RO
000Bh
Capability Version
Set to 1h for this version of the PCI Express logic
PCI Express Extended CAP ID
Assigned for Vendor Specific Capability
Device: 0
Function: 0
Offset: 148h
Bit
Attr
Default
31:20
RO
3Ch
19:16
RO
1h
VSEC Version
Set to 1h for this version of the PCI Express logic
15:0
RO
4h
VSEC ID
Identifies Intel Vendor Specific Capability for AER on DMI
Description
VSEC Length
This field points to the next Capability in extended configuration space which is
the ACS capability at 150h.
VSHDR
Bus: 0
80
Function: 0
Bit
VSHDR
Bus: 0
3.2.5.75
Device: 0
Device: 3
Function: 0
Offset: 148h
Bit
Attr
Default
Description
31:20
RO
3Ch
VSEC Length
This field indicates the number of bytes in the entire VSEC structure, including the
PCI Express Enhanced Capability header, the Vendor-Specific header, and the
Vendor-Specific Registers.
19:16
RO
1h
VSEC Version
Set to 1h for this version of the PCI Express logic
15:0
RO
4h
VSEC ID
Identifies Intel Vendor Specific Capability for AER on NTB
3.2.5.76
ERRCAPHDR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.77
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
Description
31:20
RO
1D0h
19:16
RO
1h
15:0
RO
0001h
Capability Version
Set to 1h for this version of the PCI Express logic
PCI Express Extended CAP ID
Assigned for advanced error reporting
3.2.5.78
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
31:22
RV
0h
Reserved
21
RW1CS
0b
20
RW1CS
0b
19
RV
0h
Reserved
18
RW1CS
0b
17
RW1CS
0b
16
RW1CS
0b
15
RW1CS
0b
14
RW1CS
0b
13
RW1CS
0b
12
RW1CS
0b
14Ch
14Ch
14Ch
14Ch (PCIe Root Port Mode)
14Ch
Description
11:6
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
3:0
RV
0h
Reserved
81
UNCERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.79
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
31:22
RV
0h
Reserved
21
RWS
0b
20
RWS
0b
19
RV
0h
Reserved
18
RWS
0b
17
RWS
0b
16
RWS
0b
15
RWS
0b
14
RWS
0b
13
RWS
0b
12
RWS
0b
11:6
RV
0h
Reserved
RWS
0b
RWS
0b
3:0
RV
0h
Reserved
150h
150h
150h
150h (PCIe Root Port Mode)
150h
Description
82
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Attr
Default
31:22
RV
0h
Reserved
21
RWS
0b
20
RWS
0b
19
RV
0h
Reserved
18
RWS
1b
17
RWS
1b
16
RWS
0b
15
RWS
0b
14
RWS
0b
13
RWS
1b
154h
154h
154h
154h (PCIe Root Port Mode)
154h
Description
12
RWS
0b
11:6
RV
0h
Reserved
RWS
1b
UNCERRSEV
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.80
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
RWS
1b
3:0
RV
0h
Reserved
154h
154h
154h
154h (PCIe Root Port Mode)
154h
Description
3.2.5.81
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Attr
Default
31:14
RV
0h
Reserved
13
RW1CS
0b
158h
158h
158h
158h (PCIe Root Port Mode)
158h
Description
12
RW1CS
0b
11:9
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
5:1
RV
0h
Reserved
RW1CS
0b
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
31:14
RV
0h
Reserved
13
RWS
1b
12
RWS
0b
15Ch
15Ch
15Ch
15Ch (PCIe Root Port Mode)
15Ch
Description
11:9
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
5:1
RV
0h
Reserved
83
CORERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.82
Bit
Attr
Default
RWS
0b
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
15Ch
15Ch
15Ch
15Ch (PCIe Root Port Mode)
15Ch
Description
Receiver Error Mask
ERRCAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.83
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
160h
160h
160h
160h (PCIe Root Port Mode)
160h
Bit
Attr
Default
Description
31:9
RV
0h
Reserved
RO
0b
RO
0b
RO
0b
RO
0b
4:0
ROS-V
0h
3.2.5.84
Device:
Device:
Device:
Device:
0
1
2
3
Device: 3
Bit
Attr
Default
31:0
ROS-V
000000
00h
Function:
Function:
Function:
Function:
0
0-1
0-3
0
Function: 1-3
Offset:
Offset:
Offset:
Offset:
84
RPERRCMD
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.85
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
174h
174h
174h
174h (PCIe Root Port Mode)
174h
Bit
Attr
Default
Description
31:3
RV
0h
Reserved
RW
0b
RW
0b
RW
0b
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
178h
178h
178h
178h (PCIe Root Port Mode)
178h
Bit
Attr
Default
Description
31:27
RO
0h
26:7
RO
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
85
RPERRSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.86
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
178h
178h
178h
178h (PCIe Root Port Mode)
178h
Attr
Default
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
Description
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
17Ch
17Ch
17Ch
17Ch (PCIe Root Port Mode)
17Ch
Bit
Attr
Default
31:16
ROS-V
0h
15:0
ROS-V
0h
Description
PERFCTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
86
0
1
2
3
3
Bit
ERRSID
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.5.87
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
180h
180h
180h
180h (PCIe Root Port Mode)
180h
Bit
Attr
Default
Description
63:42
RV
0h
Reserved
41
RW
0b
PERFCTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
180h
180h
180h
180h (PCIe Root Port Mode)
180h
Bit
Attr
Default
40
RW
0b
39:36
RV
0h
Reserved
35
RW
0b
34:21
RV
0h
20:16
RW
18h
15:14
RV
0h
13:8
RW
30h
Description
87
PERFCTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
RW
1b
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
180h
180h
180h
180h (PCIe Root Port Mode)
180h
Description
Use Allocating Flows for Normal Writes on VC0 and VCp
1: Use allocating flows for the writes that meet the following criteria.
0: Use non-allocating flows for writes that meet the following criteria.
(TPH=0 OR TPHDIS=1 OR (TPH=1 AND Tag=0 AND CIPCTRL[28]=1)) AND
(NS=0 OR NoSnoopOpWrEn=0) AND
Non-DCA Write
Notes:
VC1/VCm traffic is not impacted by this bit in Dev#0
When allocating flows are used for the above write types, IIO does not send a
Prefetch Hint message.
Current recommendation for BIOS is to just leave this bit at default of 1b for all
but DMI port. For DMI port when operating in DMI mode, this bit must be left at
default value and when operating in PCIe mode, this bit should be set by BIOS.
Note there is a coupling between the usage of this bit and bits 2 and 3.
TPHDIS is bit 0 of this register
NoSnoopOpWrEn is bit 3 of this register
88
RW
1b
RW
0b
RW
0b
RW
0b
RW
1b
3.2.5.88
MISCCTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
Attr
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Default
Offset:
Offset:
Offset:
Offset:
Offset:
188h
188h
188h
188h (PCIe Root Port Mode)
188h
Description
63:52
RV
0h
Reserved
51
RW
1b
50
RW
0b
49
RW1CS
0b
48
RW1C
0b
Received PME_TO_ACK
Indicates that IIO received a PME turn off ack packet or it timed out waiting for
the packet
47:42
RV
0h
Reserved
41
RW
0b
40:39
RV
0h
Reserved
38
RW
0b
37
RW
0b
36
RWS
0b
Form-Factor
Indicates what form-factor a particular root port controls
0 - CEM
1 - Express Module
This bit is used to interpret bit 6 in the VPP serial stream for the port as either
MRL# (CEM) input or EMLSTS# (Express Module) input.
35
RW
0b
89
MISCCTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
90
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
188h
188h
188h
188h (PCIe Root Port Mode)
188h
Bit
Attr
Default
Description
34
RW
0b
33
RW
0b
32
RW
0b
31
RW
0b
Reserved
30
RW-O
1b
29
RW
1b
cfg_to_en
Disables/enables config timeouts, independently of other timeouts.
28
RW
0b
to_dis
Disables timeouts completely.
27
RWS
0b
26
RW
0b
25
RO
0b
24
RW
0b
23
RW
0b
Phold Disable
Applies only to Dev#0When set, the IIO responds with Unsupported request on
receiving assert_phold message from ICH and results in generating a fatal error.
22
RWS
0b
check_cpl_tc
MISCCTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
188h
188h
188h
188h (PCIe Root Port Mode)
188h
Bit
Attr
Default
Description
21
RW-O
0b
20
RW
1b
19
RV
0h
Reserved
18
RWS
0b
17
RO
0b
16
RO
0b
15
RWS
0b
dis_hdr_storage
14
RWS
0b
allow_one_np_os
13
RWS
0b
tlp_on_any_lane
12
RWS
1b
disable_ob_parity_check
11
RWS
1b
allow_1nonvc1_after_10vc1s
Allow a non-VC1 request from DMI to go after every ten VC1 request (to prevent
starvation of non-VC1).
Notes:
This bit has no effect if the port is in PCI Express mode.
10
RV
0h
Reserved
RWS
0b
dispdspolling
Disables gen2 if timeout happens in polling.cfg.
8:7
RW
0b
PME2ACKTOCTRL
RW
0b
RW-V
0b
91
MISCCTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
92
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
188h
188h
188h
188h (PCIe Root Port Mode)
188h
Bit
Attr
Default
Description
RW
0b
RW
0b
Enable_ACPI_mode_for_Hotplug
Applies only to root ports. For Dev#0 in DMI mode, this bit is to be left at default
value always.When this bit is set, all Hot-Plug events from the PCI Express port
are handled via _HPGPE messages to the ICH and no MSI/INTx messages are ever
generated for Hot Plug events (regardless of whether MSI or INTx is enabled at
the root port or not) at the root port. When this bit is clear, _HPGPE message
generation on behalf of root port Hot Plug events is disabled and OS can chose to
generate MSI or INTx interrupt for Hot Plug events, by setting the MSI enable bit
in the Section 3.3.5.22, MSICTRL: MSI Control on page 176 in root ports. This
bit does not apply to the DMI ports. Refer to PCI Express Base Specification,
Revision 2.0 and Chapter 10, 'PCI Express Hot Plug Interrupts,' for details of MSI
and GPE message generation for hotplug events. Clearing this bit (from being 1)
schedules a Deassert_HPGPE event on behalf of the root port, provided there was
any previous Assert_HPGPE message that was sent without an associated
Deassert message.
Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to
set it up appropriately in that mode.
RW
0b
Enable_ACPI_mode_for_PM
Applies only to root ports. For Dev#0 in DMI mode, this bit is to be left at default
value always.When this bit is set, all PM events at the PCI Express port are
handled via _PMEGPE messages to the ICH, and no MSI interrupts are ever
generated for PM events at the root port (regardless of whether MSI in the
Section 3.3.5.22, MSICTRL: MSI Control on page 176 is enabled at the root port
or not). When clear, _PMEGPE message generation for PM events is disabled and
OS can chose to generate MSI interrupts for delivering PM events by setting the
MSI enable bit in root ports. This bit does not apply to the DMI ports. Refer to PCI
Express Base Specification, Revision 2.0 and Chapter 19, 'Power Management,' for
details of MSI and GPE Clearing this bit (from being 1) schedules a
Deassert_PMEGPE event on behalf of the root port, provided there was any
previous Assert_PMEGPE message that was sent without an associated Deassert
message.
Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to
set it up appropriately in that mode.
RW-O
0b
3.2.5.89
PCIE_IOU_BIF_CTRL
Bus: 0
Device: 0
Bit
Attr
Function: 0
Default
Offset: 190h
Description
15:4
RV
0h
Reserved
WO
0b
2:0
3.2.5.90
RO
000b
DMICTR
Bus: 0
Device: 0
Offset: 1A0
Function: 0
Bit
Attr
Default
Description
63:2
RO
000000
000000
0000h
RW
1b
RW
1b
Reserved
93
3.2.5.91
PCIE_IOU_BIF_CTRL
Bus: 0
Device: 1
Bus: 0
Device: 2
Bus: 0
Device: 3
Bit
3.2.5.92
Function: 0
Function: 0
Function: 0
Offset: 190h
Offset: 190h
Offset: 190h (PCIe Root Port Mode)
Attr
Default
Description
15:4
RV
0h
Reserved
WO
0b
2:0
RWS
PXP2CAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
1
2
3
3
Function:
Function:
Function:
Function:
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
250h
250h
250h (PCIe Root Port Mode)
250h
Bit
Attr
Default
Description
31:20
RO
280h
19:16
RO
2h
15:0
RWO
0000h
Capability Version
This field is a PCI-SIG defined version number that indicates the version of the
Capability structure present. Must be 1h for this version of the specification.
PCI Express Extended Capability ID
This field is a PCI SIG defined ID number that indicates the nature and format of
the Extended Capability. PCI Express Extended Capability ID for the Secondary
PCI Express Extended Capability is 0019h.
Note:
BIOS is required to write 0019h.
94
3.2.5.93
LNKCON3
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
3.2.6
Attr
Device:
Device:
Device:
Device:
1
2
3
3
Function:
Function:
Function:
Function:
0-1
0-3
0
1-3
Default
Offset:
Offset:
Offset:
Offset:
254h
254h
254h (PCIe Root Port Mode)
254h
Description
31:2
RV
0h
Reserved
RW
0b
RW
0b
Perform Equalization
When this register is 1b and a 1b is written to the `Link Retrain register with
`Target Link Speed set to 8 GT/s, the Upstream component must perform
Transmitter Equalization.
3.2.6.1
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:20
RO
280h
19:16
RO
1h
15:0
RO
000Bh
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
1D0h
1D0h
1D0h
1D0h (PCIe Root Port Mode)
1D0h
Description
Next Capability Offset
This field points to the next capability or 0 if there isnt a next capability.
Capability Version
Set to 2h for this version of the PCI Express specification
PCI Express Extended Capability ID
Vendor Defined Capability
95
3.2.6.2
ERRINJHDR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.3
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:20
RO
00Ah
19:16
RO
1h
15:0
RO
0003h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
1D4h
1D4h
1D4h
1D4h (PCIe Root Port Mode)
1D4h
Description
Vendor Specific Capability Length
Indicates the length of the capability structure, including header bytes.
Vendor Specific Capability Revision
Set to 1h for this version of the WHEA Error Injection logic.
Vendor Specific ID
Assigned for WHEA Error Injection
ERRINJCON
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
1D8h
1D8h
1D8h
1D8h (PCIe Root Port Mode)
1D8h
Bit
Attr
Default
Description
15:3
RV
0h
Reserved
RW
0b
RW
0b
96
RW-O
0b
3.2.6.4
CTOCTRL
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
3.2.6.5
Device:
Device:
Device:
Device:
Device:
Attr
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Default
31:10
RV
0h
9:8
RW
00b
7:0
RV
0h
Offset:
Offset:
Offset:
Offset:
Offset:
1E0h
1E0h
1E0h
1E0h (PCIe Root Port Mode)
1E0h
Description
Reserved
XP-to-PCIe timeout select within 17 s to 64 s range
When OS selects a timeout range of 17s to 64s for XP (that affect NP tx issued to
the PCIe/DMI) using the root ports DEVCTRL2 register, this field selects the subrange within that larger range, for additional controllability.
00: 17s-30s
01: 31s-45s
10: 46s-64s
11: Reserved
Reserved
3.2.6.6
Attr
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Default
Offset:
Offset:
Offset:
Offset:
Offset:
200h
200h
200h
200h (PCIe Root Port Mode)
200h
Description
31:1
RV
0h
Reserved
RW1CS
0b
XPCORERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:1
RV
0h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
204h
204h
204h
204h (PCIe Root Port Mode)
204h
Description
Reserved
97
XPCORERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.7
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
204h
204h
204h
204h (PCIe Root Port Mode)
204h
Attr
Default
Description
RWS
0b
Bit
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
208h
208h
208h
208h (PCIe Root Port Mode)
208h
Attr
Default
31:10
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
Reserved7
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
Reserved2
RW1CS
0b
RW1CS
0b
Reserved0
Description
XPUNCERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
98
0
1
2
3
3
Bit
XPUNCERRSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.8
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
20Ch
20Ch
20Ch
20Ch (PCIe Root Port Mode)
20Ch
Bit
Attr
Default
Description
31:10
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
Reserved7
RWS
0b
RWS
0b
XPUNCERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.9
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
20Ch
20Ch
20Ch
20Ch (PCIe Root Port Mode)
20Ch
Bit
Attr
Default
RWS
0b
RWS
0b
RWS
0b
Reserved2
RWS
0b
RWS
0b
Reserved0
Description
XPUNCERRSEV
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.10
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
210h
210h
210h
210h (PCIe Root Port Mode)
210h
Bit
Attr
Default
Description
31:10
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
Reserved7
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
Reserved2
RWS
1b
RWS
0b
Reserved0
XPUNCERRPTR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
214h
214h
214h
214h (PCIe Root Port Mode)
214h
Bit
Attr
Default
Description
7:5
RV
0h
Reserved
4:0
ROS-V
0h
99
3.2.6.11
3.2.6.12
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
218h
218h
218h
218h (PCIe Root Port Mode)
218h
Attr
Default
Description
31:22
RV
0h
Reserved
21
RWS
0b
20
RWS
0b
19
RV
0h
Reserved
18
RWS
0b
17
RWS
0b
16
RWS
0b
15
RWS
0b
14
RWS
0b
13
RWS
0b
12
RWS
0b
11:6
RV
0h
Reserved
RWS
0b
RWS
0b
3:0
RV
0h
Reserved
100
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
1D0h
21Ch
21Ch
21Ch (PCIe Root Port Mode)
21Ch
Bit
Attr
Default
Description
31:14
RV
0h
Reserved
13
RWS
0b
12
RWS
0b
11:9
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
5:1
RV
0h
Reserved
RWS
0b
3.2.6.13
3.2.6.14
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
220h
220h
220h
220h (PCIe Root Port Mode)
220h
Bit
Attr
Default
Description
31:3
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
3.2.6.15
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
224h
224h
224h
224h (PCIe Root Port Mode)
224h
Bit
Attr
Default
Description
31:10
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
Reserved7
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
Reserved2
RWS
0b
RWS
0b
Reserved0
101
XPCOREDMASK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.16
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
228h
228h
228h
228h (PCIe Root Port Mode)
228h
Bit
Attr
Default
Description
31:1
RV
0h
Reserved
RWS
0b
3.2.6.17
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
230h
230h
230h
230h (PCIe Root Port Mode)
230h
Attr
Default
Description
15:3
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
102
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
15:3
RV
0h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
232h
232h
232h
232h (PCIe Root Port Mode)
232h
Description
Reserved
XPGLBERRPTR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.18
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
232h
232h
232h
232h (PCIe Root Port Mode)
232h
Bit
Attr
Default
Description
2:0
ROS-V
0b
LNERRSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bit
3.2.6.19
Device:
Device:
Device:
Device:
Device:
Attr
Device:
Device:
Device:
Device:
1
2
3
3
Function:
Function:
Function:
Function:
0-1
0-3
0
1-3
Default
31:16
RV
0h
15:0
RW1CS
0000h
Offset:
Offset:
Offset:
Offset:
258h
258h
258h (PCIe Root Port Mode)
258h
Description
Reserved
Lane Error Status
A value of 1b in any bit indicates if the corresponding PCIe Express Lane detected
lane based error.
Bit 0 Lane 0 Error Detected
Bit 1 Lane 1 Error Detected
Bit 2 Lane 2 Error Detected
Bit 3 Lane 3 Error Detected
Bit 4 Lane 4 Error Detected (not used when the link is bifurcated as x4)
Bit 5 Lane 5 Error Detected (not used when the link is bifurcated as x4)
Bit 6 Lane 6 Error Detected (not used when the link is bifurcated as x4)
Bit 7 Lane 7 Error Detected (not used when the link is bifurcated as x4)
Bit 8 Lane 8 Error Detected (not used when the link is bifurcated as x4 or x8)
Bit 9 Lane 9 Error Detected (not used when the link is bifurcated as x4 or x8)
Bit 10 Lane 10 Error Detected (not used when the link is bifurcated as x4 or x8)
Bit 11 Lane 11 Error Detected (not used when the link is bifurcated as x4 or x8)
Bit 12 Lane 12 Error Detected (not used when the link is bifurcated as x4 or x8)
Bit 13 Lane 13 Error Detected (not used when the link is bifurcated as x4 or x8)
Bit 14 Lane 14 Error Detected (not used when the link is bifurcated as x4 or x8)
Bit 15 Lane 15 Error Detected (not used when the link is bifurcated as x4 or x8)
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:20
RO
000h
19:16
RO
1h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
280h
280
280
280h (PCIe Root Port Mode)
280
Description
Next Capability Offset
Capability Version
103
LER_CAP
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.20
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
15:0
RO
000Bh
Bit
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
280h
280
280
280h (PCIe Root Port Mode)
280
Description
PCI Express Extended Capability ID
Vendor Specific Capability
Device:
Device:
Device:
Device:
Device:
Attr
Default
31:20
RO
018h
19:16
RO
2h
15:0
RO
0004h
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
284h
284
284
284h (PCIe Root Port Mode)
284
Description
VSEC Length
VSEC Revision ID
Vendor Specific ID
Represents the Live Error Recovery capability
LER_CTRLSTS
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.22
Function:
Function:
Function:
Function:
Function:
LER_HDR
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.21
0
1
2
3
3
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
288h
288
288
288h (PCIe Root Port Mode)
288
Bit
Attr
Default
Description
31
RW1CS
0b
30:1
RV
0h
Reserved
RWS
0b
104
LER_UNCERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
Bus: 0
3.2.6.23
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
31:22
RV
0h
Reserved
21
RWS
0b
20
RWS
0b
19
RV
0h
Reserved
18
RWS
0b
17
RWS
0b
16
RWS
0b
15
RWS
0b
14
RWS
0b
13
RWS
0b
12
RWS
0b
28Ch
28C
28C
28Ch (PCIe Root Port Mode)
28C
Description
11:6
RV
0h
Reserved
RWS
0b
RWS
0b
3:0
RV
0h
Reserved
LER_XPUNCERRMSK
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bus: 0
Device:
Bit
Attr
0
1
2
3
3
Default
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
290
290
290
290h (PCIe Root Port Mode)
290
Description
31:10
RV
0h
Reserved
RWS
0b
8:7
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
RWS
0b
2:0
RV
0h
Reserved
105
3.2.6.24
LER_RPERRMSK
Bus: 0
Bus: 0
Bus: 0
Bus: 0
:0
Bit
Device:
Device:
Device:
Device:
Device:
0
1
2
3
3
Function:
Function:
Function:
Function:
Function:
0
0-1
0-3
0
1-3
Offset:
Offset:
Offset:
Offset:
Offset:
294
294
294
294h (PCIe Root Port Mode)
294
Attr
Default
Description
31:7
RV
0h
Reserved
RWS
0b
RWS
0b
4:0
RV
0h
Reserved
3.2.7
3.2.7.1
LN[0:3]EQ
Bus: 0
Device: 1
Function: 0-1
Bus: 0
Device: 2
Function: 0-3
Bus: 0
Device: 3
Function: 0
Port Mode and NTB Primary End Device Mode)
Bus: 0
Device: 3
Function: 1-3
Bit
106
Attr
Default
15
RV
0h
Reserved
14:12
RW-O
2h
LN[0:3]EQ
Bus: 0
Device: 1
Function: 0-1
Bus: 0
Device: 2
Function: 0-3
Bus: 0
Device: 3
Function: 0
Port Mode and NTB Primary End Device Mode)
Bus: 0
Device: 3
Function: 1-3
Bit
Attr
Default
Description
11:8
RW-O
8h
RV
0h
Reserved
6:4
RO
7h
3:0
RW-O
8h
107
3.2.7.2
108
Attr
Default
15
RV
0h
Reserved
14:12
RW-O
2h
11:8
RW-O
8h
RV
0h
Reserved
6:4
RO
7h
LN[4:7]EQ
Bus: 0
Device: 1
Function: 0
Bus: 0
Device: 2
Function: 0, 2
Bus: 0
Device: 3
Function: 0
Port Mode and NTB Primary End Device Mode)
Bus: 0
Device: 3
Function: 2
3.2.7.3
Bit
Attr
Default
Description
3:0
RW-O
8h
Attr
Default
Description
15
RV
0h
Reserved
14:12
RW-O
2h
109
LN[8:15]EQ
Bus: 0
Device: 2
Function: 0
Offset: 26Ch, 26Eh, 270h, 272h, 274h,
276h, 278h, 27Ah
Bus: 0
Device: 3
Function: 0
Offset: 26Ch, 26Eh, 270h, 272h, 274h,
276h, 278h, 27Ah(PCIe Root Port Mode and NTB Primary End Device Mode)
110
Bit
Attr
Default
Description
11:8
RW-O
8h
RV
0h
Reserved
6:4
RO
7h
3:0
RW-O
8h
3.2.8
Table 3-7.
10h
90h
14h
94h
18h
98h
DMIVC1RCAP
1Ch
9Ch
DMIVC1RCTL
20h
A0h
DMIVC0RSTS
DMIVC1RSTS
24h
A4h
DMIVCPRCAP
28h
A8h
DMIVCPRCTL
2Ch
ACh
30h
B0h
DMIVCMRCAP
34h
B4h
DMIVCMRCTL
38h
B8h
DMIVCPRSTS
DMIVCMRSTS
3Ch
BCh
DMIRCLDECH
40h
C0h
DMIESD
44h
C4h
48h
C8h
4Ch
CCh
DMILED
50h
D0h
54h
D4h
DMILBA0
58h
D8h
5Ch
DCh
60h
E0h
DMIVCpCdtThrottle
64h
E4h
DMIVCmCdtThrottle
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
DMIVC1CdtThrottle
7Ch
FCh
80h
100h
84h
104h
88h
108h
8Ch
10Ch
111
3.2.8.1
DMIVC0RCAP
Bus: 0
Bit
3.2.8.2
Device: 0
Offset: 10h
Function: 0
Attr
Default
Description
31:16
RO
0000h
15
RO
0h
14:0
RV
0h
Reserved
3.2.8.3
Device: 0
Offset: 14h
Function: 0
Bit
Attr
Default
Description
31
RO
1b
30:27
RV
0h
Reserved
26:24
RO
0h
Virtual Channel 0 ID
Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read
only.
23:8
RV
0h
Reserved
RO
0b
6:1
RWLB
3Fh
RO
1b
112
Device: 0
Offset: 1Ah
Bit
Attr
Default
15:2
RV
0h
Function: 0
Description
Reserved
DMIVC0RSTS
Bus: 0
3.2.8.4
Function: 0
Bit
Attr
Default
Description
RO-V
1b
RV
0h
Reserved
DMIVC1RCAP
Bus: 0
3.2.8.5
Device: 0
Offset: 1Ah
Device: 0
Offset: 1Ch
Function: 0
Bit
Attr
Default
Description
31:16
RV
0h
Reserved
15
RO
1b
14:0
RV
0h
Reserved
Device: 0
Offset: 20h
Function: 0
Bit
Attr
Default
Description
31
RW-LB
0b
30:27
RV
0h
Reserved
113
DMIVC1RCTL
Bus: 0
3.2.8.6
Device: 0
Offset: 20h
Function: 0
Bit
Attr
Default
Description
26:24
RW-LB
001b
23:8
RV
0h
Reserved
RO
0b
6:1
RW-LB
00h
RO
0b
Virtual Channel 1 ID
Assigns a VC ID to the VC resource. Assigned value must be non-zero. This field
can not be modified when the VC is already enabled.
3.2.8.7
Function: 0
Bit
Attr
Default
15:2
RV
0h
Reserved
RO-V
1b
RV
0h
Reserved
Description
DMIVCPRCAP
Bus: 0
114
Device: 0
Offset: 26h
Device: 0
Offset: 28h
Function: 0
Bit
Attr
Default
Description
31:16
RV
0h
Reserved
15
RO
0b
14:0
RV
0h
Reserved
3.2.8.8
3.2.8.9
Device: 0
Offset: 2Ch
Function: 0
Bit
Attr
Default
Description
31
RW-LB
0b
30:27
RV
0h
Reserved
26:24
RW-LB
010b
23:8
RV
0h
Reserved
RO
0b
6:1
RW-LB
00h
RO
0b
Device: 0
Offset: 32h
Bit
Attr
Default
15:2
RV
0h
Function: 0
Description
Reserved
115
DMIVCPRSTS
Bus: N
3.2.8.10
Function: 0
Bit
Attr
Default
Description
RO-V
1b
RV
0h
Reserved
DMIVCMRCAP
Bus: 0
Bit
3.2.8.11
Device: 0
Offset: 32h
Device: 0
Offset: 34h
Function: 0
Attr
Default
Description
31:16
RV
0h
Reserved
15
RO
1b
14:0
RV
0h
Reserved
116
Device: 0
Offset: 38h
Function: 0
Bit
Attr
Default
Description
31
RW-LB
0b
30:27
RV
0h
Reserved
DMIVCMRCTL
Bus: 0
3.2.8.12
Device: 0
Offset: 38h
Bit
Attr
Default
26:24
RW-LB
000b
Function: 0
Description
VCm ID
23:8
RV
0h
Reserved
RO
1b
6:1
RO
0h
RO
0b
3.2.8.13
Device: 0
Offset: 3Eh
Function: 0
Bit
Attr
Default
Description
15:2
RV
0h
Reserved
RO-V
1b
RV
0h
Reserved
Device: 0
Offset: 40h
Bit
Attr
Default
31:20
RO
080h
19:16
RO
1h
15:0
RO
0005h
Function: 0
Description
Pointer to Next Capability
Capability Version
Indicates capability structure version
Extended Capability ID
Indicates Root Complex Link Declaration capability structure.
117
3.2.8.14
DMIESD
Bus: 0
Bit
3.2.8.15
Device: 0
Offset: 44h
Default
31:24
RO
01h
Port Number
23:16
RW-O
00h
Component ID
15:8
RO
01h
7:4
RV
0h
Reserved
3:0
RO
2h
Element Type
Indicates Internal Root Complex Link for DMI port
Description
Device: 0
Offset: 50h
Attr
Default
Description
31:24
RW-O
00h
23:16
RW-O
00h
Target Component ID
15:2
RV
0h
Reserved
RO
0b
Link Type
0: Link Points to Memory Mapped Space
1: Link Points to Configuration Space
RW-O
0b
Link Valid
Device: 0
Offset: 58h
Bit
Attr
Default
31:12
RW-O
00000h
11:0
RV
0h
Function: 0
Description
Link Address
Reserved
DMIVC1CdtThrottle
Bus: 0
Device: 0
Offset: 60h
118
Function: 0
Bit
DMILBA0
Bus: 0
3.2.8.17
Attr
DMILED
Bus: 0
3.2.8.16
Function: 0
Bit
Attr
Default
31:24
RWS
00h
23:22
RV
0h
21:16
RWS
00h
Function: 0
Description
Posted Request Data VC1 Credit Withhold
Number of VC1 Posted Data credits to withhold from being reported or used.
Reserved
Posted Request Header VC1 Credit Withhold
Number of VC1 Posted Request credits to withhold from being reported or used.
DMIVC1CdtThrottle
Bus: 0
Device: 0
Offset: 60h
3.2.8.18
Bit
Attr
Default
Description
15:8
RWS
00h
7:6
RV
0h
5:0
RWS
00h
Reserved
Non-Posted Request Header VC1 Credit Withhold
Number of VC1 Non-Posted Request credits to withhold from being reported or
used.
DMIVCpCdtThrottle
Bus: 0
Device: 0
Offset: 64h
3.2.8.19
Function: 0
Function: 0
Bit
Attr
Default
31:24
RWS
00h
23:22
RV
0h
21:16
RWS
00h
15:8
RWS
00h
7:6
RV
0h
5:0
RWS
00h
Description
Posted Request Data VCp Credit Withhold
Number of VCp Posted Data credits to withhold from being reported or used.
Reserved
Reserved
Non-Posted Request Header VCp Credit Withhold
Number of VCp Non-Posted Request credits to withhold from being reported or
used.
DMIVCmCdtThrottle
Bus: 0
Device: 0
Offset: 68h
Bit
Attr
Default
31:24
RWS
00h
Function: 0
Description
Posted Request Data VCm Credit Withhold
Number of VCm Posted Data credits to withhold from being reported or used.
23:22
RV
0h
21:16
RWS
00h
Reserved
Posted Request Header VCm Credit Withhold
Number of VCm Posted Request credits to withhold from being reported or used.
15:8
RWS
00h
7:6
RV
0h
5:0
RWS
00h
Reserved
Non-Posted Request Header VCm Credit Withhold
Number of VCm Non-Posted Request credits to withhold from being reported or
used.
119
3.3
3.3.1
Table 3-8.
DID
VID
0h
PCISTS
PCICMD
4h
TABLEOFF_BIR
RID
8h
PBAOFF_BIR
CLSR
Ch
CCR
BIST
HDR
PLAT
10h
PB01BASE
18h
PB45BASE
MAXLAT
SVID
MINGNT
INTPIN
PXPCAP
MSINXTPTR
120
84h
88h
PXPNXTPTR
PXPCAPID
DEVCAP
DEVSTS
90h
94h
DEVCTRL
98h
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
SBAR45SZ
SBAR23SZ
PBAR45SZ
54h
MSGADR
80h
1Ch
50h
MSIMSGCTL
MSIXCAPID
8Ch
14h
PB23BASE
SDID
MSIXMSGCTRL
MSICAPID
PBAR23SZ
D0h
PPD
D4h
58h
D8h
5Ch
DCh
60h
PMCAP
E0h
64h
PMCSR
E4h
MSGDAT
68h
E8h
MSIMSK
6Ch
ECh
MISIPENDING
70h
F0h
Table 3-8.
Table 3-9.
F4h
78h
F8h
7Ch
FCh
100h
XPREUT_HDR_CAP
104h
XPREUT_HDR_LEF
108h
ACSCAPHDR
110h
ACSCAP
184h
188h
MISCCTRLSTS
10Ch
ACSCTRL
180h
PERFCTRLSTS
18Ch
PCIE_IOU_BIF_CTRL
114h
194h
LNKCAP
19Ch
118h
198h
11Ch
120h
LNKSTS
LNKCON
124h
SLTCAP
128h
SLTSTS
SLTCON
1A8h
ROOTCAP
ROOTCON
1ACh
130h
ROOTSTS
1B0h
134h
DEVCAP2
1B4h
138h
APICBASE
VSECPHDR
1A0h
1A4h
12Ch
DEVCTRL2
13Ch
APICLIMIT
190h
NTBDEVCAP
140h
LNKCAP2
LNKSTS2
1B8h
1BCh
LNKCON2
144h
1C0h
1C4h
VSHDR
148h
1C8h
UNCERRSTS
14Ch
1CCh
UNCERRMSK
150h
ERRINJCAP
1D0h
UNCERRSEV
154h
ERRINJHDR
1D4h
CORERRSTS
158h
CORERRMSK
15Ch
ERRCAP
160h
HDRLOG0
164h
ERRINJCON
1D8h
1DCh
CTOCTRL
1E0h
1E4h
HDRLOG1
168h
1E8h
HDRLOG2
16Ch
1ECh
HDRLOG3
170h
1F0h
RPERRCMD
174h
1F4h
RPERRSTS
178h
1F8h
ERRSID
17Ch
1FCh
121
200h
LER_CAP
280h
XPCORERRMSK
204h
LER_HDR
284h
XPUNCERRSTS
208h
LER_CTRLSTS
288h
XPUNCERRMSK
20Ch
LER_UNCERRMSK
28Ch
210h
LER_XPUNCERRMSK
290h
214h
LER_RPERRMSK
294h
XPUNCERRSEV
XPUNCERR
PTR
UNCEDMASK
218h
298h
COREDMASK
21Ch
29Ch
RPEDMASK
220h
2A0h
XPUNCEDMASK
224h
2A4h
XPCOREDMASK
XPGLBERRPTR
XPGLBERRSTS
3.3.2
2A8h
2ACh
230h
2B0h
234h
2B4h
238h
2B8h
23Ch
2BCh
240h
2C0h
244h
2C4h
248h
2C8h
24Ch
2CCh
PXP2CAP
250h
2D0h
LNKCON3
254h
2D4h
LNERRSTS
LN1EQ
228h
22Ch
LN0EQ
258h
2D8h
25Ch
2DCh
LN3EQ
LN2EQ
260h
2E0h
LN5EQ
LN4EQ
264h
2E4h
LN7EQ
LN6EQ
268h
2E8h
LN9EQ
LN8EQ
26Ch
2ECh
LN11EQ
LN10EQ
270h
LN13EQ
LN12EQ
274h
LN15EQ
LN14EQ
XPPMDFXMAT0
2F0h
2F4h
278h
XPPMDFXMSK0
2F8h
27Ch
XPPMDFXMSK1
2FCh
Note:
122
Several registers will be duplicated for device 3 in the three sections discussing the
three modes it operates in RP, NTB/NTB, and NTB/RP primary and secondary but are
repeated here for readability.
Primary side configuration registers (device 3) can only be read by the local host.
3.3.2.1
VID
Bus: 0
3.3.2.2
Device: 3
Bit
Attr
Default
15:0
RO
8086h
Offset: 0h
Description
DID
Bus: 0
3.3.2.3
Function: 0
Device: 3
Bit
Attr
15:0
RO-V
Function: 0
Default
Offset: 2h
Description
Device: 3
Attr
Default
Function: 0
Offset: 4h
Description
15:11
RV
0h
Reserved
10
RW
0b
Interrupt Disable
Controls the ability of the PCI Express port to generate INTx messages on its own
behalf. This bit does not affect the ability of the RP to forward interrupt messages
received from the PCI Express port, to the internal I/OxAPIC block. However, this
bit controls the internal generation of legacy INTx interrupts for PCI Express RAS
events or for INTx interrupts due to HP/PM events or for BW change notification.
In NTB mode:
1: Legacy INTx Interrupt mode is disabled
0: Legacy INTx Interrupt mode is enabled and the NTB port can generate INTx
interrupts to system
Notes:
When this bit is set to 1, this does NOT mean that MSI is enabled. It just means
that INTx is disabled. The selection of whether MSI or INTx is chosen for
generation an interrupt is achieved via the MSI enable bit described in MSICTRL.
If a root port had previously generated an Assert_INTx interrupt when this bit
transitions from 0 to 1, then the root port generates a Deassert_INTx message to
indicate the interrupt is deasserted.
RO
0b
123
PCICMD
Bus: 0
Device: 3
Function: 0
Offset: 4h
Bit
Attr
Default
Description
RW
0b
SERR Enable
This field enables notifying the internal core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the NTB port. The internal core error logic of
IIO then decides if/how to escalate the error further (pins/message etc.). This bit
also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL
messages received from the port to the internal IIO core error logic.
1: Fatal and Non-fatal error generation and Fatal and Non-fatal error message
forwarding is enabled
0: Fatal and Non-fatal error generation and Fatal and Non-fatal error message
forwarding is disabled
Refer to PCI Express* Base Specification, Revision 2.0 for details of how this bit is
used in conjunction with other control bits in the Root Control register for
forwarding errors detected on the PCI Express interface to the system core error
logic.
RO
0b
RW
0b
RO
0b
RO
0b
RO
0b
RW
0b
124
PCICMD
Bus: 0
Device: 3
Function: 0
Offset: 4h
Bit
Attr
Default
Description
RW
0b
RO
0b
IO Space Enable
1: Enables the I/O address range, defined in the IOBASE and IOLIM registers of
the PCI-to-PCI bridge header, for target decode from primary side
0: Disables the I/O address range, defined in the IOBASE and IOLIM registers of
the PCI-to-PCI bridge header, for target decode from primary side
Notes:
This bit is not ever used by hardware to decode transactions from the secondary
side of the root port.
NTB does not support I/O space accesses. Hardwired to 0
125
3.3.2.4
126
Device: 3
Function: 0
Offset: 6h
Bit
Attr
Default
Description
15
RW1C
0b
14
RW1C
0b
13
RW1C
0b
12
RW1C
0b
11
RW1C
0b
10:9
RO
0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
RW1C
0b
RO
0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
RV
0h
Reserved
PCISTS
Bus: 0
3.3.2.5
Device: 3
Offset: 6h
Bit
Attr
Default
RO
0b
RO
1b
Capabilities List
This bit indicates the presence of a capabilities list structure
RO-V
0b
INTx Status
This Read-only bit reflects the state of the interrupt in the PCI Express Root Port.
Only when the Interrupt Disable bit in the command register is a 0 and this
Interrupt Status bit is a 1, will this device generate INTx interrupt. Setting the
Interrupt Disable bit to a 1 has no effect on the state of this bit.
This bit does not get set for interrupts forwarded to the root port from
downstream devices in the hierarchy. When MSI are enabled, Interrupt status
should not be set.
The intx status bit should be deasserted when all the relevant events (RAS errors/
HP/link change status/PM) internal to the port using legacy interrupts are cleared
by software.
In NTB Mode:
When Set, indicates that an INTx emulation interrupt is pending internally in the
Function. NTB clears this bit when the internal interrupt condition is cleared by
software. Note this bit could be set even when INTx assertion is disabled (and
INTx mode is enabled though) but an internal interrupt condition is pending.
2:0
RV
0h
Reserved
Description
RID
Bus: 0
3.3.2.6
Function: 0
Device: 3
Function: 0
Offset: 8h
Bit
Attr
Default
Description
7:0
RO
00h
Revision Identification
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register
in any Processor function.
Implementation Note:
Read and write requests from the host to any RID register in any Processor
function are re-directed to the IIO cluster. Accesses to the CCR field are also
redirected due to DWORD alignment. It is possible that JTAG accesses are direct,
so will not always be redirected.
CCR
Bus: 0
Device: 3
Function: 0
Offset: 9h
Bit
Attr
Default
Description
23:16
RO
06h
Base Class
For PCI Express NTB port this field is hardwired to 06h, indicating it is a Bridge
Device.
15:8
RO-V
80h
Sub-Class
In NTB mode, this field hardwired to 80h to indicate a Other bridge type.
In PCIe mode, it is hardwired to 04h indicating PCI-PCI Bridge.
Port3_NTB: Attr: RO-V Default: 80h
7:0
RO
00h
127
3.3.2.7
CLSR
Bus: 0
3.3.2.8
Device: 3
Bit
Attr
Default
7:0
RW
0h
Offset: Ch
Description
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for IIO is
always 64B. IIO hardware ignore this setting.
HDR
Bus: 0
3.3.2.9
Function: 0
Device: 3
Function: 0
Offset: Eh
Bit
Attr
Default
Description
RO-V
1b
Multi-function Device
This bit defaults to 0 for PCI Express NTB port.
BIOS can individually control the value of this bit, based on HDRTYPCTRL register.
BIOS will write to that register to change this field to 0, if it exposes only function
0 in the device to OS.
6:0
RO
0h
Configuration Layout
This field identifies the format of the configuration header layout. It is Type1 for
PCI Express and Type0 in NTB mode. The default is 00h, indicating a non-bridge
function.
Port3_NTB: Attr: RO Default: 00h
Port3_PCIe: Attr: RO Default: 01h
3.3.2.10
3.3.2.11
CAPPTR
Bus: 0
128
Device: 3
Bit
Attr
Default
7:0
RW-O
60h
Function: 0
Offset: 34h
Description
Capability Pointer
Points to the first capability structure for the device. In NTB mode, capabilities
start at a different location.
3.3.2.12
Bus: 0
3.3.2.13
Device: 3
Function: 0
Offset: 3Ch
Bit
Attr
Default
Description
7:0
RW
00h
Interrupt Line
This bit is RW for devices that can generate a legacy INTx message and is needed
only for compatibility purposes.
INTPIN
Bus: 0
Device: 3
Function: 0
Offset: 3Dh
Bit
Attr
Default
Description
7:0
RW-O
01h
Interrupt Pin
This field defines the type of interrupt to generate for the port.
01h: Generate INTA
Others: Reserved
BIOS can program this to 0 to indicate to OS that the port does not support INTx
interrupt.
3.3.3
3.3.3.1
3.3.3.2
Device: 3
Function: 0
Offset: 10h
Bit
Attr
Default
Description
63:16
RW
0h
15:4
RV
0h
Reserved
RO
1b
Prefetchable
BAR points to Prefetchable memory.
2:1
RO
10b
RO
0b
Type
Memory type claimed by BAR 0/1is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
129
PB23BASE
Bus: 0
3.3.3.3
Device: 3
Function: 0
Offset: 18h
Bit
Attr
Default
Description
63:12
RW
0h
11:4
RV
0h
Reserved
RO
1b
Prefetchable
BAR points to Prefetchable memory.
2:1
RO
10b
RO
0b
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
3.3.3.4
Device: 3
Function: 0
Offset: 20h
Bit
Attr
Default
Description
63:12
RW
0h
11:4
RV
0h
Reserved
RO
1b
Prefetchable
BAR points to Prefetchable memory.
2:1
RO
10b
RO
0b
Type
Memory type claimed by BAR 4/5 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
130
3.3.3.5
3.3.3.6
3.3.3.7
3.3.3.8
3.3.3.9
3.3.3.10
Device: 3
Attr
Function: 0
Default
Offset: 6Ch
Description
31:2
RV
0h
Reserved
1:0
RW
0b
Mask Bits
For each Mask bit that is set, the PCI Express port is prohibited from sending the
associated message.NTB supports up to 2 messages
Corresponding bits are masked if set to 1
Device: 3
Function: 0
Offset: 70h
Attr
Default
Description
31:2
RV
0h
Reserved
1:0
RO-V
0h
Pending Bits
For each Pending bit that is set, the PCI Express port has a pending associated
message.NTB supports up to two messages.
Corresponding bits are pending if set to 1
131
3.3.3.11
MSIXCAPID
Bus: 0
3.3.3.12
Bit
Attr
Default
7:0
RO
11h
Function: 0
Offset: 80h
Description
Capability ID
Assigned by PCI-SIG for MSI-X.
MSIXNXTPTR
Bus: 0
3.3.3.13
Device: 3
Device: 3
Function: 0
Offset: 81h
Bit
Attr
Default
Description
7:0
RW-O
90h
Next Ptr
This field is set to 90h for the next capability list (PCI Express capability structure)
in the chain.
MSIXMSGCTRL
Bus: 0
Device: 3
Bit
Attr
Default
15
RW
0b
Function: 0
Offset: 82h
Description
MSI-X Enable
Software uses this bit to select between INTx or MSI or MSI-X method for
signaling interrupts from the DMA
0: NTB is prohibited from using MSI-X to request service
1: MSI-X method is chosen for NTB interrupts
Notes:
Software must disable INTx and MSI-X for this device when using MSI
14
RW
0b
Function Mask
1: all the vectors associated with the NTB are masked, regardless of the per
vector mask bit state.
0: each vectors mask bit determines whether the vector is masked or not.
Notes:
Setting or clearing the MSI-X function mask bit has no effect on the state of the
per-vector Mask bit.
132
13:11
RV
0h
10:0
RO-V
003h
Reserved
Table Size
System software reads this field to determine the MSI-X Table Size N, which is
encoded as N-1. For example, a returned value of 00000000011 indicates a table
size of 4.
NTB table size is 4, encoded as a value of 003h
3.3.3.14
TABLEOFF_BIR
Bus: 0
3.3.3.15
Function: 0
Offset: 84h
Bit
Attr
Default
Description
31:3
RO
000004
00h
Table Offset
MSI-X Table Structure is at offset 8K from the PB01BASE address. See PXPCAPID
for the start of details relating to MSI-X registers.
2:0
RO
0h
Table BIR
Indicates which one of a functions Base Address registers, located beginning at
10h in Configuration Space, is used to map the functions MSI-X Table into
Memory Space.
BIR Value Base Address register
0: 10h
1: 14h
2: 18h
3: 1Ch
4: 20h
5: 24h
6: Reserved
7: Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.
PBAOFF_BIR
Bus: 0
3.3.3.16
Device: 3
Device: 3
Bit
Attr
Default
31:3
RO
000006
00h
2:0
RO
0h
Function: 0
Offset: 88h
Description
Table Offset
MSI-X PBA Structure is at offset 12K from the PB01BASE BAR address. See
PMSICXPBA register for details.
PBA BIR
Indicates which one of a functions Base Address registers, located beginning at
10h in Configuration Space, is used to map the functions MSI-X Table into
Memory Space.
BIR Value Base Address register
0: 10h
1: 14h
2: 18h
3: 1Ch
4: 20h
5: 24h
6: Reserved
7: Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.
133
3.3.3.17
3.3.3.18
3.3.3.19
134
Device: 3
Function: 0
Offset: 94h
Bit
Attr
Default
Description
31:29
RV
0h
Reserved
28
RO
0b
27:26
RO
0h
25:18
RO
0h
17:16
RV
0h
Reserved
15
RO
1b
14
RO
0b
13
RO
0b
12
RO
0b
11:9
RO
0b
8:6
RO
0b
Reserved
DEVCAP
Bus: 0
3.3.3.20
Device: 3
Function: 0
Offset: 94h
Bit
Attr
Default
Description
RO
1b
4:3
RO
0h
2:0
RO
1h
Device: 3
Attr
Default
Function: 0
Offset: 98h
Description
15
RV
0h
14:12
RO
000b
Reserved
11
RO
0b
Enable No Snoop
Not applicable since the NTB is never the originator of a TLP. This bit has no
impact on forwarding of NoSnoop attribute on peer requests.
10
RO
0b
RO
0b
RO
0h
7:5
RW
000b
RO
0b
Max_Read_Request_Size
Express/DMI ports in IIO do not generate requests greater than 128B and this
field is ignored.
135
DEVCTRL
Bus: 0
3.3.3.21
Device: 3
Function: 0
Offset: 98h
Bit
Attr
Default
Description
RW
0b
RW
0b
RW
0b
RW
0b
136
Device: 3
Attr
Default
Function: 0
Offset: 9Ah
Description
15:6
RV
0h
Reserved
RO
0h
Transactions Pending
Does not apply to Root ports, that is, bit hardwired to 0 for these devices.
DEVSTS
Bus: 0
3.3.3.22
Device: 3
Function: 0
Offset: 9Ah
Bit
Attr
Default
Description
RO
0b
RW1C
0b
RW1C
0b
RW1C
0b
RW1C
0b
3.3.3.23
Device: 3
Function: 0
Offset: D0h
Bit
Attr
Default
Description
7:0
RW-O
00h
137
PBAR45SZ
Bus: 0
3.3.3.24
Device: 3
Function: 0
Offset: D1h
Bit
Attr
Default
Description
7:0
RW-O
00h
3.3.3.25
Device: 3
Function: 0
Offset: D2h
Bit
Attr
Default
Description
7:0
RW-O
00h
3.3.3.26
Device: 3
Function: 0
Offset: D3
Bit
Attr
Default
Description
7:0
RW-O
00h
138
PPD
Bus: 0
3.3.3.27
Device: 3
Function: 0
Offset: D4h
Bit
Attr
Default
Description
7:6
RO
0h
Reserved
RW-V
0b
RO-V
0h
3:2
RW-V
00b
Crosslink Control
Directly forces the polarity of the NTB port to be either an Upstream Device (USD)
or Downstream Device (DSD).
11 - Force NTB port to USD/DSP;
10 - Force NTB port to DSD/USP;
01 - 00 Reserved
NOTE: Bits 03:02 of this register only have meaning when bits 01:00 of this same
register are programmed as 01b (NTB/NTB). When configured as NTB/RP
hardware directly sets port to DSD/USP so this field is not required.
When using crosslink control override, the external strap PECFGSEL[2:0] must be
set to 100b (Wait-on-BIOS). xref BIOS can then come and set this field and then
enable the port.
In applications that are DP configuration, and having an external controller set up
the crosslink control override through the SMBus master interface.
PECFGSEL[2:0] must be set to 100b (Wait-on-BIOS) on both chipsets. The
external controller on the master can then set the crosslink control override field
on both chipsets and then enable the ports on both chipsets.
1:0
RW-V
00b
Port Definition
Value indicating the value to be loaded into the DID register (offset 02h).
00b - Transparent bridge
01b - 2 NTBs connected back to back
10b - NTB connected to a RP
11b - Reserved
Note: When the NTB feature is disabled field becomes RO 00
3.3.3.28
Device: 3
Bit
Attr
Default
31:24
RO
00h
23
RO
0h
Function: 0
Offset: E4h
Description
Data
Not relevant for IIO
Bus Power/Clock Control Enable
This field is hardwired to 0h as it does not apply to PCI Express.
139
PMCSR
Bus: 0
3.3.3.29
Device: 3
Function: 0
Offset: E4h
Bit
Attr
Default
Description
22
RO
0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
21:16
RV
0h
Reserved
15
RW1CS
0h
PME Status
Applies only to root ports. This PME Status is a sticky bit. This bit is set,
independent of the PME Enable bit defined below, on an enabled PCI Express hotplug event. Software clears this bit by writing a 1 when it has been completed.
Refer to PCI Express* Base Specification, Revision 2.0 for further details on wake
event generation at a root port.
NTB Mode:
This bit is hard-wired to read-only 0, since this function does not support PME#
generation from any power state.
14:13
RO
0h
Data Scale
Not relevant for IIO
12:9
RO
0h
Data Select
Not relevant for IIO
RWS
0h
PME Enable
Applies only to root ports. This field is a sticky bit and when set, enables a virtual
PM_PME message to be generated internally on an enabled PCI Express hot-plug
event. This virtual PM_PME message then sets the appropriate bits in the
ROOTSTS register (which can then trigger an MSI/INT or cause a _PMEGPE
event).
0: Disable ability to send PME messages when an event occurs
1: Enables ability to send PME messages when an event occurs
Not used in NTB mode.
7:4
RV
0h
Reserved
RW-O
1b
No Soft Reset
Indicates IIO does not reset its registers when it transitions from D3hot to D0.
RV
0h
Reserved
1:0
RW-V
0h
Power State
This 2-bit field is used to determine the current power state of the function and to
set a new power state as well.
00: D0
01: D1 (not supported by IIO)
10: D2 (not supported by IIO)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not change
from the existing power state (which is either D0 or D3hot) and nor do these
bits1:0 change value.
All devices will respond to only Type 0 configuration transactions when in D3hot
state (RP will not forward Type 1 accesses to the downstream link) and will not
respond to memory/IO transactions (that is, D3hot state is equivalent to MSE/
IOSE bits being clear) as target and will not generate any memory/IO/
configuration transactions as initiator on the primary bus (messages are still
allowed to pass through).
140
3.3.3.30
3.3.3.31
3.3.3.32
3.3.3.33
Device: 3
Bit
Attr
Default
31:20
RO
144h
19:16
RO
1h
15:0
RO
000Dh
Function: 0
Offset: 110h
Description
3.3.3.34
3.3.3.35
3.3.3.36
3.3.3.37
3.3.3.38
141
VSHDR
Bus: 0
3.3.3.39
Device: 3
Function: 0
Offset: 148h
Bit
Attr
Default
Description
31:20
RO
03Ch
VSEC Length
This field indicates the number of bytes in the entire VSEC structure, including the
PCI Express Enhanced Capability header, the Vendor-Specific header, and the
Vendor-Specific Registers.
19:16
RO
1h
15:0
RO
0004h
VSEC Version
Set to 1h for this version of the PCI Express logic
VSEC ID
Identifies Intel Vendor Specific Capability for AER on NTB
3.3.3.40
3.3.3.41
3.3.3.42
3.3.3.43
3.3.3.44
3.3.3.45
142
HDRLOG[0:3]
Bus: 0
3.3.3.46
Device: 3
Bit
Attr
Default
31:0
ROS-V
000000
00h
Function: 0
3.3.3.47
Device: 3
Function: 0
Offset: 178h
Bit
Attr
Default
Description
31:27
RO
0h
26:7
RO
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
143
RPERRSTS
Bus: 0
3.3.3.48
Device: 3
Function: 0
Offset: 178h
Bit
Attr
Default
Description
RW1CS
0b
RW1CS
0b
RW1CS
0b
3.3.3.49
PERFCTRLSTS
Bus: 0
144
Device: 3
Function: 0
Offset: 180h
Bit
Attr
Default
63:42
RV
0h
Reserved
41
RW
0b
40
RW
0b
39:36
RV
0h
Reserved
35
RW
0b
34:21
RV
0h
20:16
RW
18h
15:14
RV
0h
Description
PERFCTRLSTS
Bus: 0
Device: 3
Function: 0
Offset: 180h
Bit
Attr
Default
Description
13:8
RW
30h
RW
1b
6:5
RV
0h
Reserved
RW
1b
RW
0b
RW
0b
RW
0b
RW
1b
145
3.3.3.50
MISCCTRLSTS
Bus: 0
Bit
146
Device: 3
Function: 0
Offset: 188h
Attr
Default
Description
63:50
RV
0h
Reserved
49
RW1CS
0b
48
RW1C
0b
Received PME_TO_ACK
Indicates that IIO received a PME turn off ack packet or it timed out waiting for
the packet
47:42
RV
0h
Reserved
41
RW
0b
40:39
RV
0h
Reserved
38
RW
0b
37
RW
0b
36
RWS
0b
Form-Factor
Indicates what form-factor a particular root port controls0 - CEM
1 - Express Module
This bit is used to interpret bit 6 in the VPP serial stream for the port as either
MRL# (CEM) input or EMLSTS# (Express Module) input.
35
RW
0b
34
RW
0b
MISCCTRLSTS
Bus: 0
Device: 3
Function: 0
Offset: 188h
Bit
Attr
Default
Description
33
RW
0b
32
RW
0b
31
RW
0b
Reserved
29
RW
1b
cfg_to_en
Disables/enables config timeouts, independently of other timeouts.
28
RW
0b
to_dis
Disables timeouts completely.
27
RWS
0b
26
RW-LV
0b
25
RW
0b
24
RW
0b
23
RW
0b
Phold Disable
Applies only to Dev#0When set, the IIO responds with Unsupported request on
receiving assert_phold message from ICH and results in generating a fatal error.
22
RWS
0b
check_cpl_tc
21
RW-O
0b
20:19
RV
0h
Reserved
18
RWS
0b
147
MISCCTRLSTS
Bus: 0
148
Device: 3
Function: 0
Bit
Attr
Default
17
RO
0b
16
RO
0b
15
RWS
0b
dis_hdr_storage
14
RWS
0b
allow_one_np_os
13
RWS
0b
tlp_on_any_lane
Offset: 188h
Description
12
RWS
1b
disable_ob_parity_check
11:10
RV
0h
Reserved
RWS
0b
dispdspolling
Disables gen2 if timeout happens in polling.cfg.
8:7
RW
0b
PME2ACKTOCTRL
RW
0b
RW
0b
RW
0b
RW
0b
MISCCTRLSTS
Bus: 0
3.3.3.51
Device: 3
Offset: 188h
Bit
Attr
Default
Description
RW
0b
RV
0h
Reserved
PCIE_IOU_BIF_CTRL
Bus: 0
Device: 3
Bit
3.3.3.52
Function: 0
Attr
Function: 0
Default
Offset: 190h
Description
15:4
RV
0h
Reserved
WO
0b
2:0
RWS
100b
Device: 3
Bit
Attr
Default
31:29
RV
0h
Function: 0
Offset: 194h
Description
Reserved
149
NTBDEVCAP
Bus: 0
150
Device: 3
Function: 0
Offset: 194h
Bit
Attr
Default
Description
28
RO
0b
27:26
RO
0h
25:18
RO
00h
17:16
RV
0h
Reserved
15
RO
1b
14
RO
0b
13
RO
0b
12
RO
0b
11:9
RW-O
110b
8:6
RW-O
000b
Reserved
RO
1b
NTBDEVCAP
Bus: 0
3.3.3.53
Device: 3
Function: 0
Offset: 194h
Bit
Attr
Default
Description
4:3
RO
00b
2:0
RO
001b
Device: 3
Function: 0
Offset: 19Ch
Bit
Attr
Default
Description
31:24
RW-O
00h
Port Number
This field indicates the PCI Express port number for the link and is initialized by
software/BIOS. NOTE: This register bit is a RW-O register from the host side. It
must be loaded by BIOS in the primary side equivalent register. This register is RO
from the secondary side of the NTB.
23:22
RV
0h
Reserved
21
RO
1b
20
RO
1b
19
RO
0b
18
RO
0b
17:15
RW-O
010b
L1 Exit Latency
This field indicates the L1 exit latency for the given PCI Express port. It indicates
the length of time this port requires to complete transition from L1 to L0.
000: Less than 1 us
001: 1 us to less than 2 us
010: 2 us to less than 4 us
011: 4 us to less than 8 us
100: 8 us to less than 16 us
101: 16 us to less than 32 us
110: 32 us to 64 us
111: More than 64us
Notes:
This register bit is a RW-O register from the host side. It must be loaded by BIOS
in the primary side equivalent register. This register is RO from the secondary side
of the NTB.
14:12
RW-O
011b
Reserved
151
LNKCAP
Bus: 0
3.3.3.54
Device: 3
Function: 0
Offset: 19Ch
Bit
Attr
Default
Description
11:10
RW-O
11b
9:4
RW-O
4h
3:0
RW-O
0011b
152
Device: 3
Function: 0
Offset: 1A0h
Attr
Default
Description
15:12
RV
0h
Reserved
11
RW
0b
10
RW
0b
LNKCON
Bus: 0
3.3.3.55
Device: 3
Function: 0
Offset: 1A0h
Bit
Attr
Default
Description
RW
0b
RO
0b
RW
0b
Reserved
RW
0b
WO
0b
Retrain Link
A write of 1 to this bit initiates link retraining in the given PCI Express/DMI port by
directing the LTSSM to the recovery state if the current state is [L0 or L1]. If the
current state is anything other than L0, L1 then a write to this bit does nothing.
This bit always returns 0 when read.It is permitted to write 1b to this bit while
simultaneously writing modified values to other fields in this register. If the LTSSM
is not already in Recovery or Configuration, the resulting Link training must use
the modified values. If the LTSSM is already in Recovery or Configuration, the
modified values are not required to affect the Link training that's already in
progress.
RW
0b
Link Disable
This field controls whether the link associated with the PCI Express/DMI port is
enabled or disabled. When this bit is a 1, a previously configured link would return
to the disabled state as defined in the PCI Express Base Specification, Revision
2.0. When this bit is clear, an LTSSM in the disabled state goes back to the detect
state.0: Enables the link associated with the PCI Express port
1: Disables the link associated with the PCI Express port
RO
0b
RV
0h
Reserved
1:0
RW-V
00b
Device: 3
Function: 0
Offset: 1A2h
Bit
Attr
Default
Description
15
RW1C
0b
153
LNKSTS
Bus: 0
3.3.3.56
Device: 3
Function: 0
Offset: 1A2h
Bit
Attr
Default
Description
14
RW1C
0b
13
RO
0b
12
RW-O
1b
11
RO
0b
Link Training
This field indicates the status of an ongoing link training session in the PCI Express
port0: LTSSM has exited the recovery/configuration state
1: LTSSM is in recovery/configuration state or the Retrain Link was set but training
has not yet begun.
The IIO hardware clears this bit once LTSSM has exited the recovery/configuration
state. Refer to PCI Express Base Specification, Revision 2.0 for details of which
states within the LTSSM would set this bit and which states would clear this bit.
Reserved
10
RO
0b
9:4
RO
00h
3:0
RO-V
1h
154
SLTCAP
Bus: 0
Device: 3
Function: 0
Offset: 1A4h
Bit
Attr
Default
Description
31:19
RW-O
0h
18
RO
0h
17
RW-O
0h
16:15
RW-O
0h
14:7
RW-O
00h
RW-O
0h
Hot-plug Capable
This field defines hot-plug support capabilities for the PCI Express port.0:
indicates that this slot is not capable of supporting Hot-plug operations.
1: indicates that this slot is capable of supporting Hot-plug operations
This bit is programed by BIOS based on the system design. This bit must be
programmed by BIOS to be consistent with the VPP enable bit for the port.
RW-O
0h
Hot-plug Surprise
This field indicates that a device in this slot may be removed from the system
without prior notification (like for instance a PCI Express cable).0: indicates that
hot-plug surprise is not supported
1: indicates that hot-plug surprise is supported
Note that if platform implemented cable solution (either direct or via a SIOM with
repeater), on a port, then this could be set. BIOS programs this field with a 0 for
CEM/SIOM FFs.
This bit is used by IIO hardware to determine if a transition from DL_active to
DL_Inactive is to be treated as a surprise down error or not. If a port is associated
with a hot pluggable slot and the hot-plug surprise bit is set, then any transition to
DL_Inactive is not considered an error. Refer to PCI Express Base Specification,
Revision 2.0 for further details.
RW-O
0h
155
SLTCAP
Bus: 0
3.3.3.57
Device: 3
Function: 0
Offset: 1A4h
Bit
Attr
Default
Description
RW-O
0h
RW-O
0h
RW-O
0h
RW-O
0h
Warning:
Any write to this register will set the Command Completed bit in the SLTSTS register,
ONLY if the VPP enable bit for the port is set. If the ports VPP enable bit is set (that is,
hot-plug for that slot is enabled), then the required actions on VPP are completed
before the Command Completed bit is set in the SLTSTS register. If the VPP enable bit
for the port is clear, then the write simply updates this register (see individual bit
definitions for details) but the Command Completed bit in the SLTSTS register is not
set.
SLTCON
Bus: 0
156
Device: 3
Function: 0
Offset: 1A8h
Bit
Attr
Default
Description
15:13
RV
0h
Reserved
12
RWS
0b
11
RW
0b
SLTCON
Bus: 0
Device: 3
Function: 0
Offset: 1A8h
Bit
Attr
Default
Description
10
RWS
1b
9:8
RW
3h
7:6
RW
3h
RW
0h
RW
0h
RW
0h
RW
0h
157
SLTCON
Bus: 0
3.3.3.58
Device: 3
Function: 0
Offset: 1A8h
Bit
Attr
Default
Description
RW
0h
RW
0h
158
Device: 3
Attr
Default
Function: 0
Offset: 1AAh
Description
15:9
RV
0h
Reserved
RW1C
0h
RO
0h
RO
0h
RO
0h
RW1C
0h
Command Completed
This bit is set by the IIO when the hot-plug command has completed and the hotplug controller is ready to accept a subsequent command. It is subsequently
cleared by software after the field has been read and processed. This bit provides
no guarantee that the action corresponding to the command is complete.
SLTSTS
Bus: 0
3.3.3.59
Device: 3
Function: 0
Offset: 1AAh
Bit
Attr
Default
Description
RW1C
0h
RW1C
0h
RW1C
0h
RW1C
0h
3.3.3.60
3.3.3.61
3.3.3.62
3.3.3.63
159
3.3.3.64
DEVCTRL2
Bus: 0
Bit
3.3.3.65
Device: 3
Function: 0
Offset: 1B8h
Attr
Default
Description
15:6
RV
0h
Reserved
RW
0b
RW-V
0b
3:0
RW-V
0h
3.3.3.66
3.3.3.67
160
3.3.3.68
3.3.3.69
3.3.3.70
3.3.3.71
3.3.3.72
3.3.3.73
3.3.3.74
3.3.3.75
3.3.3.76
161
3.3.3.77
3.3.3.78
3.3.3.79
3.3.3.80
3.3.3.81
3.3.3.82
3.3.3.83
3.3.3.84
3.3.3.85
162
3.3.3.86
3.3.3.87
3.3.3.88
3.3.3.89
3.3.3.90
3.3.3.91
3.3.3.92
3.3.3.93
3.3.3.94
163
3.3.3.95
3.3.3.96
164
3.3.4
3.3.5
Table 3-11. Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x00h 0xFCh (Sheet 1 of 2)
DID
VID
PCISTS
0h
PCICMD
CCR
BIST
RID
HDR
PLAT
CLSR
SID
84h
PBAOFF_BIR
88h
Ch
8Ch
PXPCAP
20h
CAPPTR
PXPNXTPTR
LNKCAP
LNKSTS
MINGNT
INTPIN
INTL
A0h
A4h
28h
A8h
2Ch
ACh
30h
B0h
34h
DEVCAP2
B4h
DEVCTRL2
3Ch
LNKCAP2
LNKSTS2
B8h
BCh
LNKCON2
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
SSCNTL
58h
D4h
D8h
5Ch
MSICAPID
9Ch
LNKCON
54h
MSINXTPTR
98h
24h
40h
MSICTRL
90h
94h
DEVCTRL
38h
MAXLAT
PXPCAPID
DEVCAP
DEVSTS
1Ch
SUBVID
80h
TABLEOFF_BIR
18h
SB45BASE
MSIXCAPID
4h
14h
SB23BASE
MSIXNXTPT
R
8h
10h
SB01BASE
MSIXMSGCTRL
DCh
60h
PMCAP
PMCSR
E0h
MSIAR
64h
MSIUAR
68h
E8h
MSIDR
6Ch
ECh
MSIMSK
70h
F0h
E4h
165
Table 3-11. Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x00h 0xFCh (Sheet 2 of 2)
MSIPENDING
74h
F4h
78h
F8h
7Ch
FCh
Table 3-12. Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x100h 0x1FCh
166
PXP2CAP
100h
180h
LNERRSTS
104h
184h
LN1EQ
LN0EQ
108h
188h
LN3EQ
LN2EQ
10Ch
18Ch
LN5EQ
LN4EQ
110h
190h
LN7EQ
LN6EQ
114h
194h
LN9EQ
LN8EQ
118h
198h
LN11EQ
LN10EQ
11Ch
19Ch
LN13EQ
LN12EQ
120h
1A0h
LN15EQ
LN14EQ
124h
1A4h
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
148h
1C8h
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
3.3.5.1
VID
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 500h
Device: 3
Offset: 500h
Bus: 0
3.3.5.2
Bit
Attr
Default
15:0
RO
8086h
Offset: 0h
MMIO BAR: PB01BASE
Function: 0
Description
Vendor Identification Number
The value is assigned by PCI-SIG to Intel.
DID
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 502h
Device: 3
Offset: 502h
Bus: 0
3.3.5.3
Function: 0
Function: 0
Bit
Attr
Default
15:0
RO
3C0Fh
Function: 0
Function: 0
Offset: 02h
MMIO BAR: PB01BASE
Function: 0
Description
Device Identification Number
The value is assigned by Intel to each product. For Processor IIO NTB Secondary
Endpoint, the device ID is 0x3C0F.
Device: 0
Device: 3
Offset: 504h
Device: 3
Offset: 504h
Bus: 0
Function: 0
Function: 0
Offset: 04h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
15:11
RV
0h
Reserved
10
RW
0b
INTxDisable
Interrupt Disable. Controls the ability of the PCI Express port to generate INTx
messages. This bit does not affect the ability of Processor to route interrupt
messages received at the PCI Express port. However, this bit controls the
generation of legacy interrupts to the DMI for PCI Express errors detected
internally in this port (for example, Malformed TLP, CRC error, completion time out
etc.) or when receiving RP error messages or interrupts due to HP/PM events
generated in legacy mode within Processor. Refer to the INTPIN register in
Section 3.3.5.17, INTPIN: Interrupt Pin on page 175 for interrupt routing to
DMI.1: Legacy Interrupt mode is disabled
0: Legacy Interrupt mode is enabled
RO
0b
167
PCICMD
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 504h
Device: 3
Offset: 504h
Bus: 0
3.3.5.4
Function: 0
Function: 0
Offset: 04h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
RO
0b
SERR Enable
For PCI Express/DMI ports, this field enables notifying the internal core error logic
of occurrence of an uncorrectable error (fatal or non-fatal) at the port. The
internal core error logic of IIO then decides if/how to escalate the error further
(pins/message, and so forth). This bit also controls the propagation of PCI Express
ERR_FATAL and ERR_NONFATAL messages received from the port to the internal
IIO core error logic.1: Fatal and Non-fatal error generation and Fatal and Non-fatal
error message forwarding is enabled
0: Fatal and Non-fatal error generation and Fatal and Non-fatal error message
forwarding is disabled
Refer to PCI Express* Base Specification, Revision 2.0 for details of how this bit is
used in conjunction with other control bits in the Root Control register for
forwarding errors detected on the PCI Express interface to the system core error
logic.
RO
0b
RW
0b
RO
0b
RO
0b
RO
0b
RW
0b
RW
0b
RO
0b
IO Space Enable
Controls a device's response to I/O Space accesses. A value of 0 disables the
device response. A value of 1 allows the device to respond to I/O Space accesses.
State after RST# is 0.NTB does not support I/O space accesses. Hardwired to 0
168
PCISTS
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 506h
Device: 3
Offset: 506h
Bus: 0
Function: 0
Function: 0
Offset: 06h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
15
RW1C
0b
14
RO
0b
13
RW1C
0b
12
RW1C
0b
11
RW1C
0b
10:9
RO
0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
RW1C
0b
169
PCISTS
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 506h
Device: 3
Offset: 506h
Bus: 0
3.3.5.5
Offset: 06h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
RO
0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
RO
0b
Reserved
RO
0b
66 MHz capable
Not applicable to PCI Express. Hardwired to 0.
RO
1b
Capabilities List
This bit indicates the presence of a capabilities list structure
RO-V
0b
INTx Status
When Set, indicates that an INTx emulation interrupt is pending internally in the
Function.
2:0
RV
0h
Reserved
Description
RID
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 508h
Device: 3
Offset: 508h
Bus: 0
3.3.5.6
Function: 0
Function: 0
Bit
Attr
Default
7:0
RO
00h
Function: 0
Function: 0
Offset: 08h
MMIO BAR: PB01BASE
Function: 0
Description
Revision_ID
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register
in any Intel Xeon Processor E5 Family function.
Implementation Note:
Read and write requests from the host to any RID register in any Intel Xeon
Processor E5 Family function are re-directed to the IIO cluster. Accesses to the
CCR field are also redirected due to DWORD alignment. It is possible that JTAG
accesses are direct, so will not always be redirected.
Device: 0
Device: 3
Offset: 509h
Device: 3
Offset: 509h
Bus: 0
170
Function: 0
Function: 0
Offset: 09h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
23:16
RO
06h
Base Class
For PCI Express NTB port this field is hardwired to 06h, indicating it is a Bridge
Device.
15:8
RO
80h
Sub-Class
For PCI Express NTB port, this field hardwired to 80h to indicate an Other bridge
type.
CCR
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 509h
Device: 3
Offset: 509h
Bus: 0
3.3.5.7
Bit
Attr
Default
7:0
RO
00h
Offset: 09h
MMIO BAR: PB01BASE
Function: 0
Description
Register-Level Programming Interface
This field is hardwired to 00h for PCI Express NTB port.
CLSR
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 50Ch
Device: 3
Offset: 50Ch
Bus: 0
3.3.5.8
Function: 0
Function: 0
Bit
Attr
Default
7:0
RW
0h
Function: 0
Function: 0
Offset: 0Ch
MMIO BAR: PB01BASE
Function: 0
Description
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for IIO is
always 64B. IIO hardware ignore this setting.
Device: 0
Device: 3
Offset: 50Dh
Device: 3
Offset: 50Dh
Bus: 0
3.3.5.9
Bit
Attr
Default
7:0
RO
0h
Function: 0
Function: 0
Offset: 0Dh
MMIO BAR: PB01BASE
Function: 0
Description
Prim_Lat_timer
Primary Latency Timer Not applicable to PCI Express. Hardwired to 00h.
Device: 0
Device: 3
Offset: 50Eh
Device: 3
Offset: 50Eh
Bus: 0
Bit
Attr
Default
RO
0b
6:0
RO
00h
Function: 0
Function: 0
Offset: 0Eh
MMIO BAR: PB01BASE
Function: 0
Description
Multi-function Device
This bit defaults to 0 for PCI Express NTB port.
Configuration Layout
This field identifies the format of the configuration header layout. It is Type0 for
PCI Express NTB port.The default is 00h, indicating a non-bridge function.
171
3.3.5.10
3.3.5.11
Device: 0
Device: 3
Offset: 510h
Device: 3
Offset: 510h
Function: 0
Function: 0
Offset: 10h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
63:15
RW
00h
14:4
RO
00h
Reserved
Fixed size of 32 KB.
RW-O
1b
2:1
RO
10b
RO
0b
Prefetchable
BAR points to Prefetchable memory (default) BAR points to Non-Prefetchable
memory
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
172
Device: 0
Device: 3
Offset: 518h
Device: 3
Offset: 518h
Function: 0
Function: 0
Offset: 18h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
63:12
RW
0h
11:4
RO
00h
Reserved
Granularity must be at least 4 KB.
SB23BASE
Bus: M
Bus: 0
Bus: 0
3.3.5.12
Device: 0
Device: 3
Offset: 518h
Device: 3
Offset: 518h
Bit
Attr
Default
RO
1b
2:1
RO
10b
RO
0b
Function: 0
Function: 0
Offset: 18h
MMIO BAR: PB01BASE
Function: 0
Description
Prefetchable
BAR points to Prefetchable memory.
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
3.3.5.13
Device: 0
Device: 3
Offset: 520h
Device: 3
Offset: 520h
Function: 0
Function: 0
Offset: 20h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
63:12
RW
0h
11:4
RO
00h
RO
1b
2:1
RO
10b
RO
0b
Reserved
Granularity must be at least 4 KB.
Prefetchable
BAR points to Prefetchable memory.
Type
Memory type claimed by BAR 4/5 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
173
SUBVID
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 52Ch
Device: 3
Offset: 52Ch
Bus: 0
3.3.5.14
Bit
Attr
Default
15:0
RW-O
0000h
Function: 0
Function: 0
Offset: 2Ch
MMIO BAR: PB01BASE
Function: 0
Description
Subsystem Vendor ID
This field must be programmed during boot-up to indicate the vendor of the
system board. When any byte or combination of bytes of this register is written,
the register value locks and cannot be further updated.
Device: 0
Device: 3
Offset: 52Eh
Device: 3
Offset: 52Eh
Bus: 0
3.3.5.15
Function: 0
Function: 0
Offset: 2Eh
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
15:0
RW-O
0000h
Subsystem ID
This field must be programmed during BIOS initialization. When any byte or
combination of bytes of this register is written, the register value locks and cannot
be further updated.
Device: 0
Device: 3
Offset: 534h
Device: 3
Offset: 534h
Bus: 0
3.3.5.16
Bit
Attr
Default
7:0
RW-O
60h
Function: 0
Function: 0
Offset: 34h
MMIO BAR: PB01BASE
Function: 0
Description
Capability Pointer
Points to the first capability structure for the device.
174
INTL
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 53Ch
Device: 3
Offset: 53Ch
Bus: 0
3.3.5.17
Function: 0
Function: 0
Offset: 3Ch
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
7:0
RW
00h
Interrupt Line
This bit is RW for devices that can generate a legacy INTx message and is needed
only for compatibility purposes.
Device: 0
Device: 3
Offset: 53Dh
Device: 3
Offset: 53Dh
Bus: 0
3.3.5.18
Function: 0
Function: 0
Offset: 3Dh
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
7:0
RW-O
01h
INTP
Interrupt Pin. This field defines the type of interrupt to generate for the PCI
Express port.001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
BIOS/configuration Software has the ability to program this register once during
boot to set up the correct interrupt for the port.
Note: While the PCI spec. defines only one interrupt line (INTA#) for a single
function device, the logic for the NTB has been modified to meet
customer requests for programmability of the interrupt pin. BIOS should
always set this to INTA# for standard OSs.
MINGNT
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 53Eh
Device: 3
Offset: 53Eh
Bus: 0
Bit
Attr
Default
7:0
RO
00h
Function: 0
Function: 0
Offset: 3Eh
MMIO BAR: PB01BASE
Function: 0
Description
Minimum Grant
This register does not apply to PCI Express. It is hard-coded to 00h.
175
3.3.5.19
MAXLAT
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 53Fh
Device: 3
Offset: 53Fh
Bus: 0
3.3.5.20
Bit
Attr
Default
7:0
RO
00h
Bus: 0
Attr
Default
7:0
RO
05h
Maximum Latency
This register does not apply to PCI Express. It is hard-coded to 00h.
Function: 0
Function: 0
Offset: 60h
MMIO BAR: PB01BASE
Function: 0
Description
Capability ID
Assigned by PCI-SIG for MSI.
Bus: 0
Device: 0
Device: 3
Offset: 561h
Device: 3
Offset: 561h
Function: 0
Function: 0
Offset: 61h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
7:0
RW-O
80h
Next Ptr
This field is set to 80h for the next capability list (PCI Express capability structure)
in the chain.
MSICTRL
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 562h
Device: 3
Offset: 562h
Bus: 0
Bit
176
Function: 0
Description
Device: 0
Device: 3
Offset: 560h
Device: 3
Offset: 560h
Bit
MSINXTPTR
Bus: M
Bus: 0
3.3.5.22
Offset: 3Fh
MMIO BAR: PB01BASE
MSICAPID
Bus: M
Bus: 0
3.3.5.21
Function: 0
Function: 0
Function: 0
Function: 0
Offset: 62h
MMIO BAR: PB01BASE
Function: 0
Attr
Default
Description
15:9
RV
0h
Reserved
RO
1b
RO-V
0b
MSICTRL
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 562h
Device: 3
Offset: 562h
Bus: 0
3.3.5.23
Function: 0
Function: 0
Offset: 62h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
6:4
RW
000b
3:1
RO
001b
RW
0b
MSI Enable
The software sets this bit to select platform-specific interrupts or transmit MSI
messages.0: Disables MSI from being generated.
1: Enables the PCI Express port to use MSI messages for RAS, provided bit 4 in
Section 3.2.5.88, MISCCTRLSTS: Misc. Control and Status on page 89 is clear
and also enables the Express port to use MSI messages for PM and HP events at
the root port provided these individual events are not enabled for ACPI handling
(see Section 3.2.5.88, MISCCTRLSTS: Misc. Control and Status on page 89 for
details.
NOTE: Software must disable INTx and MSI-X for this device when using MSI
Device: 0
Device: 3
Offset: 564h
Device: 3
Offset: 564h
Bus: 0
Function: 0
Function: 0
Offset: 64h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
31:20
RW
0h
Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address. This field
is R/W.
19:12
RW
00h
Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.
177
MSIAR
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 564h
Device: 3
Offset: 564h
Bus: 0
3.3.5.24
Function: 0
Function: 0
Offset: 64h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
11:4
RW
00h
RW
0h
RW
0h
1:0
RO
0h
Reserved.
Device: 0
Device: 3
Offset: 568h
Device: 3
Offset: 568h
Bus: 0
3.3.5.25
Bit
Attr
Default
31:0
RW
000000
00h
Offset: 68h
MMIO BAR: PB01BASE
Function: 0
Description
MSI Upper Address Register
MSIDR
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 56Ch
Device: 3
Offset: 56Ch
Bus: 0
178
Function: 0
Function: 0
Function: 0
Function: 0
Offset: 6Ch
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
31:16
RO
0000h
15
RW
0h
Trigger Mode
0: Edge Triggered
1: Level Triggered
Notes:
IIO does nothing with this bit other than passing it along to Intel QPI
14
RW
0h
Level
0: Deassert
1: Assert
Notes:
IIO does nothing with this bit other than passing it along to Intel QPI
13:12
RW
0h
Reserved.
MSIDR
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 56Ch
Device: 3
Offset: 56Ch
Bus: 0
3.3.5.26
Bit
Attr
Default
11:8
RW
0h
7:0
RW
00h
Function: 0
Function: 0
Offset: 6Ch
MMIO BAR: PB01BASE
Function: 0
Description
Delivery Mode
0000: Fixed: Trigger Mode can be edge or level.
0001: Lowest Priority: Trigger Mode can be edge or level.
0010: SMI/PMI/MCA - Not supported via MSI of root port
0011: Reserved - Not supported via MSI of root port
0100: NMI - Not supported via MSI of root port
0101: INIT - Not supported via MSI of root port
0110: Reserved
0111: ExtINT - Not supported via MSI of root port
Others: Reserved
Interrupt Vector
The interrupt vector (LSB) will be modified by the IIO to provide context sensitive
interrupt information for different events that require attention from the
processor. Only 1 message can be enabled by software, so all events may use any
vector.
Device: 0
Device: 3
Offset: 570h
Device: 3
Offset: 570h
Bus: 0
Bit
3.3.5.27
Attr
Function: 0
Function: 0
Offset: 70h
MMIO BAR: PB01BASE
Function: 0
Default
Description
31:1
RV
0h
Reserved
RW
0h
Mask Bit
For each Mask bit that is set, the PCI Express port is prohibited from sending the
associated message. NTB supports up to 1 message.
Corresponding bits are masked if set to 1
Bit
Attr
Device: 0
Device: 3
Offset: 574h
Device: 3
Offset: 574h
Default
Function: 0
Function: 0
Offset: 74h
MMIO BAR: PB01BASE
Function: 0
Description
31:1
RV
0h
Reserved
RO
0h
Pending Bits
For each Pending bit that is set, the PCI Express port has a pending associated
message. NTB supports 1 message.
Corresponding bits are pending if set to 1.
179
3.3.5.28
MSIXCAPID
Bus: M
Bus: 0
Bus: 0
3.3.5.29
Bit
Attr
Default
7:0
RO
11h
Bus: 0
Offset: 80h
MMIO BAR: PB01BASE
Function: 0
Description
Capability ID
Assigned by PCI-SIG for MSI-X.
Device: 0
Device: 3
Offset: 581h
Device: 3
Offset: 581h
Function: 0
Function: 0
Offset: 81h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
7:0
RO
90h
Next Ptr
This field is set to 90h for the next capability list (PCI Express capability structure)
in the chain.
MSIXMSGCTRL
Bus: M
Bus: 0
Bus: 0
180
Function: 0
Function: 0
MSIXNXTPTR
Bus: M
Bus: 0
3.3.5.30
Device: 0
Device: 3
Offset: 580h
Device: 3
Offset: 580h
Device: 0
Device: 3
Offset: 582h
Device: 3
Offset: 582h
Function: 0
Function: 0
Offset: 82h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
15
RW
0b
MSI-X Enable
Software uses this bit to select between INTx or MSI or MSI-X method for
signaling interrupts from the NTB.
0: NTB is prohibited from using MSI-X to request service.
1: MSI-X method is chosen for NTB interrupts.
Note: Software must disable INTx and MSI for this device when using MSI-X.
14
RW
0b
Function Mask
If = 1b, all the vectors associated with the NTB are masked, regardless of the per
vector mask bit state. If = 0b, each vectors mask bit determines whether the
vector is masked or not. Setting or clearing the MSI-X function mask bit has no
effect on the state of the per-vector Mask bit.
13:11
RO
0h
Reserved.
10:0
RO
003h
Table Size
System software reads this field to determine the MSI-X Table Size N, which is
encoded as N-1. For example, a returned value of 00000000011 indicates a table
size of 4. NTB table size is 4, encoded as a value of 003h.
3.3.5.31
TABLEOFF_BIR
Bus: M
Bus: 0
Bus: 0
3.3.5.32
Device: 0
Device: 3
Offset: 584h
Device: 3
Offset: 584h
Function: 0
Function: 0
Offset: 84h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
31:3
RO
000008
00h
Table Offset
MSI-X Table Structure is at offset 16K from the SB01BASE BAR address.
Section 3.3.8.1, PMSIXTBL[0:3]: Primary MSI-X Table Address Register 0 - 3 on
page 210 for the start of details relating to MSI-X registers.NOTE: Offset placed at
16K so that it can also be visible through the primary BAR for debug purposes.
2:0
RO
0h
Table BIR
Indicates which one of a functions Base Address registers, located beginning at
10h in Configuration Space, is used to map the functions MSI-X Table into
Memory Space.
BIR Value Base Address register
0 10h
1 14h
2 18h
3 1Ch
4 20h
5 24h
6 Reserved
7 Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.
PBAOFF_BIR
Bus: M
Bus: 0
Bus: 0
Device: 0
Device: 3
Offset: 588h
Device: 3
Offset: 588h
Function: 0
Function: 0
Offset: 88h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
31:3
RO
00000A
00h
Table Offset
MSI-X PBA Structure is at offset 20K from the SB01BASE BAR address. See
Section 3.3.9.4, SMSICXPBA: Secondary MSI-X Pending Bit Array on page 214
for details.NOTE: Offset placed at 20K so that it can also be visible through the
primary BAR for debug purposes.
2:0
RO
0h
PBA BIR
Indicates which one of a functions Base Address registers, located beginning at
10h in Configuration Space, is used to map the functions MSI-X Table into
Memory Space.
BIR Value Base Address register
0 10h
1 14h
2 18h
3 1Ch
4 20h
5 24h
6 Reserved
7 Reserved
For a 64-bit Base Address register, the Table BIR indicates the lower DWORD.
181
3.3.5.33
3.3.5.34
Device: 0
Device: 3
Offset: 590h
Device: 3
Offset: 590h
Bit
Attr
Default
7:0
RO
10h
Function: 0
Function: 0
Offset: 90h
MMIO BAR: PB01BASE
Function: 0
Description
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.Required by PCI
Express* Base Specification, Revision 2.0 to be this value.
3.3.5.35
Device: 0
Device: 3
Offset: 591h
Device: 3
Offset: 591h
Bit
Attr
Default
7:0
RW-O
E0h
Function: 0
Function: 0
Offset: 91h
MMIO BAR: PB01BASE
Function: 0
Description
Next Ptr
This field is set to the PCI PM capability.
Device: 0
Device: 3
Offset: 592h
Device: 3
Offset: 592h
Bus: 0
Bit
182
Attr
Default
Function: 0
Function: 0
Offset: 92h
MMIO BAR: PB01BASE
Function: 0
Description
15:14
RV
0h
Reserved
13:9
RO
0h
RW-O
0b
Slot Implemented
Applies only to the RPs for NTB this value is kept at 0b.
1: indicates that the PCI Express link associated with the port is connected to a
slot.
0: indicates no slot is connected to this port.
This register bit is of type write once and is controlled by BIOS/special
initialization firmware.
PXPCAP
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 592h
Device: 3
Offset: 592h
Bus: 0
3.3.5.36
Bit
Attr
Default
7:4
RO
0000b
3:0
RW-O
2h
Function: 0
Function: 0
Offset: 92h
MMIO BAR: PB01BASE
Function: 0
Description
Device/Port Type
This field identifies the type of device. 0000b = PCI Express Endpoint.
Capability Version
This field identifies the version of the PCI Express capability structure. Set to 2h
for PCI Express devices for compliance with the extended base registers.
Device: 0
Device: 3
Offset: 594h
Device: 3
Offset: 594h
Bus: 0
Bit
Attr
Default
Function: 0
Function: 0
Offset: 94h
MMIO BAR: PB01BASE
Function: 0
Description
31:29
RV
0h
Reserved
28
RO
0b
27:26
RO
0h
25:18
RO
00h
17:16
RV
0h
Reserved
15
RO
1b
14
RO
0b
13
RO
0b
12
RO
0b
11:9
RO
110b
Reserved
183
DEVCAP
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 594h
Device: 3
Offset: 594h
Bus: 0
3.3.5.37
Function: 0
Function: 0
Offset: 94h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
8:6
RO
000b
RO
1b
4:3
RO
00b
2:0
RO
001b
Reserved
Extended Tag Field Supported
IIO devices support 8-bit tag1 = Maximum Tag field is 8 bits
0 = Maximum Tag field is 5 bits
Device: 0
Device: 3
Offset: 598h
Device: 3
Offset: 598h
Bus: 0
Bit
184
Attr
Default
Function: 0
Function: 0
Offset: 98h
MMIO BAR: PB01BASE
Function: 0
Description
15
RV
0h
14:12
RO
000b
Reserved
11
RO
0b
Enable No Snoop
Not applicable since the NTB is never the originator of a TLP. This bit has no
impact on forwarding of NoSnoop attribute on peer requests.
10
RO
0b
RO
0b
RW
0h
7:5
RW
000b
Max_Read_Request_Size
Express/DMI ports in IIO do not generate requests greater than 128B and this
field is ignored.
DEVCTRL
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 598h
Device: 3
Offset: 598h
Bus: 0
3.3.5.38
Function: 0
Function: 0
Offset: 98h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
RO
0b
RW
0b
RW
0b
RW
0b
RW
0b
185
DEVSTS
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 59Ah
Device: 3
Offset: 59Ah
Bus: 0
3.3.5.39
Function: 0
Function: 0
Offset: 9Ah
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
15:6
RV
0h
Reserved
RO
0h
Transactions Pending
RO
0b
RW1C
0b
RW1C
0b
RW1C
0b
RW1C
0b
Device: 0
Device: 3
Offset: 59Ch
Device: 3
Offset: 59Ch
Bus: 0
186
Function: 0
Function: 0
Offset: 9Ch
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
31:24
RO
00h
Port Number
This field indicates the PCI Express port number for the link and is initialized by
software/BIOS.
Notes:
This register bit is a RW-O register from the host side. It must be loaded by BIOS
in the primary side equivalent register. This register is RO from the secondary side
of the NTB.
LNKCAP
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 59Ch
Device: 3
Offset: 59Ch
Bus: 0
Function: 0
Function: 0
Offset: 9Ch
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
23:22
RV
0h
Reserved
21
RO
0b
20
RO
1b
19
RO
1b
18
RO
0b
17:15
RW-O
010b
L1 Exit Latency
This field indicates the L1 exit latency for the given PCI Express port. It indicates
the length of time this port requires to complete transition from L1 to L0.
000: Less than 1 us
001: 1 us to less than 2 us
010: 2 us to less than 4 us
011: 4 us to less than 8 us
100: 8 us to less than 16 us
101: 16 us to less than 32 us
110: 32 us to 64 us
111: More than 64us
Notes:
This register bit is a RW-O register from the host side. It must be loaded by BIOS
in the primary side equivalent register. This register is RO from the secondary side
of the NTB.
14:12
RW-O
011b
Reserved
11:10
RW-O
11b
9:4
RW-O
8h
187
LNKCAP
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 59Ch
Device: 3
Offset: 59Ch
Bus: 0
3.3.5.40
Bit
Attr
Default
3:0
RO
0011b
Function: 0
Function: 0
Offset: 9Ch
MMIO BAR: PB01BASE
Function: 0
Description
Maximum Link Speed
This field indicates the maximum link speed of this Port.
The encoding is the binary value of the bit location in the Supported Link Speeds
Vector (in LNKCAP2) that corresponds to the maximum link speed.
Intel Xeon Processor E5 Product Family supports a maximum of 8 Gbps,
If PCIe 3.0 is disabled for the Part this field defaults to 0010 b (5 Gbps)
If PCIe 3.0 is enabled for the Part this defaults to 00 11b (8 Gbps)
Device: 0
Device: 3
Offset: 5A0h
Device: 3
Offset: 5A0h
Bus: 0
Bit
3.3.5.41
Function: 0
Function: 0
Offset: A0h
MMIO BAR: PB01BASE
Function: 0
Attr
Default
Description
15:10
RV
0h
Reserved
RO
0b
RO
0b
RW-V
0b
Reserved
RW-V
0b
5:4
RV
0h
Reserved
RO
0b
RV
0h
Reserved
1:0
RW
00b
Reserved
188
LNKSTS
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 5A2h
Device: 3
Offset: 5A2h
Bus: 0
Function: 0
Function: 0
Offset: A2h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
15:14
RV
0h
Reserved
13
RO
0b
1b
12
Description
Note:
This register bit is a RW-O register from the host side. It must be loaded
by BIOS in the primary side equivalent register. This register is RO from
the secondary side of the NTB.
256_2_3_Parent: Attr: RO Default: 1b
0_3_0_PB01BASE: Attr: RO Default: 1b
0_3_0_SB01BASE: Attr: RW-O Default: 1b
3.3.5.42
11
RO
0b
Link Training
This field indicates the status of an ongoing link training session in the PCI Express
port.
0: LTSSM has exited the recovery/configuration state
1: LTSSM is in recovery/configuration state or the Retrain Link was set but training
has not yet begun.
The IIO hardware clears this bit once LTSSM has exited the recovery/configuration
state. Refer to PCI Express Base Specification, Revision 2.0 for details of which
states within the LTSSM would set this bit and which states would clear this bit.
10
RO
0b
Reserved
9:4
RO
0h
3:0
RO-V
1h
189
SSCNTL
Bus: M
Bus: 0
Device: 0
Device: 3
Offset: 5D4h
Device: 3
Offset: 5D4h
Bus: 0
3.3.5.43
Function: 0
Function: 0
Offset: D4h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
15:1
RO
0h
Reserved
RW
0b
Device: 0
Device: 3
Offset: 5E0h
Device: 3
Offset: 5E0h
Bus: 0
190
Function: 0
Function: 0
Offset: E0h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
31:27
RO
0h
PME Support
Indicates the PM states within which the function is capable of sending a PME
message.NTB secondary side does not forward PME messages.
Bit 31 = D3cold
Bit 30 = D3hot
Bit 29 = D2
Bit 28 = D1
Bit 27 = D0
26
RO
0b
D2 Support
IIO does not support power management state D2.
25
RO
0b
D1 Support
IIO does not support power management state D1.
24:22
RO
000b
21
RO
0b
20
RV
0h
Reserved
19
RO
0b
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16
RO
011b
15:8
RO
00h
7:0
RO
01h
Capability ID
Provides the PM capability ID assigned by PCI-SIG.
AUX Current
Device does not support auxiliary current
Version
This field is set to 3h (PM 1.2 compliant) as version number for all PCI Express
ports.
3.3.5.44
Device: 0
Device: 3
Offset: 5E4h
Device: 3
Offset: 5E4h
Bus: 0
Function: 0
Function: 0
Offset: E4h
MMIO BAR: PB01BASE
Function: 0
Bit
Attr
Default
Description
31:24
RO
00h
23
RO
0h
22
RO
0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
Data
Not relevant for IIO
21:16
RV
0h
Reserved
15
RO
0h
PME Status
Applies only to RPs. This bit is hard-wired to read-only 0, since this function does
not support PME# generation from any power state.
This PME Status is a sticky bit. This bit is set, independent of the PMEEN bit
defined below, on an enabled PCI Express hotplug event provided the RP was in
D3hot state. Software clears this bit by writing a 1 when it has been completed.
Refer to PCI Express Base Specification, Revision 2.0 for further details on wake
event generation at a RP
14:13
RO
0h
Data Scale
Not relevant for IIO
12:9
RO
0h
Data Select
Not relevant for IIO
RO
0h
PME Enable
Applies only to RPs. 0: Disable ability to send PME messages when an event
occurs
1: Enables ability to send PME messages when an event occurs
7:4
RV
0h
Reserved
RW-O
1b
Indicates IIO does not reset its registers when it transitions from D3hot
to D0
RV
0h
Reserved
1:0
RW
0h
Power State
This 2-bit field is used to determine the current power state of the function and to
set a new power state as well. 00: D0
01: D1 (not supported by IIO)
10: D2 (not supported by IIO)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not change
from the existing power state (which is either D0 or D3hot) and nor do these
bits1:0 change value.
All devices will respond to only Type 0 configuration transactions when in D3hot
state (RP will not forward Type 1 accesses to the downstream link) and will not
respond to memory/IO transactions (that is, D3hot state is equivalent to MSE/
IOSE bits being clear) as target and will not generate any memory/IO/
configuration transactions as initiator on the primary bus (messages are still
allowed to pass through).
191
3.3.5.45
PXP2CAP
Bus: M
3.3.5.46
Device: 0
Function: 0
Offset: 100h
Bit
Attr
Default
Description
31:20
RO
000h
19:16
RO
1h
15:0
RO
0000h
Capability Version
This field is a PCI-SIG defined version number that indicates the version of the
Capability structure present. Must be 1h for this version of the specification.
PCI Express Extended Capability ID
This field is a PCI SIG defined ID number that indicates the nature and format of
the Extended Capability. PCI Express Extended Capability ID for the Secondary
PCI Express Extended Capability is 0x0019h.
3.3.5.47
3.3.5.48
3.3.5.49
192
3.3.6
PBAR4LMT
PBAR2XLAT
PBAR4XLAT
SBAR2LMT
SBAR4LMT
SBAR2XLAT
SBAR4XLAT
SBAR0BASE
SPAD0
80h
4h
SPAD1
84h
8h
SPAD2
88h
Ch
SPAD3
8Ch
10h
SPAD4
90h
14h
SPAD5
94h
18h
SPAD6
98h
1Ch
SPAD7
9Ch
20h
SPAD8
A0h
24h
SPAD9
A4h
28h
SPAD10
A8h
2Ch
SPAD11
ACh
30h
SPAD12
B0h
34h
SPAD13
B4h
38h
SPAD14
B8h
3Ch
SPAD15
BCh
40h
SPADSEMA4
44h
SBAR2BASE
SBAR4BASE
NTBCNTL
CBFDF
0h
SBDF
C0h
C4h
48h
C8h
4Ch
CCh
50h
RSDBMSIXV70
D0h
54h
RSDBMSIXV158
D4h
58h
D8h
5Ch
DCh
PDBMSK
PDOORBELL
60h
E0h
SDBMSK
SDOORBELL
64h
E4h
USMEMMISS
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
100h
180h
B2BSPAD1
104h
184h
B2BSPAD2
108h
188h
B2BSPAD3
10Ch
18Ch
193
110h
190h
B2BSPAD5
114h
194h
B2BSPAD6
118h
198h
B2BSPAD7
11Ch
19Ch
B2BSPAD8
120h
1A0h
B2BSPAD9
124h
1A4h
B2BSPAD10
128h
1A8h
B2BSPAD11
12Ch
1ACh
B2BSPAD12
130h
1B0h
B2BSPAD13
134h
1B4h
B2BSPAD14
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
148h
1C8h
B2BSPAD15
B2BDOORBELL
B2BBAR0XLAT
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
3.3.7
3.3.7.1
PBAR2LMT
Bus: 0
Bus: 0
194
Device: 3
Offset: 0h
Device: 3
Offset: 0h
Bit
Attr
Default
63:48
RV
0h
Function: 0
Function: 0
Description
Reserved
PBAR2LMT
Bus: 0
Bus: 0
Device: 3
Offset: 0h
Device: 3
Offset: 0h
Function: 0
Function: 0
Bit
Attr
Default
Description
47:12
RW
000000
000h
11:0
3.3.7.2
RV
0h
Reserved
PBAR4LMT
Bus: 0
Bus: 0
Device: 3
Offset: 8h
Device: 3
Offset: 8h
Bit
Attr
Default
63:48
RV
0h
Function: 0
Function: 0
Description
Reserved
195
PBAR4LMT
Bus: 0
Bus: 0
Device: 3
Offset: 8h
Device: 3
Offset: 8h
Function: 0
Function: 0
Bit
Attr
Default
Description
47:12
RW
000000
000h
11:0
3.3.7.3
RV
0h
Reserved
PBAR2XLAT
Bus: 0
Bus: 0
Device: 3
Offset: 10h
Device: 3
Offset: 10h
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
RW
000000
000000
0h
11:0
196
RV
0h
Reserved
3.3.7.4
PBAR4XLAT
Bus: 0
Bus: 0
3.3.7.5
Device: 3
Offset: 18h
Device: 3
Offset: 18h
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
RW
000000
000000
0h
11:0
RV
0h
Reserved
SBAR2LMT
Bus: 0
Bus: 0
Device: 3
Offset: 20h
Device: 3
Offset: 20h
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
RW-V
000000
000000
0h
11:0
RV
0h
Reserved
197
3.3.7.6
SBAR4LMT
Bus: 0
Bus: 0
Device: 3
Offset: 28h
Device: 3
Offset: 28h
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
RW-V
000000
000000
0h
11:0
3.3.7.7
RV
0h
Reserved
Bit
Attr
Default
63:12
RW-L
000000
000000
0h
11:0
198
Device: 3
Offset: 30h
Device: 3
Offset: 30h
RV
0h
Function: 0
Function: 0
Description
Secondary BAR 2/3 Translate
The aligned base address into Primary side memory.
Notes:
Attr will appear as RW to SW
The number of bits that are writable in this register is dictated by the value loaded
into the SBAR23SZ register by the BIOS at initialization time (before BIOS PCI
enumeration). SBAR23SZ indicates the lowest order bit of this register field that is
writeable where valid values are 12-39. If SBAR23SZ is set to 12, all bits are
writeable. If set to 39, then bits 38:12 are Read Only and will return values of 0.
For the special case where SBAR23SZ = 0, bits 63:0 are all RO=0 resulting in
the BAR being disabled.
The lowest order address bit is 12 to enforce a minimum granularity of 4 KB.
Reserved
3.3.7.8
3.3.7.9
Device: 3
Offset: 38h
Device: 3
Offset: 38h
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
RW-L
000000
000000
0h
11:0
RV
0h
Reserved
Bit
Attr
63:13
Device: 3
Offset: 40h
Device: 3
Offset: 40h
Function: 0
Function: 0
Default
Description
000000
000000
0h
12:4
RV
0h
Reserved
RW-O
1b
Prefetchable
1: BAR points to Prefetchable memory (default)
0: BAR points to Non-Prefetchable memory
2:1
RO
10b
RO
0b
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
199
3.3.7.10
Device: 3
Offset: 48h
Device: 3
Offset: 48h
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
RW
000000
000000
0h
3.3.7.11
11:4
RO
00h
RO
1b
2:1
RO
10b
RO
0b
Reserved
Granularity must be at least 4KB.
Prefetchable
BAR points to Prefetchable memory.
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
Device: 3
Offset: 50h
Device: 3
Offset: 50h
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
RW
000000
000000
0h
200
SBAR4BASE
Bus: 0
Bus: 0
3.3.7.12
Device: 3
Offset: 50h
Device: 3
Offset: 50h
Bit
Attr
Default
11:4
RO
00h
RO
1b
2:1
RO
10b
RO
0b
Function: 0
Function: 0
Description
Reserved
Prefetchable
BAR points to Prefetchable memory.
Type
Memory type claimed by BAR 4/5 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).
Device: 3
Offset: 58h
Device: 3
Offset: 58h
Bus: 0
Function: 0
Function: 0
Bit
Attr
Default
Description
31:11
RV
0h
Reserved
10
0b
9:8
00b
7:6
00b
201
NTBCNTL
Bus: 0
Bus: 0
Bit
Attr
Device: 3
Offset: 58h
Device: 3
Offset: 58h
Function: 0
Function: 0
Default
Description
5:4
00b
3:2
00b
1b
1b
202
3.3.7.13
Device: 3
Offset: 5Ch
Device: 3
Offset: 5Ch
Bus: 0
3.3.7.14
Function: 0
Function: 0
Bit
Attr
Default
Description
15:8
RW
7Fh
Secondary Bus for the secondary side of the NTB port while in NTB mode
Value to be used for the Bus number for ID-based routing.Hardware will leave the
default value of 7Fh when this port is USD
Hardware will increment the default value to 80h when this port is DSD
7:3
RW
00h
Secondary Device for the secondary side of the NTB port while in NTB
mode
Value to be used for the Device number for ID-based routing.
2:0
RW
0h
Secondary Function for the secondary side of the NTB port while in NTB
mode
Value to be used for the Function number for ID-based routing.
CBFDF
Bus: 0
Device: 3
Offset: 5Eh
Device: 3
Offset: 5Eh
Bus: 0
Bit
Attr
Default
15:8
RO-V
00h
Function: 0
Function: 0
Description
Secondary Bus
Value to be used for the Bus number for ID-based routing.
This register contains the Bus, Device and Function for the secondary side of the
NTB when PPD.Port Definition is configured as NTB/RP.
Notes:
When configured as a NTB/RP, the NTB must capture the Bus and Device Numbers
supplied with all Type 0 Configuration Write Requests completed by the NTB and
supply these numbers in the Bus and Device Number fields of the Requester ID for
all Requests initiated by the NTB. The Bus Number and Device Number may be
changed at run time, and so it is necessary to re-capture this information with
each and every Configuration Write Request.
When configured as a NTB/RP, if NTB must generate a Completion prior to the
initial device Configuration Write Request, 0s must be entered into the Bus
Number and Device Number fields
This register is only valid when configured as NTB/RP. This register has no
meaning when configured as NTB/NTB or RP.
3.3.7.15
7:3
RO-V
00h
2:0
RO-V
0h
Secondary Device
Value to be used for the Device number for ID-based routing.
Secondary Function
Value to be used for the Function number for ID-based routing.
203
PDOORBELL
Bus: 0
Bus: 0
Bit
Attr
15
Device: 3
Offset: 60h
Device: 3
Offset: 60h
Function: 0
Function: 0
Default
0h
Description
Link State Interrupt
This bit is set when a link state change occurs on the Secondary side of the NTB
(Bit 0 of the NTBSTATUS register). This bit is cleared by writing a 1 from the
Primary side of the NTB.
Notes:
This field is RW1C from PB01BASE (primary side window) and RO from SB01BASE
(secondary side window).
0_3_0_PB01BASE: Attr: RW1C Default: 0h
0_3_0_SB01BASE: Attr: RO Default: 0h
14:0
0000h
3.3.7.16
Device: 3
Offset: 62h
Device: 3
Offset: 62h
Bus: 0
Bit
15:0
Attr
Function: 0
Function: 0
Default
FFFFh
Description
Primary Doorbell Mask
This register will allow software to mask the generation of interrupts to the
processor on the Primary side of the NTB.
0: Allow the interrupt
1: Mask the interrupt
Notes:
This field is RW from PB01BASE (primary side window) and RO from SB01BASE
(secondary side window).
0_3_0_PB01BASE: Attr: RW Default: FFFFh
0_3_0_SB01BASE: Attr: RO Default: FFFFh
3.3.7.17
204
SDOORBELL
Bus: 0
Bus: 0
Bit
Attr
15:0
Device: 3
Offset: 64h
Device: 3
Offset: 64h
Function: 0
Function: 0
Default
Description
0000h
3.3.7.18
Device: 3
Offset: 66h
Device: 3
Offset: 66h
Bus: 0
Bit
Attr
Default
15:0
RW-V
0000h
Function: 0
Function: 0
Description
Secondary Doorbell Mask
This register will allow software to mask the generation of interrupts to the
processor on the Secondary side of the NTB.
0: Allow the interrupt
1: Mask the interrupt
Notes:
This field is RO from PB01BASE (primary side window) and RW from SB01BASE
(secondary side window).
3.3.7.19
Device: 3
Offset: 70h
Device: 3
Offset: 70h
Bit
Attr
Default
15:0
RW-V
0000h
Function: 0
Function: 0
Description
Upstream Memory Miss
This register keeps a running count of misses to any of the 3 upstream memory
windows on the secondary side of the NTB. The counter does not freeze at max
count it rolls over.
205
3.3.7.20
3.3.7.21
Device: 3
Function: 0
MMIO BAR:
Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Device: 3
Function: 0
MMIO BAR:
Offset: A0h, A4h, A8h, ACh, B0h, B4h, B8h, BCh
Device: 3
Function: 0
MMIO BAR:
Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch
Device: 3
Function: 0
MMIO BAR:
Offset: A0h, A4h, A8h, ACh, B0h, B4h, B8h, BCh
Bit
Attr
Default
31:0
RW
00h
PB01BASE
PB01BASE
SB01BASE
SB01BASE
Description
Scratchpad Register n
This set of 16 registers is RW from both sides of the bridge. Synchronization is
provided with a hardware semaphore (SPADSEMA4). Software will use these
registers to pass a protocol, such as a heartbeat, from system to system across
the NTB.
Bit
3.3.7.22
Device: 3
Offset: C0h
Device: 3
Offset: C0h
Attr
Default
31:1
RO
00h
RW-V
0h
Function: 0
Function: 0
Description
Reserved
Scratchpad Semaphore
This bit will allow software to synchronize write ownership of the scratchpad
register set. The processor will read the register:
If the returned value is 0, the bit is set by hardware to 1 and the reading
processor is granted ownership of the scratchpad registers.
If the returned value is 1, then the processor on the opposite side of the NTB
already owns the scratchpad registers and the reading processor is not allowed to
modify the scratchpad registers.
To relinquish ownership, the owning processor writes a 1 to this register to reset
the value to 0. Ownership of the scratchpad registers is not set in hardware, that
is, the processor on each side of the NTB is still capable of writing the registers
regardless of the state of this bit.
The attribute of this register is R0TS (Read 0 to Set) and W1TC (Write 1 to Clear)
206
Device: 3
Offset: D0h
Device: 3
Offset: D0h
Bit
Attr
Default
31:30
RV
0h
Function: 0
Function: 0
Description
Reserved
RSDBMSIXV70
Bus: 0
Bus: 0
3.3.7.23
Device: 3
Offset: D0h
Device: 3
Offset: D0h
Function: 0
Function: 0
Bit
Attr
Default
Description
29:28
RW
2h
27:26
RV
0h
Reserved
25:24
RW
2h
23:22
RV
0h
Reserved
21:20
RW
1h
19:18
RV
0h
Reserved
17:16
RW
1h
15:14
RV
0h
Reserved
13:12
RW
1h
11:10
RV
0h
Reserved
9:8
RW
1h
7:6
RV
0h
Reserved
5:4
RW
1h
3:2
RV
0h
Reserved
1:0
RW
0h
Device: 3
Offset: D4h
Device: 3
Offset: D4h
Function: 0
Function: 0
Bit
Attr
Default
Description
31:30
RV
0h
Reserved
29:28
RW
3h
27:26
RV
0h
Reserved
25:24
RW
3h
23:22
RV
0h
Reserved
21:20
RW
3h
19:18
RV
0h
Reserved
17:16
RW
3h
15:14
RV
0h
Reserved
13:12
RW
3h
11:10
RV
0h
Reserved
9:8
RW
2h
207
RSDBMSIXV158
Bus: 0
Bus: 0
3.3.7.24
Device: 3
Offset: D4h
Device: 3
Offset: D4h
Function: 0
Function: 0
Bit
Attr
Default
Description
7:6
RV
0h
Reserved
5:4
RW
2h
3:2
RV
0h
Reserved
1:0
RW
2h
Bit
31:0
3.3.7.25
Attr
Device: 3
Offset: 100h,
Device: 3
Offset: 120h,
Device: 3
Offset: 100h,
Device: 3
Offset: 120h,
Function: 0
104h, 108h, 10Ch,
Function: 0
124h, 128h, 12Ch,
Function: 0
104h, 108h, 10Ch,
Function: 0
124h, 128h, 12Ch,
Default
Description
000000
00h
208
B2BDOORBELL
Bus: 0
Bus: 0
Bit
Attr
Default
15:14
RV
0h
13:0
3.3.7.26
Device: 3
Offset: 140h
Device: 3
Offset: 140h
0000h
Function: 0
Function: 0
Description
Reserved
B2B Doorbell Interrupt
These bits are written by the processor on the Primary side of the NTB. Writing to
this register will cause a PCIe packet with the same contents as the write to be
sent to the PDOORBELL register on the a second NTB connected back-to-back with
this NTB, which in turn will cause a doorbell interrupt to be generated to the
processor on the second NTB.
Hardware on the originating NTB clears this register upon scheduling the PCIe
packet.
0_3_0_PB01BASE: Attr: RW1S Default: 0000h
0_3_0_SB01BASE: Attr: RO Default: 0000h
B2BBAR0XLAT
Bus: 0
Bus: 0
Bit
Attr
63:15
Device: 3
Offset: 144h
Device: 3
Offset: 144h
Function: 0
Function: 0
Default
Description
000000
000000
0h
B2B translate
Base address of Secondary BAR 0/1 on the opposite NTB-This register is used to
set the base address where the back-to-back doorbell and scratchpad packets will
be sent. This register must match the base address loaded into the BAR 0/1 pair
on the opposite NTB, whose Secondary side in linked to the Secondary side of this
NTB.
Notes:
There is no hardware enforced limit for this register, care must be taken when
setting this register to stay within the addressable range of the attached system.
Primary side MSI-X MMIO registers reached via PB01BASE
0_3_0_PB01BASE: Attr: RW Default: 0000000000000h
0_3_0_SB01BASE: Attr: RO Default: 0000000000000h
14:0
RO
00h
Reserved
Limit register has a granularity of 32KB (215)
209
3.3.8
PMSIXTBL0
3004h
PMSIXDATA0
2008h
3008h
PMSICXVECCNTL0
200Ch
300Ch
2010h
3010h
2014h
3014h
PMSIXDATA1
2018h
3018h
PMSICXVECCNTL1
201Ch
301Ch
2020h
3020h
2024h
3024h
PMSIXDATA2
2028h
3028h
PMSICXVECCNTL2
202Ch
302Ch
2030h
3030h
2034h
3034h
PMSIXDATA3
2038h
3038h
PMSICXVECCNTL3
203Ch
303Ch
2040h
3040h
2044h
3044h
2048h
3048h
204Ch
304Ch
PMSIXTBL2
PMSIXTBL3
PMSIXTBL[0:3]
Bus: 0
Bus: 0
210
3000h
2004h
PMSIXTBL1
3.3.8.1
PMSIXPBA
Device: 3
Function: 0
MMIO BAR: PB01BASE
Offset: 2000h, 2010h, 2020h, 2030h
Device: 3
Function: 0
MMIO BAR: SB01BASE
Offset: 2000h, 2010h, 2020h, 2030h
Bit
Attr
Default
Description
63:32
RW
000000
00h
31:2
RW
000000
00h
MSI-X Address
System-specified message lower address. For MSI-X messages, the contents of
this field from an MSI-X Table entry specifies the lower portion of the DWORDaligned address (AD[31:02]) for the memory write transaction.
1:0
RO
00b
MSG_ADD10
For proper DWORD alignment, these bits need to be 0s.
3.3.8.2
PMSIXDATA[0:3]
Bus: 0
Device: 3
Function: 0
MMIO BAR: PB01BASE
Offset: 2008h, 2018h, 2028h, 2038h
Bus: 0
Device: 3
Function: 0
MMIO BAR: SB01BASE
Offset: 2008h, 2018h, 2028h, 2038h
Bit
Attr
Default
31:0
RW
0000h
Description
Message Data
System-specified message data.
Table 3-16. MSI-X Vector Handling and Processing by IIO on Primary Side
Number of Messages enabled by Software
Events
IV[7:0]
All
xxxxxxxx1
PD[04:00]
xxxxxxxx
PD[09:05]
xxxxxxxx
PD[14:10]
xxxxxxxx
xxxxxxxx
Notes:
1.
3.3.8.3
The term xxxxxx in the Interrupt vector denotes that software initializes them and IIO will not modify
any of the x bits.
PMSICXVECCNTL[0:3]
Bus: 0
Device: 3
Function: 0
MMIO BAR: PB01BASE
Offset: 200Ch, 201Ch, 202Ch, 203Ch
Bus: 0
Device: 3
Function: 0
MMIO BAR: SB01BASE
Offset: 200Ch, 201Ch, 202Ch, 203Ch
3.3.8.4
Bit
Attr
Default
31:1
RO
000000
00h
RW
1b
Description
Reserved
MSI-X Mask
When this bit is set, the NTB is prohibited from sending a message using this MSIX Table entry. However, any other MSI-X Table entries programmed with the same
vector will still be capable of sending an equivalent message unless they are also
masked.
Bit
Attr
Device: 3
Offset: 3000h
Device: 3
Offset: 3000h
Default
Function: 0
Function: 0
Description
31:4
RV
0h
Reserved
RO-V
0b
211
PMSICXPBA
Bus: 0
Bus: 0
3.3.9
Device: 3
Offset: 3000h
Device: 3
Offset: 3000h
Function: 0
Function: 0
Bit
Attr
Default
Description
RO-V
0b
RO-V
0b
RO-V
0b
SMSIXPBA
5000h
4004h
5004h
SMSIXDATA0
4008h
5008h
SMSIXVECCNTL0
400Ch
500Ch
4010h
5010h
SMSIXTBL1
4014h
5014h
SMSIXDATA1
4018h
5018h
SMSIXVECCNTL1
401Ch
501Ch
4020h
5020h
SMSIXTBL2
4024h
5024h
SMSIXDATA2
4028h
5028h
SMSIXVECCNTL2
402Ch
502Ch
4030h
5030h
SMSIXTBL3
212
4000h
4034h
5034h
SMSIXDATA3
4038h
5038h
SMSIXVECCNTL3
403Ch
503Ch
4040h
5040h
4044h
5044h
4048h
5048h
404Ch
504Ch
3.3.9.1
SMSIXTBL[0:3]
Bus: 0
Bus: 0
3.3.9.2
Device: 3
Function: 0
MMIO BAR: PB01BASE
Offset: 4000h, 4010h, 4020h, 4030h
Device: 3
Function: 0
MMIO BAR: SB01BASE
Offset: 4000h, 4010h, 4020h, 4030h
Bit
Attr
Default
Description
63:32
RW
000000
00h
31:2
RW
000000
00h
MSI-X Address
System-specified message lower address. For MSI-X messages, the contents of
this field from an MSI-X Table entry specifies the lower portion of the DWORDaligned address (AD[31:02]) for the memory write transaction.
1:0
RO
00b
MSG_ADD10
For proper DWORD alignment, these bits need to be 0s.
3.3.9.3
Bit
Attr
Default
31:0
RW
0000h
Description
Message Data
System-specified message data.
SMSIXVECCNTL[0:3]
Bus: 0
Device: 3
Function: 0
MMIO BAR: PB01BASE
Offset: 400Ch, 401Ch, 402Ch, 403Ch
Bus: 0
Device: 3
Function: 0
MMIO BAR: SB01BASE
Offset: 400Ch, 401Ch, 402Ch, 403Ch
Bit
Attr
Default
31:1
RO
000000
00h
RW
1b
Description
Reserved
MSI-X Mask
When this bit is set, the NTB is prohibited from sending a message using this MSIX Table entry. However, any other MSI-X Table entries programmed with the same
vector will still be capable of sending an equivalent message unless they are also
masked.
213
Intel
Table 3-18. MSI-X Vector Handling and Processing by IIO on Secondary Side
Number of Messages Enabled by Software
Events
IV[7:0]
All
xxxxxxxx1
PD[04:00]
xxxxxxxx
PD[09:05]
xxxxxxxx
PD[14:10]
xxxxxxxx
PD[15]
xxxxxxxx
Notes:
1. The term xxxxxx in the Interrupt vector denotes that software initializes them and IIO will not modify any
of the x bits
3.3.9.4
SMSICXPBA
Bus: 0
Bus: 0
Bit
3.4
Device: 3
Offset: 5000h
Device: 3
Offset: 5000h
Function: 0
Function: 0
Attr
Default
Description
31:4
RV
0h
Reserved
RO-V
0b
RO-V
0b
RO-V
0b
RO-V
0b
3.4.1
Table 3-19. Intel QuickData Technology Configuration Map. Device 4 Function 0 -7 Offset
0x00H to 0x0FCH (Sheet 1 of 2)
DID
VID
00h
PCISTS
PCICMD
04h
TABLEOFF_BIR
PBAOFF_BIR
CCR
RID
08h
HDR
CLSR
0Ch
CB_BAR
10h
14h
214
MSIXMSGCTL
MSIXNXTPT
R1
MSIXCAPID
80h
84h
88h
8Ch
EXPCAP
NEXTPTR
DEVCAP
CAPID
90h
94h
Table 3-19. Intel QuickData Technology Configuration Map. Device 4 Function 0 -7 Offset
0x00H to 0x0FCH (Sheet 2 of 2)
18h
SDID
SVID
DEVSTS
DEVCON
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPTR2
34h
INTL
3Ch
BCh
40h
C0h
44h
C4h
DEVCAP2
38h
INTPIN
98h
1Ch
DEVCFG/
Reserved3
B4h
DEVCON2
B8h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
64h
PMCAP
PMCSR
E0h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Notes:
1. Each capability block contains a Next Pointer to the next capability block, or a value of zero indicating it is the last capability.
2. CAPPTR points to the first capability block.
3. This register is defined for only Fn#0 and is reserved for other functions.
215
Table 3-20. Intel QuickData Technology Configuration Map. Device 4 Function 0 -7 Offset
0x100-0x1FF
100h
CHANERR_INT
180h
104h
CHANERRMSK_INT
184h
108h
CHANERRSEV_INT
10Ch
188h
CHANERRP
TR
18Ch
110h
190h
114h
194h
118h
198h
11Ch
19Ch
120h
1A0h
124h
1A4h
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
DMAUNCERRSTS1/Reserved
148h
1C8h
DMAUNCERRMSK1/Reserved
14Ch
1CCh
150h
1D0h
154h
1D4h
DMAUNCERRSEV1/Reserved
DMAUNCER
RPTR1/
Reserved
DMAGLBER
RPTR1/
Reserved
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
Notes:
1. All the DMAUNC* and DMAGLBERRPTR registers are defined only for Fn#0 and these register offsets are reserved for other
functions.
216
3.4.2
3.4.2.1
VID
Bus: 0
3.4.2.2
Device: 4
Bit
Attr
Default
15:0
RO
8086h
Offset: 00h
Description
DID
Bus: 0
Bit
Device: 4
Attr
Function: 0 - 7
Default
15:0
3.4.2.3
Function: 0 - 7
Offset: 02h
Description
Device: 4
Bit
Attr
Default
15:11
RV
0h
Function: 0 - 7
Offset: 04h
Description
Reserved
217
PCICMD
Bus: 0
218
Device: 4
Function: 0 - 7
Offset: 04h
Bit
Attr
Default
Description
10
RW
0b
RO
0b
RO
0b
SERR Enable
This bit has no impact on error reporting from Intel QuickData Technology.
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RW
0b
RW
0b
RO
0b
IO Space Enable
N/A
3.4.2.4
PCISTS
Bus: 0
3.4.2.5
Device: 4
Function: 0 - 7
Offset: 06h
Bit
Attr
Default
Description
15
RW1C
0b
14
RO
0b
13
RO
0b
12
RO
0b
11
RW1C
0b
10:9
RO
0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
RW1C
0b
RO
0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
RV
0h
Reserved
RO
0b
RO
1b
Capabilities List
This bit indicates the presence of a capabilities list structure
RO
0b
INTx Status
Indicates that a legacy INTx interrupt condition is pending internally in the Intel
QuickData Technology device. This bit has meaning only in the legacy interrupt
mode. This bit is always 0 when MSI-X (see xref) has been selected for DMA
interrupts. Note that the setting of the INTx status bit is independent of the INTx
enable bit in the PCI command register, that is, this bit is set anytime the DMA
engine is setup by software to generate a INTx interrupt and the condition that
triggers the interrupt has occurred, regardless of whether a legacy interrupt
message was signaled or not. Note that the INTx enable bit has to be set in the
PCICMD register for DMA to generate a INTx message to the ICH. This is cleared
when the internal interrupt condition is cleared by software.
2:0
RV
0h
Reserved
219
RID
Bus: 0
3.4.2.6
Device: 4
Bit
Attr
Default
7:0
RO
00h
Function: 0 - 7
Offset: 08h
Description
Revision_ID
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register
in any Intel Xeon Processor E5 Family function.
Implementation Note:
Read and write requests from the host to any RID register in any Intel Xeon
Processor E5 Family function are re-directed to the IIO cluster. Accesses to the
CCR field are also redirected due to DWORD alignment. It is possible that JTAG
accesses are direct, so will not always be redirected.
3.4.2.7
Device: 4
Attr
Default
Description
23:16
RO
08h
Base Class
For Intel QuickData Technology, this field defaults to 08h, indicating it is a Generic
System Peripherals.
15:8
RO
80h
Sub-Class
For Intel QuickData Technology device, this field defaults to 80h indicating Other
System Peripheral.
7:0
RO
00h
Device: 4
Bit
Attr
Default
7:0
RW
0h
Function: 0 - 7
Offset: 0Ch
Description
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for IIO is
always 64B. IIO hardware ignore this setting.
HDR
Bus: 0
220
Offset: 09h
Bit
CLSR
Bus: 0
3.4.2.8
Function: 0 - 7
Device: 4
Bit
Attr
Default
RO
1b
6:0
RO
00h
Function: 0 - 7
Offset: 0Eh
Description
Multi-function Device
Intel QuickData Technology is a MF device
Configuration Layout
This field identifies the format of the configuration header layout. It is Type 0 for
all these devices. The default is 00h, indicating an endpoint device.
3.4.2.9
CB_BAR
Bus: 0
3.4.2.10
Device: 4
Function: 0- 7
Offset: 10h
Bit
Attr
Default
Description
63:14
RW
0h
BAR
This marks the 16 KB aligned 64-bit base address for memory-mapped registers
of CB-DMA The BAR register in the 8 functions will be referenced with a logical
name of CB_BAR[0:7].
Note that accesses to registers pointed to by the CB_BAR, via JTAG mini-port are
not gated by the Memory Space Enable (MSE) bit in the PCICMD register of the
particular function. That is, accesses via these two paths (which are used for
internal Processor Microcode/microcode and JTAG) to the CB_BAR registers are
honored regardless of the setting of MSE bit.
13:4
RV
0h
Reserved
RO
0b
Prefetchable
The DMA registers are not prefetchable.
2:1
RO
10b
RO
0b
Type
The DMA registers is 64-bit address space and can be placed anywhere within the
addressable region of the system.
Memory Space
This Base Address Register indicates memory space.
3.4.2.11
Device: 4
Bit
Attr
Default
15:0
RW-O
8086h
Function: 0 - 7
Offset: 2Ch
Description
3.4.2.12
Device: 4
Bit
Attr
Default
15:0
RW-O
0000h
Function: 0 - 7
Offset: 2Eh
Description
221
CAPPTR
Bus: 0
3.4.2.13
Device: 4
Bit
Attr
Default
7:0
RW-O
60h
Function: 0 - 7
Offset: 34h
Description
Capability Pointer
Points to the first capability structure for the device.
3.4.2.14
Device: 4
Function: 0 - 7
Offset: 3Ch
Bit
Attr
Default
Description
7:0
RW
00h
Interrupt Line
This bit is RW for devices that can generate a legacy INTx message and is needed
only for compatibility purposes.
3.4.2.15
Device: 4
Bit
Attr
7:0
RW-O
Function: 0 - 7
Default
Offset: 3Dh
Description
Interrupt Pin
BIOS writes this register to specify an association between a Intel QuickData
Technology channel interrupt and a legacy interrupt pin INTA, INTB, INTC, or
INTD. Hardware will use this value to remap this channels legacy interrupt to the
legacy interrupt pin. OS will read this register to determine which virtual interrupt
pin this function uses.
01h: INTA
02h: INTB
03h: INTC
04h: INTD
Channel 0, 2, 4 and 6 share INTA, channels 1, 3, 5 and 7 share INTB.
Default is: 01h (Fn#0,2,4,6), 02h (Fn#1,3,5,7)
0_4_0_CFG: Attr: RW-O Default: 01h
0_4_1_CFG: Attr: RW-O Default: 02h
0_4_2_CFG: Attr: RW-O Default: 03h
0_4_3_CFG: Attr: RW-O Default: 04h
0_4_4_CFG: Attr: RW-O Default: 01h
0_4_5_CFG: Attr: RW-O Default: 02h
0_4_6_CFG: Attr: RW-O Default: 03h
0_4_7_CFG: Attr: RW-O Default: 04h
222
DEVCFG
Bus: 0
3.4.2.16
Device: 4
Function: 0
Offset: 60h
Bit
Attr
Default
Description
15:12
RWS
0h
Number of outstanding memory read requests for XOR with Galois Field
Multiply Operations
This register controls how many CL-size memory read requests for XOR with
Galois Field Multiply Descriptor Operations that the DMA engine can have
outstanding to main memory. Setting this field to 0h will allow maximum number
of reads to be outstanding. Setting this to a value other than 0h (max 15 or Fh)
will allow only that many memory reads to be outstanding.
11
RW-O
0b
10
RW-O
0b
RWS
0b
Enable No Snoop
This bit is akin to the NoSnoop enable bit in the PCI Express capability register,
only that this bit is controlled by BIOS rather than OS. When set, the no snoop
optimization is enabled (provided the equivalent bit in the PCI Express DEVCON
register is set) on behalf of Intel QuickData Technology otherwise it is not.
Note: Due to severe performance degradation, it is not recommended that this
bit be set except in debug mode.
7:4
RWS
0h
3:0
RWS
Fh
15:12
RWS
0h
Number of outstanding memory read requests for XOR with Galois Field
Multiply Operations
This register controls how many CL-size memory read requests for XOR with
Galois Field Multiply Descriptor Operations that the DMA engine can have
outstanding to main memory. Setting this field to 0h will allow maximum number
of reads to be outstanding. Setting this to a value other than 0h (max 15 or Fh)
will allow only that many memory reads to be outstanding.
MSIXCAPID
Bus: 0
Device: 4
Bit
Attr
Default
7:0
RO
11h
Function: 0 - 7
Offset: 80h
Description
Capability ID
Assigned by PCI-SIG for MSI-X (Intel QuickData Technology).
223
3.4.2.17
MSIXNXTPTR
Bus: 0
3.4.2.18
Default
Description
7:0
RO
90h
Next Ptr
This field is set to 90h for the next capability list (PCI Express capability structure)
in the chain.
Device: 4
Function: 0- 7
Offset: 82h
Bit
Attr
Default
15
RW
0b
MSI-X Enable
Software uses this bit to select between MSI-X or INTx method for signaling
interrupts from the DMA0: INTx method is chosen for DMA interrupts.
1: MSI-X method is chosen for DMA interrupts
14
RW
0b
Function Mask
If 1, the 1 vector associated with the dma is masked, regardless of the per-vector
mask bit state. If 0, the vectors mask bit determines whether the vector is
masked or not. Setting or clearing the MSI-X function mask bit has no effect on
the state of the per-vector Mask bit.
Description
13:11
RV
0h
Reserved
10:0
RO
0h
Table Size
Indicates the MSI-X table size which for IIO is 1, encoded as a value of 0h.
Device: 4
Bit
Attr
Default
31:3
RO
000004
00h
2:0
RO
0h
Function: 0 - 7
Offset: 84h
Description
Table Offset
MSI-X Table Structure is at offset 8K from the CB BAR address. See
Section 3.4.5.15, MSGADDR: MSI-X Lower Address Registers on page 253 for
the start of details relating to MSI-X registers.
Table BIR
Intel QuickData Technology BAR is at offset 10h in the DMA config space and
hence this register is 0.
PBAOFF_BIR
Bus: 0
224
Offset: 81h
Attr
TABLEOFF_BIR
Bus: 0
3.4.2.20
Function: 0 - 7
Bit
MSIXMSGCTL
Bus: 0
3.4.2.19
Device: 4
Device: 4
Bit
Attr
Default
31:3
RO
000006
00h
Function: 0 - 7
Offset: 88h
Description
Table Offset
MSI-X PBA Structure is at offset 12K from the CB BAR address. See
Section 3.4.5.19, PENDINGBITS: MSI-X Interrupt Pending Bits Registers on
page 254 for details.
PBAOFF_BIR
Bus: 0
3.4.2.21
Device: 4
Bit
Attr
Default
2:0
RO
0h
Function: 0 - 7
Offset: 88h
Description
Table BIR
Intel QuickData Technology BAR is at offset 10h in the DMA config space and
hence this register is 0.
3.4.2.22
Device: 4
Bit
Attr
Default
7:0
RO
10h
Function: 0 - 7
Offset: 90h
Description
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
3.4.2.23
Device: 4
Bit
Attr
Default
7:0
RO
E0h
Function: 0 - 7
Offset: 91h
Description
Next Ptr
This field is set to the PCI PM capability.
Device: 4
Attr
Function: 0 - 7
Default
15:14
RV
0h
13:9
RO
00h
RO
0b
7:4
RO
1001b
3:0
RO
2h
Offset: 92h
Description
Reserved
Interrupt Message Number
N/A
Slot Implemented
N/A
Device/Port Type
This field identifies the type of device. It is set to for the DMA to indicate root
complex integrated endpoint device.
Capability Version
This field identifies the version of the PCI Express capability structure. Set to 2h
for PCI Express and DMA devices for compliance with the extended base registers.
225
3.4.2.24
3.4.2.25
Device: 4
Attr
Function: 0 - 7
Offset: 94h
Default
Description
31:29
RV
0h
Reserved
28
RWS-O
0h
FLR supported
This bit is RW-O
27:26
RO
0h
25:18
RO
00h
17:16
RV
0h
Reserved
15
RO
1b
14
RO
0b
13
RO
0b
12
RO
0b
11:9
RO
000b
8:6
RO
000b
Reserved
RO
0b
4:3
RO
0h
2:0
RO
000b
226
Device: 4
Function: 0 - 7
Offset: 98h
Bit
Attr
Default
Description
15
RW
0h
14:12
RO
000b
11
RW
1b
Enable No Snoop
For Intel QuickData Technology, when this bit is clear, all DMA transactions must
be snooped. When set, DMA transactions to main memory can utilize No Snoop
optimization under the guidance of the device driver.
10
RO
0b
Initiate FLR
Intel QuickData Technology does a reset of that function only per the FLR ECN.
This bit always returns 0 when read and a write of 0 has no impact
Max_Read_Request_Size
N/A to Intel QuickData Technology since it does not issue tx on PCIe
DEVCON
Bus: 0
3.4.2.26
Device: 4
Function: 0 - 7
Offset: 98h
Bit
Attr
Default
Description
RO
0b
RO
0h
7:5
RO
000b
RW
0b
RO
0b
RO
0b
RO
0b
RO
0b
Device: 4
Function: 0 - 7
Offset: 9Ah
Bit
Attr
Default
Description
15:6
RV
0h
Reserved
RO
0h
Transactions Pending
1: indicates that the Intel QuickData Technology device has outstanding NonPosted Request which it has issued either towards main memory, which have not
been completed. 0: Intel QuickData Technology reports this bit cleared only when
all Completions for any outstanding Non-Posted Requests it owns have been
received.
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
227
3.4.2.27
DEVCAP2
Bus: 0
Bit
3.4.2.28
Device: 4
Offset: B4h
Attr
Default
31:5
RV
0h
Reserved
RO
1b
3:0
RO
0h
Description
DEVCON2
Bus: 0
3.4.2.29
Function: 0 - 7
Device: 4
Function: 0 - 7
Bit
Attr
Default
15:5
RV
0h
Reserved
RW
0b
3:0
RO
0h
Offset: B8h
Description
228
Device: 4
Function: 0 - 7
Offset: E0h
Bit
Attr
Default
Description
31:27
RO
0h
PME Support
26
RO
0b
D2 Support
IIO does not support power management state D2.
25
RO
0b
D1 Support
IIO does not support power management state D1.
24:22
RO
0h
AUX Current
21
RO
0b
20
RV
0h
Reserved
19
RO
0b
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16
RWS-O
011b
15:8
RO
00h
7:0
RO
01h
Capability ID
Provides the PM capability ID assigned by PCI-SIG.
Version
This field is set to 3h (PM 1.2 compliant) as version number. Bit is RW-O to make
the version 2h incase legacy OSes have any issues.
3.4.2.30
3.4.2.31
Device: 4
Function: 0 - 7
Offset: E4h
Bit
Attr
Default
Description
31:24
RO
00h
23
RO
0h
22
RO
0h
B2/B3 Support
This field is hardwired to 0h as it does not apply to PCI Express.
Data
Not relevant for IIO
21:16
RV
0h
Reserved
15
RO
0h
PME Status
14:13
RO
0h
Data Scale
12:9
RO
0h
Data Select
RO
0h
PME Enable
7:4
RV
0h
Reserved
RO
1b
No Soft Reset
Indicates IIO does not reset its registers when transitioning from D3hot to D0.
RV
0h
Reserved
1:0
RW
0h
Power State
This 2-bit field is used to determine the current power state of the function and to
set a new power state as well.
00: D0
01: D1 (not supported by IIO)
10: D2 (not supported by IIO)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not change
from the existing power state (which is either D0 or D3hot) and nor do these
bits1:0 change value.
Intel QuickData Technology will respond to only Type 0 configuration transactions
when in D3hot state and will not respond to memory transactions (that is, D3hot
state is equivalent to MSE/IOSE bits being clear).
DMAUNCERRSTS
Bus: 0
Device: 4
Function: 0
Offset: 148h
Bit
Attr
Default
Description
31:13
RV
0h
Reserved
12
RW1CS
0b
Syndrome
Multiple errors
11
RV
0h
Reserved
10
RW1CS
0b
9:8
RV
0h
Reserved
RW1CS
0b
6:5
RV
0h
Reserved
229
DMAUNCERRSTS
Bus: 0
3.4.2.32
Device: 4
Offset: 148h
Bit
Attr
Default
Description
RW1CS
0b
RW1CS
0b
RW1CS
0b
1:0
RV
0h
Reserved
DMAUNCERRMSK
Bus: 0
Device: 4
Bit
3.4.2.33
Function: 0
Function: 0
Attr
Default
31:13
RV
0h
Reserved
12
RWS
0b
Syndrome
Multiple errors
11
RV
0h
Reserved
Offset: 14Ch
Description
10
RWS
0b
9:8
RV
0h
Reserved
RWS
0b
6:5
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
1:0
RV
0h
Reserved
230
Function: 0
Attr
Default
31:13
RV
0h
Reserved
12
RWS
0b
Syndrome
Multiple errors
11
RV
0h
Reserved
Offset: 150h
Description
10
RWS
0b
9:8
RV
0h
Reserved
RWS
1b
6:5
RV
0h
Reserved
RWS
1b
RWS
1b
RWS
0b
DMAUNCERRSEV
Bus: 0
Device: 4
3.4.2.34
Bit
Attr
Default
1:0
RV
0h
Function: 0
Offset: 150h
Description
Reserved
3.4.2.35
Function: 0
Offset: 154h
Bit
Attr
Default
Description
7:5
RV
0h
Reserved
4:0
ROS-V
0h
UNCERRPTR
Points to the first unmasked uncorrectable error logged in the DMAUNCERRSTS
register. This field is only valid when the corresponding error is unmasked and the
status bit is set and this register is rearmed to load again once the error pointed
by this field in the uncorrectable error status register is cleared.Value of 0x0
corresponds to bit 0 in DMAUNCERRSTS register, value of 0x1 corresponds to bit 1
and so forth.
3.4.2.36
Attr
Device: 4
Function: 0
Default
Offset: 160h
Description
7:4
RV
0h
Reserved
3:0
ROS-V
0h
CHANERR_INT
Bus: 0
Device: 4
Bit
Attr
Default
31:19
RV
0h
Function: 0 - 7
Offset: 180h
Description
Reserved
231
CHANERR_INT
Bus: 0
Bit
Attr
18
Device: 4
Default
0b
Function: 0 - 7
Offset: 180h
Description
17
0b
XOR Q Error
The hardware sets this bit when the Q validation part of the XOR with Galois Field
Multiply Validate operation fails.
Notes:
This bit is RW1CS for functions 0-1 and RO for functions 2-7
256_1_4_Parent: Attr: RW1CS Default: 0b
0_4_0_CFG: Attr: RW1CS Default: 0b
0_4_1_CFG: Attr: RW1CS Default: 0b
0_4_2_CFG: Attr: RO Default: 0b
0_4_3_CFG: Attr: RO Default: 0b
0_4_4_CFG: Attr: RO Default: 0b
0_4_5_CFG: Attr: RO Default: 0b
0_4_6_CFG: Attr: RO Default: 0b
0_4_7_CFG: Attr: RO Default: 0b
232
16
RW1CS
0b
15
RO
0b
Unaffil_err
Unaffiliated Error. IIO never sets this bit
14
RO
0b
Reserved
13
RW1CS
0b
int_cfg_err
Interrupt Configuration Error. The DMA channel sets this bit indicating that the
interrupt registers were not configured properly when the DMA channel attempted
to generate an interrupt e.g. interrupt address is not 0xFEE.
12
RW1CS
0b
Cmp_addr_err
Completion Address Error. The DMA channel sets this bit indicating that the
completion address register was configured to an illegal address or has not been
configured.
11
RW1CS
0b
Desc_len_err
Descriptor Length Error. The DMA channel sets this bit indicating that the current
transfer has an illegal length field value. When this bit has been set, the address
of the failed descriptor is in the Channel Status register.
10
RW1CS
0b
Desc_ctrl_err
Descriptor Control Error. The DMA channel sets this bit indicating that the current
transfer has an illegal control field value. When this bit has been set, the address
of the failed descriptor is in the Channel Status register.
CHANERR_INT
Bus: 0
3.4.2.37
Device: 4
Function: 0 - 7
Offset: 180h
Bit
Attr
Default
Description
RW1CS
0b
Wr_data_err
Write Data Error. The DMA channel sets this bit indicating that the current transfer
has encountered an error while writing the destination data. This error could be
because of an internal ram error in the write queue that stores the write data
before being written to main memory. When this bit has been set, the address of
the failed descriptor is in the Channel Status register.
RW1CS
0b
Rd_data_err
Read Data Error. The DMA channel sets this bit indicating that the current transfer
has encountered an error while accessing the source data. This error could be a
read data that is received poisoned. When this bit has been set, the address of the
failed descriptor is in the Channel Status register.
RW1CS
0b
DMA_data_parerr
DMA Data Parity Error. The DMA channel sets this bit indicating that the current
transfer has encountered an uncorrectable ECC/parity error reported by the DMA
engine.
RW1CS
0b
Cdata_parerr
Data Parity Error. The DMA channel sets this bit indicating that the current transfer
has encountered a parity error. When this bit has been set, the address of the
failed descriptor is in the Channel Status register.
RW1CS
0b
Chancmd_err
CHANCMD Error. The DMA channel sets this bit indicating that a write to the
CHANCMD register contained an invalid value (e.g. more than one command bit
set).
RW1CS
0b
Chn_addr_valerr
Chain Address Value Error. The DMA channel sets this bit indicating that the
CHAINADDR register has an illegal address including an alignment error (not on a
64-byte boundary).
RW1CS
0b
Descriptor Error
The DMA channel sets this bit indicating that the current transfer has encountered
an error (not otherwise covered under other error bits) when reading or executing
a DMA descriptor. When this bit has been set and the channel returns to the
Halted state, the address of the failed descriptor is in the Channel Status register.
RW1CS
0b
Nxt_desc_addr_err
Next Descriptor Address Error. The DMA channel sets this bit indicating that the
current descriptor has an illegal next descriptor address including an alignment
error (not on a 64-byte boundary). When this bit has been set and the channel
returns to the Halted state, the address of the failed descriptor is in the Channel
Status register.
RW1CS
0b
DMA_xfrer_daddr_err
DMA Transfer Destination Address Error. The DMA channel sets this bit indicating
that the current descriptor has an illegal destination address. When this bit has
been set, the address of the failure descriptor has been stored in the Channel
Status register.
RW1CS
0b
DMA_trans_saddr_err
DMA Transfer Source Address Error. The DMA channel sets this bit indicating that
the current descriptor has an illegal source address. When this bit has been set,
the address of the failure descriptor has been stored in the Channel Status
register.
CHANERRMSK_INT
Bus: 0
Device: 4
Bit
Attr
Default
31:19
RV
0h
Function: 0 - 7
Offset: 184h
Description
Reserved
233
CHANERRMSK_INT
Bus: 0
Device: 4
Bit
3.4.2.38
Attr
Default
Offset: 184h
Description
18
0b
Bit Mask 18
This register is a bit for bit mask for the CHANERR_INT register
0: enable
1: disable
Notes:
This bit is RO in functions 2-7
0_4_0_CFG: Attr: RWS Default: 0b
0_4_1_CFG: Attr: RWS Default: 0b
0_4_2_CFG: Attr: RO Default: 0b
0_4_3_CFG: Attr: RO Default: 0b
0_4_4_CFG: Attr: RO Default: 0b
0_4_5_CFG: Attr: RO Default: 0b
0_4_6_CFG: Attr: RO Default: 0b
0_4_7_CFG: Attr: RO Default: 0b
17
0b
Bit Mask 17
This register is a bit for bit mask for the CHANERR_INT register
0: enable
1: disable
Notes:
This bit is RO in functions 2-7
0_4_0_CFG: Attr: RWS Default: 0b
0_4_1_CFG: Attr: RWS Default: 0b
0_4_2_CFG: Attr: RO Default: 0b
0_4_3_CFG: Attr: RO Default: 0b
0_4_4_CFG: Attr: RO Default: 0b
0_4_5_CFG: Attr: RO Default: 0b
0_4_6_CFG: Attr: RO Default: 0b
0_4_7_CFG: Attr: RO Default: 0b
16
RWS
0b
Bit Mask 16
This register is a bit for bit mask for the CHANERR_INT register
0: enable
1: disable
15
RO
0b
Reserved
Reserved
14
RV
0h
13:0
RWS
0000h
CHANERRSEV_INT
Bus: 0
Device: 4
234
Function: 0 - 7
Bit
Attr
Default
31:19
RV
0h
Function: 0 - 7
Offset: 188h
Description
Reserved
CHANERRSEV_INT
Bus: 0
Device: 4
Bit
Attr
18
Function: 0 - 7
Default
0b
Offset: 188h
Description
Severity 18
1: Corresponding error logged in the CHANERR_INT register is escalated as fatal
error to the IIO internal core error logic.
0: That error is escalated as non-fatal to the IIO internal core error logic.
Notes:
This bit is reserved for functions 2-7
0_4_0_CFG: Attr: RWS Default: 0b
0_4_1_CFG: Attr: RWS Default: 0b
0_4_2_CFG: Attr: RO Default: 0b
0_4_3_CFG: Attr: RO Default: 0b
0_4_4_CFG: Attr: RO Default: 0b
0_4_5_CFG: Attr: RO Default: 0b
0_4_6_CFG: Attr: RO Default: 0b
0_4_7_CFG: Attr: RO Default: 0b
17
0b
Severity 17
1: Corresponding error logged in the CHANERR_INT register is escalated as fatal
error to the IIO internal core error logic.
0: That error is escalated as non-fatal to the IIO internal core error logic.
Notes:
This bit is reserved for functions 2-7
0_4_0_CFG: Attr: RWS Default: 0b
0_4_1_CFG: Attr: RWS Default: 0b
0_4_2_CFG: Attr: RO Default: 0b
0_4_3_CFG: Attr: RO Default: 0b
0_4_4_CFG: Attr: RO Default: 0b
0_4_5_CFG: Attr: RO Default: 0b
0_4_6_CFG: Attr: RO Default: 0b
0_4_7_CFG: Attr: RO Default: 0b
16
3.4.2.39
RWS
0b
15:14
RO
00b
13:0
RWS
0000h
Severity 16
1: Corresponding error logged in the CHANERR_INT register is escalated as fatal
error to the IIO internal core error logic.
0: That error is escalated as non-fatal to the IIO internal core error logic.
Reserved
Severity 13:0
1: Corresponding error logged in the CHANERR_INT register is escalated as fatal
error to the IIO internal core error logic.
0: That error is escalated as non-fatal to the IIO internal core error logic.
CHANERRPTR
Bus: 0
Device: 4
Function: 0 - 7
Offset: 18Ch
Bit
Attr
Default
Description
7:5
RV
0h
Reserved
4:0
ROS-V
0h
235
3.4.3
Table 3-21. Intel QuickData Technology CB_BAR Registers (Replicated for Each
CB_BAR[0:7])
INTRCTRL
GENCTRL
XFERCAP
CHANCNT
0h
DMA_COMP
4h
DMACOUNT
CBVER
8h
ATTNSTATUS
CS_STATUS
INTRDELAY
DMACAPABILITY
DCAOFFSET
CHANCTRL
CHANCMD
88h
Ch
CHANSTS_1
8Ch
10h
CHAINADDR_0
90h
14h
CHAINADDR_1
94h
18h
CHANCMP_0
98h
1Ch
CHANCMP_1
9Ch
A0h
24h
236
84h
CHANSTS_0
20h
CBPRIO
80h
A4h
28h
CHANERR
A8h
2Ch
CHANERRMSK
ACh
30h
DCACTRL
B0h
34h
B4h
38h
B8h
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Table 3-22. Intel QuickData Technology CB_BAR Registers (Replicated for Each
CB_BAR[0:7])
DCA_REQID_OFFSET
DCA_VER
100h
DCA_REQID0
180h
104h
DCA_REQID1
184h
PCIE_CAPABILITY
QPI_CAPABILITY
108h
188h
PCIE_CAP_ENABLE
QPI_CAP_ENABLE
10Ch
18Ch
110h
190h
114h
194h
APICID_TAG_MAP
118h
198h
11Ch
19Ch
120h
1A0h
124h
1A4h
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
148h
1C8h
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
237
Table 3-23. Intel QuickData Technology CB_BAR MMIO Registers (replicated for each
CB_BAR[7:0]) - Offset 0x2000-0x20FF
Offset
MSGADDR
2000h
MSGUPRADDR
2004h
MSGDATA
2008h
VECCTRL
200Ch
2010h
2014h
2018h
201Ch
2020h
2024h
2028h
202Ch
2030h
2034h
2038h
203Ch
....
....
PENDINGBITS
3000h
....
....
....
1FFFh
3.4.4
238
All of these registers are accessible from only the processor. The IIO supports accessing
the CB device memory-mapped registers via QWORD reads and writes. The offsets
indicated in the following descriptions are from the CB_BAR value.
Table 3-24. DMA Memory Mapped Register Set Locations
Register Set
3.4.4.1
General Registers
0000h
Channel 0
0080h
3.4.4.2
Attr
Offset: 00h
Description
7:5
RV
0h
Reserved
4:0
RO
1h
num_chan
Number of channels. Specifies the number of DMA channels. The IIO supports 1
DMA Channel per function so this register will always read 1.
3.4.4.3
Bit
Attr
Default
7:5
RV
0h
4:0
RO
14h
Offset: 01h
Description
Reserved
Trans_size
Transfer size. This field specifies the number of bytes that may be specified in a
DMA descriptors Transfer Size field. This defines the maximum transfer size
supported by IIO as a power of 2.Intel Xeon Processor E5 Family will support 1M
max.
3.4.4.4
Bit
Attr
Default
7:1
RV
0h
Reserved
RW
0b
DbgEn
Offset: 02h
Description
239
INTRCTRL
Bus: 0
3.4.4.5
Offset: 03h
Bit
Attr
Default
7:4
RV
0h
Reserved
RW
0b
RO
0b
intp
Interrupt. This bit is set whenever the channel status bit in the Attention Status
register is set and the Master Interrupt Enable bit is set. That is, it is the logical
AND of Interrupt Status and Master Interrupt Enable bits of this register. This bit
represents the legacy interrupt drive signal (when in legacy interrupt mode). In
MSI-X mode, this bit is not used by software and is a dont care.
RO
0b
intp_sts
Interrupt Status. This bit is set whenever the bit in the Attention Status register is
set. This bit is not used by software in MSI-X mode and is a dont care.
RW
0b
Mstr_intp_En
Master Interrupt Enable. Setting this bit enables the generation of an interrupt in
legacy interrupt mode. This bit is automatically reset each time this register is
read. When this bit is clear ed, the IIO will not generate a legacy interrupt under
otherwise valid conditions. This bit is not used when DMA is in MSI-X mode.
Description
ATTNSTATUS
Bus: 0
Bit
3.4.4.6
Attr
Offset: 04h
Description
31:1
RV
0h
Reserved
RO-V
0h
ChanAttn
Channel Attention. Represents the interrupt status of the channel. This bit clears
when read. Writes have no impact on this bit.
CBVER: CB Version
The CB version register field indicates the version of the CB specification that the IIO
implements. The most significant 4-bits (range 7:4) are the major version number and
the least significant 4-bits (range 3:0) are the minor version number. The IIO
implementation for this Intel QuickData Technology version is 3.2 encoded as 0b0011
0010.
CBVER
Bus: 0
240
Offset: 08h
Bit
Attr
Default
Description
7:4
RO
3h
MJRVER
Major Version. Specifies Major version of the CB implementation. Current value is
2h
3:0
RO
2h
MNRVER
Minor Version. Specifies Minor version of the CB implementation. Current value is
0h
3.4.4.7
INTRDELAY
Bus: 0
3.4.4.8
Offset: 0Ch
Bit
Attr
Default
15
RO
1b
14
RV
0h
Reserved
13:0
RW
0h
Description
CS_STATUS
Bus: 0
Bit
3.4.4.9
Attr
Offset: 0Eh
Description
15:4
RV
0h
Reserved
RO
0b
Address Remapping
This bit reflects the TE bit of the non-VC1 Intel VT-d engine.
RO
0b
Memory Bypass
RO
0b
MMIO Restriction
RV
0h
Reserved
DMACAPABILITY
Bus: 0
MMIO BAR: CB_BAR [0:7]
Bit
Attr
31:10
RV
Default
Offset: 10h
Description
0h
Reserved
0b
241
DMACAPABILITY
Bus: 0
MMIO BAR: CB_BAR [0:7]
Offset: 10h
Bit
Attr
Default
Description
RO
0b
RO
1b
Extended APIC ID
Set if 32b APIC IDs are supported.
1: 32b APIC IDs supported
0: 8b APIC IDs supported
RO
1b
RO
1b
Move/CRC Supported
If set, specifies Move and CRC opcodes are supported. The opcodes are:
0x41 - Move and Generate CRC-32
0x42 - Move and Test CRC-32
0x43 - Move and Store CRC-32
Note:
When this bit is zero, the DMA engine will abort if it encounters a descriptor with
these opcodes.
RW-O
1b
RO
0b
XOR Supported
If set, specifies XOR opcodes are supported. Opcodes are:
0x85 - original XOR Generation
0x86 - original XOR Validate
Note:
These opcodes have been deprecated in Intel QuickData Technology v3.
The DMA engine will abort if it encounters a descriptor with these opcodes.
RO
1b
242
DMACAPABILITY
Bus: 0
MMIO BAR: CB_BAR [0:7]
Bit
Attr
Default
RO
1b
Offset: 10h
Description
RO
1b
3.4.4.10
DCAOFFSET
Bus: 0
3.4.4.11
Bit
Attr
Default
15:0
RO
0100h
Description
Points to where the general DCA registers are present
Bit
Attr
Default
7:0
RO
0h
Offset: 40h
Description
not used
DCA_VER
Bus: 0
3.4.4.13
Offset: 14h
CBPRIO
Bus: 0
3.4.4.12
Bit
Attr
Default
7:4
RO
1h
Major Revision
3:0
RO
0h
Minor Revision
Offset: 100h
Description
DCA_REQID_OFFSET
Bus: 0
MMIO BAR: CB_BAR [0:7]
Bit
Attr
Default
15:0
RO
0180h
Offset: 102h
Description
DCA Requester ID
Registers are at offset 180h
243
3.4.4.14
QPI_CAPABILITY
Bus: 0
MMIO BAR: CB_BAR [0:7]
Bit
3.4.4.15
Attr
Default
Description
15:1
RV
0h
Reserved
RO
1b
Prefetch Hint
IIO supports Prefetch Hint only method on the coherent interface
PCIE_CAPABILITY
Bus: 0
MMIO BAR: CB_BAR [0:7]
Bit
3.4.4.16
Default
Description
15:1
RV
0h
Reserved
RO
1b
MemWr
IIO supports only memory write method on PCI Express
Offset: 10Ch
Bit
Attr
Default
Description
15:1
RV
0h
Reserved
RW
0b
PCIE_CAP_ENABLE
Bus: 0
MMIO BAR: CB_BAR [0:7]
3.4.4.18
Offset: 10Ah
Attr
QPI_CAP_ENABLE
Bus: 0
MMIO BAR: CB_BAR [0:7]
3.4.4.17
Offset: 108h
Offset: 10Eh
Bit
Attr
Default
Description
15:1
RV
0h
Reserved
RW
0b
244
APICID_TAG_MAP
Bus: 0
MMIO BAR: CB_BAR [0:7]
3.4.5
Offset: 110h
Bit
Attr
Default
Description
63:40
RV
0h
39:32
RW
80h
Tag Map 4
This field is used by the Intel QuickData Technology engine to populate Tag field
bit 4 of the memory write transaction it issues with either 1, 0, or a selected
APICID bit.
[7:6]
00: Tag[4] = Tag_Map_4[0]
01: Tag[4] = APICID[ Tag_Map_4[3:0] ]
10: Tag[4] = NOT( APICID[ Tag_Map_4[3:0] ] )
11: reserved
31:24
RW
80h
Tag Map 3
This field is used by the Intel QuickData Technology engine to populate Tag field
bit 3 of the memory write transaction it issues with either 1, 0, or a selected
APICID bit.
[7:6]
00: Tag[3] = Tag_Map_3[0]
01: Tag[3] = APICID[ Tag_Map_3[3:0] ]
10: Tag[3] = NOT( APICID[ Tag_Map_3[3:0] ] )
11: reserved
23:16
RW
80h
Tag Map 2
This field is used by the Intel QuickData Technology engine to populate Tag field
bit 2 of the memory write transaction it issues with either 1, 0, or a selected
APICID bit.
[7:6]
00: Tag[2] = Tag_Map_2[0]
01: Tag[2] = APICID[ Tag_Map_2[3:0] ]
10: Tag[2] = NOT( APICID[ Tag_Map_2[3:0] ] )
11: reserved
15:8
RW
80h
Tag Map 1
This field is used by the Intel QuickData Technology engine to populate Tag field
bit 1 of the memory write transaction it issues with either 1, 0, or a selected
APICID bit.
[7:6]
00: Tag[1] = Tag_Map_1[0]
01: Tag[1] = APICID[ Tag_Map_1[3:0] ]
10: Tag[1] = NOT( APICID[ Tag_Map_1[3:0] ] )
11: reserved
7:0
RW
80h
Tag Map 0
This field is used by the Intel QuickData Technology engine to populate Tag field
bit 0 of the memory write transaction it issues with either 1, 0, or a selected
APICID bit.
[7:6]
00: Tag[0] = Tag_Map_0[0]
01: Tag[0] = APICID[ Tag_Map_0[3:0] ]
10: Tag[0] = NOT( APICID[ Tag_Map_0[3:0] ] )
11: reserved
Reserved
245
3.4.5.1
246
Offset: 80h
Attr
Default
Description
15:10
RV
0h
Reserved
RW-L
0b
RW-LV
0b
In_use
In Use. This bit indicates whether the DMA channel is in use. The first time this bit
is read after it has been cleared, it will return 0 and automatically transition from
0 to 1, reserving the channel for the first consumer that reads this register. All
subsequent reads will return 1 indicating that the channel is in use. This bit is
cleared by writing a 0 value, thus releasing the channel. A consumer uses this
mechanism to atomically claim exclusive ownership of the DMA channel. This
should be done before attempting to program any register in the DMA channel
register set. This field is RW if CHANCNT register is 1 otherwise this register is RO.
7:6
RV
0h
Reserved
RW-L
0b
Desc_addr_snp_ctrl
Descriptor address snoop control. 1: When set, this bit indicates that the
descriptors are not in coherent space and should not be snooped.
0: When cleared, the descriptors are in coherent space and each descriptor
address must be snooped on Intel QPI.
This field is RW if CHANCNT register is 1 otherwise this register is RO.
RW-L
0b
Err_Int_En
Error Interrupt Enable. This bit enables the DMA channel to generate an interrupt
(MSI or legacy) when an error occurs during the DMA transfer. If Any Error Abort
Enable (see below) is not set, then unaffiliated errors do not cause an
interrupt.This field is RW if CHANCNT register is 1 otherwise this register is RO.
RW-L
0b
AnyErr_Abrt_En
Any Error Abort Enable. This bit enables an abort operation when any error is
encountered during the DMA transfer. When the abort occurs, the DMA channel
generates an interrupt and a completion update as per the Error Interrupt Enable
and Error Completion Enable bits. When this bit is reset, only affiliated errors
cause the DMA channel to abort.This field is RW if CHANCNT register is 1
otherwise this register is RO.
RW-L
0b
Err_Cmp_En
Error Completion Enable. This bit enables a completion write to the address
specified in the CHANCMP register upon encountering an error during the DMA
transfer. If Any Error Abort is not set, then unaffiliated errors do not cause a
completion write.This field is RW if CHANCNT register is 1 otherwise this register is
RO.
RV
0h
Reserved
RW1C
0b
Intp_Dis
Interrupt Disable. Upon completing a descriptor, if an interrupt is specified for that
descriptor and this bit is reset, then the DMA channel generates an interrupt and
sets this bit. The choice between MSI or legacy interrupt mode is determined with
the MSICTRL register. Legacy interrupts are further gated through intxDisable in
thePCICMD register of the Intel QuickData Technology PCI configuration space.
The controlling process can re-enable this channels interrupt by writing a one to
this bit, which clears the bit. Writing a zero has no effect. Thus, each time this bit
is reset, it enables the DMA channel to generate one interrupt.
3.4.5.2
DMA_COMP
Bus: 0
Bit
3.4.5.3
Attr
Offset: 82h
Default
Description
15:3
RV
0h
Reserved
RO
1b
v3 Compatibility
Compatible with version 3 CB spec
RO
1b
v2 Compatibility
Compatible with version 2 CB spec
RO
0b
v1 Compatibility
Not compatible with version 1
3.4.5.4
Offset: 84h
Bit
Attr
Default
7:6
RV
0h
Reserved
RW-LV
0b
Reset DMA
Set this bit to reset the DMA channel. Setting this bit is a last resort to recover the
DMA channel from a programming error or other problem such as dead lock from
cache coherency protocol. Execution of this command does not generate an
interrupt or generate status. This command causes the DMA channel to return to a
known state (Halted).This field is RW if CHANCNT register is 1 otherwise this
register is RO.
4:3
RV
0h
Reserved
RW-LV
0b
Susp_DMA
Suspend DMA. Set this bit to suspend the current DMA transfer. This field is RW if
CHANCNT register is 1 otherwise this register is RO.
1:0
RV
0h
Reserved
Description
DMACOUNT
Bus: 0
3.4.5.5
Offset: 86h
Bit
Attr
Default
Description
15:0
RW-L
0000h
247
CHANSTS_0
Bus: 0
3.4.5.6
Offset: 88h
Bit
Attr
Default
Description
31:6
RO
000000
0h
5:3
RV
0h
2:0
RO
011b
Reserved
DMA_trans_state
DMA Transfer Status. The DMA engine sets these bits indicating the state of the
current DMA transfer. The cause of an abort can be either error during the DMA
transfer or invoked by the controlling process via the CHANCMD register.000 Active
001 - Idle, DMA Transfer Done (no hard errors)
010 - Suspended
011 - Halted, operation aborted (refer to Channel Error register for further detail)
100 - Armed
3.4.5.7
Offset: 8Ch
Bit
Attr
Default
Description
31:0
RO
000000
00h
3.4.5.8
Offset: 90h
Bit
Attr
Default
Description
31:0
RW-L
000000
00h
248
CHAINADDR_1
Bus: 0
3.4.5.9
Offset: 94h
Bit
Attr
Default
Description
31:0
RW-L
000000
00h
3.4.5.10
Offset: 98h
Bit
Attr
Default
Description
31:3
RW-L
000000
00h
2:0
RV
0h
Reserved
3.4.5.11
Offset: 9Ch
Bit
Attr
Default
Description
31:0
RW-L
000000
00h
249
CHANERR
Bus: 0
Offset: A8h
Bit
Attr
Default
31:19
RV
0h
Reserved
0b
18
Description
Note:
This bit is RW1CS for functions 0-1 and RO for functions 2-7
0_4_0_CB_BAR: Attr: RW1CS Default: 0b
0_4_1_CB_BAR: Attr: RW1CS Default: 0b
0_4_2_CB_BAR: Attr: RO Default: 0b
0_4_3_CB_BAR: Attr: RO Default: 0b
0_4_4_CB_BAR: Attr: RO Default: 0b
0_4_5_CB_BAR: Attr: RO Default: 0b
0_4_6_CB_BAR: Attr: RO Default: 0b
0_4_7_CB_BAR: Attr: RO Default: 0b
17
0b
XOR Q Error
The hardware sets this bit when the Q validation part of the
XOR with Galois Field Multiply Validate operation fails.
Note:
This bit is RW1CS for functions 0-1 and RO for functions 2-7
0_4_0_CB_BAR: Attr: RW1CS Default: 0b
0_4_1_CB_BAR: Attr: RW1CS Default: 0b
0_4_2_CB_BAR: Attr: RO Default: 0b
0_4_3_CB_BAR: Attr: RO Default: 0b
0_4_4_CB_BAR: Attr: RO Default: 0b
0_4_5_CB_BAR: Attr: RO Default: 0b
0_4_6_CB_BAR: Attr: RO Default: 0b
0_4_7_CB_BAR: Attr: RO Default: 0b
250
16
RW1CS
0b
15
RO
0b
Unaffil_err
Unaffiliated Error. IIO never sets this bit
14
RV
0h
Reserved
13
RW1CS
0b
int_cfg_err
Interrupt Configuration Error. The DMA channel sets this bit indicating that the
interrupt registers were not configured properly when the DMA channel attempted
to generate an interrupt. E.g. interrupt address is not 0xFEE.
12
RW1CS
0b
Cmp_addr_err
Completion Address Error. The DMA channel sets this bit indicating that the
completion address register was configured to an illegal address or has not been
configured.
11
RW1CS
0b
Desc_len_err
Descriptor Length Error. The DMA channel sets this bit indicating that the current
transfer has an illegal length field value. When this bit has been set, the address
of the failed descriptor is in the Channel Status register.
10
RW1CS
0b
Desc_ctrl_err
Descriptor Control Error. The DMA channel sets this bit indicating that the current
transfer has an illegal control field value. When this bit has been set, the address
of the failed descriptor is in the Channel Status register.
CHANERR
Bus: 0
3.4.5.12
Offset: A8h
Bit
Attr
Default
Description
RW1CS
0b
Wr_data_err
Write Data Error. The DMA channel sets this bit indicating that the current transfer
has encountered an error while writing the destination data. This error could be
because of an internal ram error in the write queue that stores the write data
before being written to main memory. When this bit has been set, the address of
the failed descriptor is in the Channel Status register.
RW1CS
0b
Rd_data_err
Read Data Error. The DMA channel sets this bit indicating that the current transfer
has encountered an error while accessing the source data. This error could be a
read data that is received poisoned. When this bit has been set, the address of the
failed descriptor is in the Channel Status register.
RW1CS
0b
DMA_data_parerr
DMA Data Parity Error. The DMA channel sets this bit indicating that the current
transfer has encountered an uncorrectable ECC/parity error reported by the DMA
engine.
RW1CS
0b
Cdata_parerr
Chipset Data Parity Error. The DMA channel sets this bit indicating that the current
transfer has encountered a parity error reported by the chipset. When this bit has
been set, the address of the failed descriptor is in the Channel Status register.
RW1CS
0b
Chancmd_err
CHANCMD Error. The DMA channel sets this bit indicating that a write to the
CHANCMD register contained an invalid value (e.g. more than one command bit
set).
RW1CS
0b
Chn_addr_valerr
Chain Address Value Error. The DMA channel sets this bit indicating that the
CHAINADDR register has an illegal address including an alignment error (not on a
64-byte boundary).
RW1CS
0b
Descriptor Error
The DMA channel sets this bit indicating that the current transfer has encountered
an error (not otherwise covered under other error bits) when reading or executing
a DMA descriptor. When this bit has been set and the channel returns to the
Halted state, the address of the failed descriptor is in the Channel Status register.
RW1CS
0b
Nxt_desc_addr_err
Next Descriptor Address Error. The DMA channel sets this bit indicating that the
current descriptor has an illegal next descriptor address including an alignment
error (not on a 64-byte boundary). When this bit has been set and the channel
returns to the Halted state, the address of the failed descriptor is in the Channel
Status register.
RW1CS
0b
DMA_xfrer_daddr_err
DMA Transfer Destination Address Error. The DMA channel sets this bit indicating
that the current descriptor has an illegal destination address. When this bit has
been set, the address of the failure descriptor has been stored in the Channel
Status register.
RW1CS
0b
DMA_trans_saddr_err
DMA Transfer Source Address Error. The DMA channel sets this bit indicating that
the current descriptor has an illegal source address. When this bit has been set,
the address of the failure descriptor has been stored in the Channel Status
register.
CHANERRMSK
Bus: 0
Bit
Attr
Default
31:19
RV
0h
Offset: ACh
Description
Reserved
251
CHANERRMSK
Bus: 0
Bit
Attr
18
Offset: ACh
Description
Bit Mask 18
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
Note:
This bit is RO in functions 2-7
0_4_0_CB_BAR: Attr: RWS Default: 0b
0_4_1_CB_BAR: Attr: RWS Default: 0b
0_4_2_CB_BAR: Attr: RO Default: 0b
0_4_3_CB_BAR: Attr: RO Default: 0b
0_4_4_CB_BAR: Attr: RO Default: 0b
0_4_5_CB_BAR: Attr: RO Default: 0b
0_4_6_CB_BAR: Attr: RO Default: 0b
0_4_7_CB_BAR: Attr: RO Default: 0b
17
0b
Bit Mask 17
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
Note:
This bit is RO in functions 2-7
0_4_0_CB_BAR: Attr: RWS Default: 0b
0_4_1_CB_BAR: Attr: RWS Default: 0b
0_4_2_CB_BAR: Attr: RO Default: 0b
0_4_3_CB_BAR: Attr: RO Default: 0b
0_4_4_CB_BAR: Attr: RO Default: 0b
0_4_5_CB_BAR: Attr: RO Default: 0b
0_4_6_CB_BAR: Attr: RO Default: 0b
0_4_7_CB_BAR: Attr: RO Default: 0b
3.4.5.13
16
RWS
0b
Bit Mask 16
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
15:14
RV
0h
Reserved
13:0
RWS
0000h
DCACTRL
Bus: 0
252
Bit Mask 13
This register is a bit for bit mask for the CHANERR register
0: enable
1: disable
Offset: B0h
Bit
Attr
Default
Description
31:16
RV
0h
Reserved
15:0
RW-L
0h
3.4.5.14
DCA_REQID[0:1]
Bus: 0
MMIO BAR: CB_BAR [0:7]
3.4.5.15
Bit
Attr
Default
Description
31
RO
0b
Last
This bit is set only in the last RequesterID register for this port. Thus, it identifies
that this is the last DCA RequesterID register for this port.
30
RV
0h
Reserved
29
RW
0b
Valid
when set the requester id programed into bits 15:0 is used by hardware for DCA
write identification, otherwise the bits are ignored.
28
RW
0b
27:16
RV
0h
Reserved
15:8
RW
0h
Bus Number
PCI bus number of the DCA requester
7:3
RW
0h
Device Number
Device number of the day requester
2:0
RW
0b
Function Number
Function number of the day requester
MSGADDR
Bus: 0
3.4.5.16
Offset: 2000h
Bit
Attr
Default
Description
31:20
RW
0h
Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address. This field
is R/W for compatibility reasons only.
19:2
RW
0h
Address
Specifies the local APIC to which this MSI-X interrupt needs to be sent
1:0
RV
0h
Reserved
MSGUPRADDR
Bus: 0
Bit
Attr
Default
31:0
RW
0h
Offset: 2004h
Description
253
3.4.5.17
MSGDATA
Bus: 0
3.4.5.18
Attr
Default
Description
31:0
RW
0h
MSI Data
Specifies the vector that needs to be used for interrupts from the DMA engine. IIO
uses the lower 16 bits of this field to form the data portion of the interrupt on the
coherent interface. The upper 16 bits are not used by IIO and left as RW only for
compatibility reasons.
Offset: 200Chh
Bit
Attr
Default
31:1
RV
0h
Reserved
RW
1b
Mask
When a bit is set, the channel is prohibited from sending a message, even if all
other internal conditions for interrupt generation are valid.
Description
PENDINGBITS
Bus: 0
3.5
Offset: 2008h
Bit
VECCTRL
Bus: 0
3.4.5.19
Bit
Attr
Default
31:1
RO
000000
00h
RW-V
0b
Offset: 3000h
Description
254
3.5.1
Table 3-25. Intel VT, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 0x000-0x0FF
DID
VID
00h
HDRTYPECTRL
80h
PCISTS
PCICMD
04h
MMCFG
84h
CCR
RID
08h
88h
HDR
CLSR
0Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
SDID
SVID
30h
CAPPTR1
34h
INTPIN
INTL
3Ch
PXPNXTPTR
PXPCAPID
40h
38h
PXPCAP
PCIe-Reserved
TSEG
2Ch
GENPROTRANGE1_BASE
B0h
B4h
GENPROTRANGE1_LIMIT
B8h
BCh
GENPROTRANGE2_BASE
44h
48h
A8h
ACh
C0h
C4h
GENPROTRANGE2_LIMIT
4Ch
C8h
CCh
50h
TOLM
D0h
54h
TOHM
D4h
58h
D8h
5Ch
DCh
60h
NCMEM_BASE
64h
68h
NCMEM_LIMIT
6Ch
70h
E8h
ECh
MENCMEM_BASE
74h
78h
E0h
E4h
F0h
F4h
MENCMEM_LIMIT
7Ch
F8h
FCh
Notes:
1. CAPPTR points to the first capability block
255
Table 3-26. Intel VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 0x100-0x1FF
100h
VTBAR
104h
180h
VTGENCTRL
184h
CPUBUSNO
108h
VTISOCHCTRL
188h
LMMIOL
10Ch
VTGENCTRL2
18Ch
LMMIOH_BASE
LMMIOH_LIMIT
GENPROTRANGE0_BASE
GENPROTRANGE0_LIMIT
110h
114h
190h
IOTLBPARTITION
118h
198h
11Ch
19Ch
120h
1A0h
124h
1A4h
128h
VTUNCERRSTS
1A8h
12Ch
VTUNCERRMSK
1ACh
130h
VTUNCERRSEV
134h
1B8h
1BCh
140h
144h
CIPINTRS
1B4h
138h
CIPSTS
CIPINTRC
1B0h
VTUNCERRPTR
13Ch
CIPCTRL
CIPDCASAD
194h
IIOMISCCTRL
1C0h
1C4h
148h
1C8h
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
Table 3-27. Intel VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 0x200-0x2FF (Sheet 1 of 2)
200h
280h
204h
284h
208h
288h
20Ch
28Ch
210h
214h
256
LTDPR
290h
294h
Table 3-27. Intel VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 0x200-0x2FF (Sheet 2 of 2)
218h
298h
21Ch
29Ch
220h
2A0h
224h
2A4h
228h
2A8h
22Ch
2ACh
230h
2B0h
234h
2B4h
238h
2B8h
23Ch
2BCh
240h
2C0h
244h
2C4h
248h
2C8h
24Ch
2CCh
250h
2D0h
254h
2D4h
258h
2D8h
25Ch
2DCh
260h
2E0h
264h
2E4h
268h
2E8h
26Ch
2ECh
270h
2F0h
274h
2F4h
278h
2F8h
27Ch
2FCh
Table 3-28. Intel VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 0x800-0x8FF (Sheet 1 of 2)
IRP_MISC_DFX0
IRP_MISC_DFX1
IRP0DELS
IRP1DELS
IRP0DBGRING0
IRP1DBGRING0
IRPSPARER
EGS
IRP1DBGRI
NG1
IRP0RNG
IRP0DBGRI
NG1
800h
880h
804h
884h
808h
888h
80Ch
88Ch
810h
890h
814h
894h
818h
898h
81Ch
89Ch
820h
8A0h
824h
8A4h
828h
8A8h
82Ch
8ACh
830h
8B0h
257
Table 3-28. Intel VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 0x800-0x8FF (Sheet 2 of 2)
IRP1RNG
IRPEGCREDITS
258
834h
8B4h
838h
8B8h
83Ch
8BCh
840h
8C0h
844h
8C4h
848h
8C8h
84Ch
8CCh
850h
8D0h
854h
8D4h
858h
8D8h
85Ch
8DCh
860h
8E0h
864h
8E4h
868h
8E8h
86Ch
8ECh
870h
8F0h
874h
8F4h
878h
8F8h
87Ch
8FCh
Table 3-29. IIO Control/Status & Global Error Register Map - Device 5, Function 2: Offset
0x0-0xFF
DID
VID
0h
PCISTS
PCICMD
04h
CCR
RID
08h
HDR
CLSR
0Ch
80h
IRPPERRSV
84h
88h
IIOERRSV
8Ch
10h
MIERRSV
90h
14h
PCIERRSV
94h
SYSMAP
9Ch
18h
1Ch
SDID
SVID
20h
VIRAL
A0h
24h
ERRPINCTL
A4h
28h
ERRPINST
A8h
2Ch
ERRPINDAT
ACh
30h
CAPPTR1
34h
INTPIN
INTL
3Ch
PXPNXTPTR
PXPCAPID
40h
38h
PXPCAP
PCIe RESERVED
98h
B0h
VPPCTL
B4h
VPPSTS
B8h
BCh
VPPFREQ
C0h
44h
48h
C4h
VPP_INVER
TS
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Notes:
1. CAPPTR points to the first capability block.
259
Table 3-30. IIO Control/Status & Global Error Register Map - Device 5, Function 2: Offset
0x100-0x1FF
RESERVED PCIe Header space
100h
180h
104h
184h
108h
188h
10Ch
18Ch
110h
190h
114h
194h
118h
198h
11Ch
19Ch
120h
1A0h
124h
1A4h
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
GNERRST
1C0h
144h
GFERRST
1C4h
148h
GERRCTL
1C8h
14Ch
GSYSST
1CCh
150h
GSYSCTL
154h
158h
15Ch
1D8h
GFFERRST
1DCh
160h
1E0h
164h
1E4h
168h
GFNERRST
1E8h
16Ch
GNFERRST
1ECh
170h
1F0h
174h
1F4h
178h
17Ch
260
1D0h
1D4h
GNNERRST
1F8h
1FCh
Table 3-31. IIO Local Error Map - Device 5, Function 2: Offset 0x200h-0x2FFh
200h
280h
204h
284h
208h
288h
20Ch
28Ch
210h
290h
214h
294h
218h
298h
21Ch
29Ch
220h
2A0h
224h
2A4h
228h
2A8h
22Ch
IRPP0ERRST
230h
2ACh
IRPP1ERRST
2B0h
IRPP0ERRCTL
234h
IRPP1ERRCTL
2B4h
IRPP0FFERRST
238h
IRPP1FFERRST
2B8h
IRPP0FNERRST
23Ch
IRPP1FNERRST
2BCh
IRPP0FFERRHD0
240h
IRPP1FFERRHD0
2C0h
IRPP0FFERRHD1
244h
IRPP1FFERRHD1
2C4h
IRPP0FFERRHD2
248h
IRPP1FFERRHD2
2C8h
IRPP0FFERRHD3
24Ch
IRPP1FFERRHD3
2CCh
IRPP0NFERRST
250h
IRPP1NFERRST
2D0h
IRPP0NNERRST
254h
IRPP1NNERRST
2D4h
IRPP0NFERRHD0
258h
IRPP1NFERRHD0
2D8h
IRPP0NFERRHD1
25Ch
IRPP1NFERRHD1
2DCh
IRPP0NFERRHD2
260h
IRPP1NFERRHD2
2E0h
IRPP0NFERRHD3
264h
IRPP1NFERRHD3
2E4h
IRPP0ERRCNTSEL
268h
IRPP1ERRCNTSEL
2E8h
IRPP0ERRCNT
26Ch
IRPP1ERRCNT
2ECh
270h
2F0h
274h
2F4h
278h
2F8h
27Ch
2FCh
261
Table 3-32. IIO Local Error Map - Device 5, Function 2: Offset 0x300-0x3FF
IIOERRST
300h
MIERRST
380h
IIOERRCTL
304h
MIERRCTL
384h
IIOFFERRST
308h
MIFFERRST
388h
IIOFFERRHD0
30Ch
MIFFERRHDR_0
38Ch
IIOFFERRHD1
310h
MIFFERRHDR_1
390h
IIOFFERRHD2
314h
MIFFERRHDR_2
394h
IIOFFERRHD3
318h
MIFFERRHDR_3
398h
IIOFNERRST
31Ch
MIFNERRST
39Ch
IIONFERRST
320h
MINFERRST
3A0h
IIONFERRHD0
324h
MINFERRHDR_0
3A4h
IIONFERRHD1
328h
MINFERRHDR_1
3A8h
IIONFERRHD2
32Ch
MINFERRHDR_2
3ACh
IIONFERRHD3
330h
MINFERRHDR_3
3B0h
IIONNERRST
334h
MINNERRST
338h
3B4h
3B8h
IIOERRCNTSEL
33Ch
MIERRCNTSEL
3BCh
IIOERRCNT
340h
MIERRCNT
3C0h
344h
3C4h
348h
3C8h
34Ch
3CCh
350h
3D0h
354h
3D4h
358h
3D8h
35Ch
3DCh
360h
3E0h
364h
3E4h
368h
3E8h
36Ch
3ECh
370h
3F0h
374h
3F4h
378h
3F8h
37Ch
3FCh
Table 3-33. I/OxAPIC PCI Configuration Space Map - Device 5/Function 4: Offset 0x000xFF (Sheet 1 of 2)
DID
VID
0h
PCISTS
PCICMD
4h
RDINDEX
CCR
RID
8h
88h
HDR
CLSR
Ch
8Ch
MBAR
10h
RDWINDOW
14h
90h
94h
18h
98h
1Ch
9Ch
20h
262
80h
84h
IOAPICTETPC
A0h
Table 3-33. I/OxAPIC PCI Configuration Space Map - Device 5/Function 4: Offset 0x000xFF (Sheet 2 of 2)
SDID
SVID
CAPPTR
INTPIN
INTL
ABAR
PXPCAP
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
34h
B4h
38h
B8h
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
PMCAP
6Ch
ECh
PMCSR
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Table 3-34. I/OxAPIC PCI Configuration Space Map - Device 5/Function 4:Offset 0x2000x2FF (Sheet 1 of 2)
200h
280h
204h
284h
208h
IOADSELS0
288h
20Ch
IOADSELS1
28Ch
210h
290h
214h
294h
218h
298h
21Ch
29Ch
220h
IOINTSRC0
2A0h
224h
IOINTSRC1
2A4h
228h
IOREMINTCNT
2A8h
22Ch
IOREMGPECNT
2ACh
230h
2B0h
234h
2B4h
238h
2B8h
23Ch
2BCh
263
Table 3-34. I/OxAPIC PCI Configuration Space Map - Device 5/Function 4:Offset 0x2000x2FF (Sheet 2 of 2)
240h
IOXAPICPARERRINJCTL
2C0h
244h
FAUXGV
2C4h
248h
2C8h
24Ch
2CCh
250h
2D0h
254h
2D4h
258h
2D8h
25Ch
2DCh
260h
2E0h
264h
2E4h
268h
2E8h
26Ch
2ECh
270h
2F0h
274h
2F4h
278h
2F8h
27Ch
2FCh
3.5.2
3.5.2.1
VID
Bus: 0
3.5.2.2
Device: 5
Bit
Attr
Default
15:0
RO
8086h
Offset: 00h
Description
DID
Bus: 0
264
Function: 0,2,4,
Device: 5
Bit
Attr
Default
15:0
RO
3C28h
Function: 0,2,4
Offset: 02h
Description
3.5.2.3
3.5.2.4
Device: 5
Attr
Function: 0,2,4
Default
Offset: 04h
Description
15:11
RV
0h
Reserved
10
RO
0b
INTx Disable
N/A for these devices
RO
0b
RO
0b
SERR Enable
This bit has no impact on error reporting from these devices
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
IO Space Enable
Hardwired to 0 since these devices dont decode any IO BARs
Device: 5
Function: 0,2,4
Offset: 06h
Bit
Attr
Default
Description
15
RO
0b
14
RO
0b
13
RO
0b
265
PCISTS
Bus: 0
3.5.2.5
Device: 5
Function: 0,2,4
Offset: 06h
Bit
Attr
Default
Description
12
RO
0b
11
RO
0b
10:9
RO
0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
RO
0b
RO
0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
RV
0h
Reserved
RO
0b
RO
1b
Capabilities List
This bit indicates the presence of a capabilities list structure
RO
0b
INTx Status
Hardwired to 0
2:0
RV
0h
Reserved
3.5.2.6
Device: 5
Bit
Attr
Defau
lt
7:0
RO
00h
Function: 0,2,4
Offset: 08h
Description
Revision_ID
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in
any Intel Xeon Processor E5 Family function.
Implementation Note:
Read and write requests from the host to any RID register in any Intel Xeon Processor
E5 Family Intel QPI function are re-directed to the IIO cluster. Accesses to the CCR
field are also redirected due to DWORD alignment. It is possible that JTAG accesses
are direct, so will not always be redirected.
266
Device: 5
Bit
Attr
Default
23:16
RO
08h
Function: 0,2,4
Offset: 09h
Description
Base Class
For almost all IIO device/functions this field is hardwired to 06h, indicating it is a
Bridge Device. Non-bridge generic devices use a value of 08h, indicating it is a
Generic System Peripheral.
CCR
Bus: 0
3.5.2.7
Device: 5
Offset: 09h
Bit
Attr
Default
Description
15:8
RO
80h
Sub-Class
For almost all IIO device/functions, this field defaults to 00h indicating host bridge.
Non-bridge devices use a value of 80h.
7:0
RO
00h
CLSR
Bus: 0
3.5.2.8
Function: 0,2,4
Device: 5
Function: 0,2,4
Offset: 0Ch
Bit
Attr
Default
Description
7:0
RW
0h
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for Intel
Xeon Processor E5 Family is always 64B.
3.5.2.9
Device: 5
Function: 0,2,4
Offset: 0Eh
Bit
Attr
Default
Description
RO
1b
Multi-function Device
This bit defaults to 1b since all these devices are multi-function For Dev#4, 6, 7,
BIOS can individually control the value of this bit in function#0 of these devices,
based on HDRTYPECTRL register. BIOS will set these control bits to change this
field to 0 in function#0 of these devices, if it exposes only function 0 in the device
to OS.
6:0
RO
00h
Configuration Layout
This field identifies the format of the configuration header layout. It is Type 0 for
all these devices. The default is 00h, indicating an endpoint device.
RO
1b
Multi-function Device
This bit defaults to 1b since all these devices are multi-function. For Dev#4, 6, 7,
BIOS can individually control the value of this bit in function#0 of these devices,
based on HDRTYPECTRL register. BIOS will set these control bits to change this
field to 0 in function#0 of these devices, if it exposes only function 0 in the device
to OS.
SVID
Bus: 0
Device: 5
Bit
Attr
Defau
lt
15:0
RW-O
8086h
Function: 0, 2,4
Offset: 2Ch
Description
267
3.5.2.10
SCID
Bus: 0
3.5.2.11
Device: 5
Bit
Attr
Default
15:0
RW-O
00h
Function: 0,2,4
Offset: 2Eh
Description
3.5.2.12
Device: 5
Bit
Attr
Default
7:0
RO
Dev 5, F
0,2=
40h
Dev 5,
F4 =
44h
Function: 0,2,4
Offset: 34h
Description
Capability Pointer
Points to the first capability structure for the device which is the PCIe capability.
3.5.2.13
Device: 5
Bit
Attr
Default
7:0
RO
00h
Offset: 3Ch
Description
Interrupt Line
N/A for these devices
INTPIN
Bus: 0
3.5.2.14
Function: 0,2
Device: 5
Bit
Attr
Default
7:0
RO
00h
Function: 0,2
Offset: 3Dh
Description
Interrupt Pin
N/A since these devices do not generate any interrupt on their own
268
PXPCAPID
Bus: 0
3.5.2.15
Device: 5
Bit
Attr
Default
7:0
RO
10h
Function: 0, 2
Offset: 40h
Description
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
3.5.2.16
Device: 5
Bit
Attr
Default
7:0
RO
E0h
Function: 0,2
Offset: 41h
Description
Next Ptr
This field is set to the PCI PM capability.
Device: 5
Bit
Attr
Defau
lt
15:1
4
RV
0h
13:9
RO
00h
RO
0b
7:4
RO
1001b
3:0
RO
2h
Function: 0, 2,4
Offset: 42h
Description
Reserved
Interrupt Message Number N/A
Slot Implemented N/A
Device/Port Type
This field identifies the type of device. It is set to for the DMA to indicate root complex
integrated endpoint device.
Capability Version
This field identifies the version of the PCI Express capability structure. Set to 2h for
PCI Express and DMA devices for compliance with the extended base registers.
3.5.3
3.5.3.1
HDRTYPECTRL
Bus: 0
Device: 5
Bit
Attr
Default
31:3
RV
0h
Function: 0
Offset: 80h
Description
Reserved
269
HDRTYPECTRL
Bus: 0
3.5.3.2
Offset: 80h
Attr
Default
Description
2:0
RW
000b
Device: 5
Function: 0
Offset: 84h
Bit
Attr
Default
Description
63:58
RW-LB
00h
57:32
RV
0h
Reserved
31:26
RW-LB
3Fh
25:0
RV
0h
Reserved
TSEG
Bus: 0
270
Function: 0
Bit
MMCFG
Bus: 0
3.5.3.3
Device: 5
Device: 5
Bit
Attr
Default
63:52
RW-LB
000h
51:32
RV
0h
31:20
RW-LB
FE0h
19:0
RV
0h
Function: 0
Offset: A8h
Description
3.5.3.4
GENPROTRANGE1_BASE
Bus: 0
Device: 5
Bit
3.5.3.5
Attr
63:51
RV
50:16
RW-LB
15:0
RV
Default
0h
Offset: B0h
Description
Reserved
Reserved
GENPROTRANGE1_LIMIT
Bus: 0
Device: 5
Bit
3.5.3.6
Function: 0
Attr
Function: 0
Default
63:51
RV
0h
50:16
RW-LB
000000
000h
15:0
RV
0h
Offset: B8h
Description
Reserved
Limit address
[50:16] of generic memory address range that needs to be protected from
inbound dma accesses. The protected memory range can be anywhere in the
memory space addressable by the processor. Addresses that fall in this range, that
is, GenProtRange.Base[63:16] <= Address [63:16] <= GenProtRange.Limit
[63:16], are completer aborted by IIO.
Setting the Protected range base address greater than the limit address disables
the protected memory region.
Note that this range is orthogonal to Intel VT-d spec defined protected address
range. This register is programmed once at boot time and does not change after
that, including any quiesce flows. Since this register provides for a generic range,
it can be used to protect any system dram region from DMA accesses. The
expected usage for this range is to abort all PCIe accesses to the PCI-Segments
region.
Reserved
GENPROTRANGE2_BASE
Bus: 0
Device: 5
Bit
Attr
Default
63:51
RV
0h
Function: 0
Offset: C0h
Description
Reserved
271
GENPROTRANGE2_BASE
Bus: 0
Device: 5
3.5.3.7
Bit
Attr
50:16
RW-LB
15:0
RV
Default
Reserved
Bit
Attr
Function: 0
Default
63:51
RV
0h
50:16
RW-LB
000000
000h
15:0
RV
0h
Offset: C8h
Description
Reserved
Limit address
[50:16] of generic memory address range that needs to be protected from
inbound dma accesses. The protected memory range can be anywhere in the
memory space addressable by the processor. Addresses that fall in this range that
is, GenProtRange.Base[63:16] <= Address [63:16] <= GenProtRange.
Limit [63:16], are completer aborted by IIO.Setting the Protected range base
address greater than the limit address disables the protected memory region.
Note that this range is orthogonal to Intel VT-d spec defined protected address
range. This register is programmed once at boot time and does not change after
that, including any quiesce flows.
This region is expected to be used to protect against PAM region accesses
inbound, but could also be used for other purposes, if needed.
Reserved
TOLM
Bus: 0
272
Offset: C0h
Description
GENPROTRANGE2_LIMIT
Bus: 0
Device: 5
3.5.3.8
Function: 0
Device: 5
Function: 0
Offset: D0h
Bit
Attr
Default
Description
31:26
RW-LB
00h
TOLM address
Indicates the top of low dram memory which is aligned to a 64MB boundary. A 32
bit transaction that satisfies 0 <= Address[31:26] <= TOLM[31:26] is a
transaction towards main memory.
25:0
RV
0h
Reserved
3.5.3.9
TOHM
Bus: 0
3.5.3.10
Device: 5
Bit
Attr
Default
63:26
RW-LB
000000
0000h
25:0
RV
0h
Function: 0
Offset: D4h
Description
TOHM address
Indicates the limit of an aligned 64 MB granular region that decodes >4 GB
addresses towards system dram memory. A 64-bit transaction that satisfies 4G
<= A[63:26] <= TOHM[63:26] is a transaction towards main memory.
This register is programmed once at boot time and does not change after that,
including during quiesce flows.
Reserved
NCMEM_BASE
Bus: 0
Bit
Attr
63:26
RW-LB
25:0
RV
Device: 5
Default
Function: 0
Offset: E0h
Description
Reserved
273
3.5.3.11
3.5.3.12
Device: 5
Attr
Default
Description
63:26
RW-LB
000000
0000h
25:0
RV
0h
Reserved
MENCMEM_BASE: Intel Management Engine (Intel ME) Noncoherent Memory Base Address
Bit
Attr
63:19
RW-LB
18:0
RV
Offset: F0h
Description
Reserved
Function: 0
Offset: F8h
Bit
Attr
Default
Description
63:19
RW-LB
000000
000000
h
18:0
RV
0h
Reserved
CPUBUSNO
Bus: 0
274
Function: 0
Default
MENCMEM_LIMIT
Bus: 0
Device: 5
3.5.3.14
Offset: E8h
Bit
MENCMEM_BASE
Bus: 0
Device: 5
3.5.3.13
Function: 0
Device: 5
Bit
Attr
Default
31:17
RV
0h
Function: 0
Offset: 108h
Description
Reserved
CPUBUSNO
Bus: 0
3.5.3.15
Device: 5
Function: 0
Offset: 108h
Bit
Attr
Default
Description
16
RW-LB
0h
15:8
RW-LB
00h
7:0
RW-LB
00h
Valid
1: IIO claims PCI config accesses from ring if:
the bus# matches the value in bits 7:0 of this register and Dev# >= 16
OR
the bus# does not match either the value in bits 7:0 or 15:8 of this register
0: IIO does not claim PCI config accesses from ring
LMMIOL
Bus: 0
Device: 5
Bit
Attr
Default
31:24
RW-LB
00h
Function: 0
Offset: 10Ch
Description
23:16
RV
0h
15:8
RW-LB
00h
Reserved
Local MMIO Low Base Address
Corresponds to A[31:24] of MMIOL base address. An inbound memory address
that satisfies local MMIOL base[15:8] <= A[31:24] <= local MMIOL limit[15:8] is
treated as a local peer2peer transaction that do not cross coherent interface.
Notes:
Setting LMMIOL.BASE greater than LMMIOL.LIMIT disables local MMIOL
peer2peer.
This register is programmed once at boot time and does not change after that,
including any quiesce flows.
7:0
3.5.3.16
RV
0h
Reserved
LMMIOH_BASE
Bus: N
Device: 5
Bit
Attr
Default
63:51
RV
0h
Function: 0
Offset: 110h
Description
Reserved
275
LMMIOH_BASE
Bus: N
3.5.3.17
Offset: 110h
Attr
Default
Description
50:26
RW-LB
000000
0h
25:0
RV
0h
Reserved
Bit
Attr
Default
63:51
RV
0h
50:26
RW-LB
000000
0h
25:0
RV
0h
Function: 0
Offset: 118h
Description
Reserved
Local MMIOH Limit Address
Corresponds to A[50:26] of MMIOH limit. An inbound memory address that
satisfies local MMIOH base [50:26] <= A[63:26] <= local MMIOH limit [50:26] is
treated as local a peer2peer transactions that does not cross the coherent
interface.
Notes:
Setting LMMIOH.BASE greater than LMMIOH.LIMIT disables local MMIOH
peer2peer.
This register is programmed once at boot time and does not change after that,
including any quiesce flows.
Reserved
GENPROTRANGE0_BASE
Bus: 0
Device: 5
276
Function: 0
Bit
LMMIOH_LIMIT
Bus: N
3.5.3.18
Device: 5
Bit
Attr
Default
63:51
RV
0h
50:16
RW-LB
15:0
RV
Function: 0
Offset: 120h
Description
Reserved
Reserved
3.5.3.19
GENPROTRANGE0_LIMIT
Bus: 0
Device: 5
Bit
3.5.3.20
Attr
Function: 0
Default
63:51
RV
0h
50:16
RW-LB
000000
000h
15:0
RV
0h
Offset: 128h
Description
Reserved
Limit Address
[50:16] of generic memory address range that needs to be protected from
inbound dma accesses. The protected memory range can be anywhere in the
memory space addressable by the processor. Addresses that fall in this range that
is, GenProtRange.Base[63:16] <= Address [63:16] <= GenProtRange.Limit
[63:16], are completer aborted by IIO.
Setting the Protected range base address greater than the limit address disables
the protected memory region.
Note that this range is orthogonal to Intel VT-d spec defined protected address
range. This register is programmed once at boot time and does not change after
that, including any quiesce flows. Since this register provides for a generic range,
it can be used to protect any system dram region from DMA accesses. The
expected usage for this range is to abort all PCIe accesses to the PCI-Segments
region.
Reserved
Device: 5
Function: 0
Offset: 140h
Bit
Attr
Default
Description
31
RW
0b
30:29
RV
0h
Reserved
28
RW
0b
27:16
RV
0h
Reserved
15
RW
1b
14:12
RW
0h
Socket ID
This is the BIOS programmed field that indicates the SocketID of this particular
socket. SocketID is the unique value that each socket in the system gets for
DCA/DIO target determination. Normally this value is the same as the
APICID[7:5] of the cores in the socket, but it can be other values as well, if
system topology were to not allow that straight mapping.
IIO uses strapped NodeID to compare against the target NodeID determined by
using the target SocketID value as a lookup into the CIPDCASAD register. If there
is a match, then a PCIDCAHint is not sent (since the data is already located in the
same LLC).
This register is not used for this comparison. It is not used by hardware at all.
277
CIPCTRL
Bus: 0
3.5.3.21
Device: 5
Offset: 140h
Bit
Attr
Default
Description
11:9
RW
0h
8:6
RW
001b
5:3
RW
000b
RW
0b
RW
0b
RW
0b
CIPSTS
Bus: 0
278
Function: 0
Device: 5
Bit
Attr
Default
31:3
RV
0h
Function: 0
Offset: 144h
Description
Reserved
CIPSTS
Bus: 0
3.5.3.22
Device: 5
Function: 0
Offset: 144h
Bit
Attr
Default
Description
RO
1b
RO
1b
RRB Empty
This indicates that there are no pending requests in the RRB.
0 - Pending RRB requests
1 - RRB Empty
This is a live bit and hence can toggle clock by clock. This is provided mostly as a
debug visibility feature.
RO
0b
CIPDCASAD
Bus: 0
Device: 5
Function: 0
Offset: 148h
Bit
Attr
Default
Description
31:29
RW
000b
28:26
RW
000b
25:23
RW
000b
22:20
RW
000b
19:17
RW
000b
16:14
RW
000b
13:11
RW
000b
10:8
RW
000b
7:1
RV
0h
Reserved
279
CIPDCASAD
Bus: 0
3.5.3.23
Bit
Attr
Default
RW
0b
Function: 0
Offset: 148h
Description
Enable TPH/DCA
When disabled, PrefetchHint will not be sent on the coherent interface.
0: Disable TPH/DCA Prefetch Hints
1: Enable TPH/DCA Prefetch Hints
Notes:
This register is locked based on DISDCA setting
This table is programmed by BIOS and this bit is set when the table is valid
CIPINTRC
Bus: 0
280
Device: 5
Device: 5
Function: 0
Bit
Attr
Default
63:45
RV
0h
Reserved
44
RW
1b
A20M Detect
43
RW
1b
INTR Detect
42
RW
0b
SMI Detect
41
RW
0b
INIT Detect
Offset: 14Ch
Description
40
RW
0b
NMI Detect
39:38
RV
0h
Reserved
37
RW
0b
FERR Invert
36
RW
1b
A20M Invert
35
RW
0b
INTR Invert
34
RW
0b
SMI Invert
33
RW
0b
Init Invert
32
RW
0b
NMI Invert
31:26
RV
0h
Reserved
25
RW
0b
24
RW
0b
23:21
RV
0h
Reserved
20
RW
0b
A20M Mask
19
RV
0h
Reserved
18
RW
0b
17
RW
0b
16
RW
0b
15:14
RV
0h
Reserved
13
RW-L
1b
FERR Mask
Notes:
Locked by RSPLCK
12
RW
1b
A20M Mask
11
RW
1b
INTR Mask
10
RW
1b
SMI Mask
RW
1b
Init Mask
CIPINTRC
Bus: 0
3.5.3.24
Device: 5
Function: 0
Bit
Attr
Default
RW
1b
NMI Mask
RW-L
0b
IA32 or IPF
Notes:
Locked by RSPLCK
6:2
RV
0h
Reserved
RW
0b
RW-L
0b
Offset: 14Ch
Description
3.5.3.25
Device: 5
Function: 0
Offset: 154h
Bit
Attr
Default
Description
31
RW1CS
0b
30
RW1CS
0b
29:8
RV
0h
Reserved
RO-V
0b
RO-V
0b
RO-V
0b
RO-V
0b
RO-V
0b
RO-V
0b
RO-V
0b
RO-V
0b
VTBAR
Bus: 0
Device: 5
Bit
Attr
Default
31:13
RW-LB
00000h
12:1
RV
0h
Function: 0
Offset: 180h
Description
281
VTBAR
Bus: 0
3.5.3.26
Device: 5
Attr
Default
Description
RW-LB
0b
Device: 5
Function: 0
Offset: 184h
Bit
Attr
Default
15
RW-O
0b
14:8
RV
0h
Reserved
7:4
RW-LB
0011b
Isoch/Non-Isoch HPA_LIMIT
Represents the host processor addressing limit
0000: 2^36 (that is, bits 35:0)
0001: 2^37 (that is, bits 36:0)
...
1010: 2^46 (that is, bits 45:0)
When Intel VT-d translation is enabled on an Intel VT-d engine (isoch or nonisoch), all host addresses (during page walks) that go beyond the limit specified in
this register will be aborted by IIO. Note that pass-through and translated ATS
accesses carry the host-address directly in the access and are subject to this
check as well.
3:0
RW-LB
8h
Isoch/Non-Isoch GPA_LIMIT
Represents the guest virtual addressing limit for the non-Isoch Intel VT-d engine.
0000: 2^40 (that is, bits 39:0)
0001: 2^41 (that is, bits 40:0)
..
0111: 2^47
1000: 2^48
Others: Reserved
When Intel VT-d translation is enabled, all incoming guest addresses from PCI
Express, associated with the non-isoch Intel VT-d engine, that go beyond the limit
specified in this register will be aborted by IIO and a UR response returned. This
register is not used when translation is not enabled. Note that translated and
pass-through addresses are in the host-addressing domain and NOT guestaddressing domain and hence GPA_LIMIT checking on those accesses are
bypassed and instead HPA_LIMIT checking applies.
Description
VTISOCHCTRL
Bus: 0
282
Offset: 180h
Bit
VTGENCTRL
Bus: 0
3.5.3.27
Function: 0
Device: 5
Bit
Attr
Default
31:9
RV
0h
Function: 0
Offset: 188h
Description
Reserved
VTISOCHCTRL
Bus: 0
3.5.3.28
Device: 5
Function: 0
Offset: 188h
Bit
Attr
Default
Description
RW-LB
0b
7:5
RW-LB
0h
4:2
RW-LB
0h
Number of Isoch L1 entries for Azalia when Isoch Intel VT-d engine is
enabled
000: 16 entries (when ISOCH is enabled only)
001: 1 entry
010: 2 entries
011: 4 entries
100: 8 entries
101: 16 entries
Others: Reserved
RV
0h
Reserved
RW-LB
1b
VTGENCTRL2
Bus: 0
Device: 5
Function: 0
Offset: 18Ch
Bit
Attr
Default
Description
31:12
RV
0h
Reserved
11
RW-L
0b
283
VTGENCTRL2
Bus: 0
3.5.3.29
Device: 5
Offset: 18Ch
Bit
Attr
Default
Description
10:7
RW-LB
7h
LRU Timer
Controls the rate at which the LRU buckets should degrade.
If we are in Request mode (LRUCTRL = 0), then we will degrade LRU after 16 *
N requests where N is the value of this field.
If we are in Cycles mode (CRUCTRL = 1), then we will degrade LRU after 256 *
N cycles where N is the value of this field.
The default value of 0x7 (along with LRUCTRL=0) will give us a default behavior of
decreasing the LRU buckets every 112 requests.
6:5
RW-LB
01b
Prefetch Control
Queued invalidation, interrupt table read, context table reads and root table reads
NEVER have prefetch/snarf/reuse capability. This is a general rule. Beyond that
the Prefetch Control bits control additional behavior as shown below. This field
controls which VT-d reads are to be considered for prefetch/snarf/reuse in the QPI
buffers.
00: Prefetch/snarf/reuse is turned off that is, IRP cluster never reuses the VT-d
read data
01: Prefetch/snarf/reuse is enabled for all leaf/non-leaf VT-d page walk reads.
10: RESERVED
11: Prefetch/snarf/reuse is enabled on ALL leaf (not non-leaf) VT-d page walks
reads regardless of the setting of the CC.ALH bit
RV
0h
Reserved
RW-LB
0b
Dont use U bit in leaf entry for leaf eviction policy on untranslated DMA
requests (AT=00b)
RW-LB
0b
RW-LB
0b
Dont mark leaf entries with U=0 on translation requests with AT=01 for
early eviction
RV
0h
Reserved
IOTLBPARTITION
Bus: 0
Device: 5
Bit
284
Function: 0
Attr
Function: 0
Default
Offset: 194h
Description
31:29
RV
0h
28:27
RW
00b
Reserved
Range Selection for DMI[20:22]
26:25
RW
00b
24:23
RW
00b
22:15
RV
0h
14:13
RW
00b
Reserved
Range Selection for Intel ME
12:11
RW
00b
10:9
RW
00b
8:1
RV
0h
Reserved
RW-LB
0b
3.5.3.30
VTUNCERRSTS
Bus: 0
3.5.3.31
Device: 5
Function: 0
Offset: 1A8h
Bit
Attr
Default
Description
31
RW1CS
0b
30:9
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
Device: 5
Function: 0
Offset: 1ACh
Bit
Attr
Default
Description
31
RWS
0b
30:9
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
285
3.5.3.32
VTUNCERRSEV
Bus: 0
3.5.3.33
Function: 0
Offset: 1B0h
Bit
Attr
Default
Description
31
RWS
0b
30:9
RV
0h
Reserved
RWS
1b
RWS
1b
RWS
0b
RWS
1b
RWS
1b
RWS
1b
RWS
1b
RWS
1b
RWS
1b
VTUNCERRPTR
Bus: 0
286
Device: 5
Device: 5
Bit
Attr
Default
7:5
RV
0h
4:0
ROS-V
00h
Function: 0
Offset: 1B4h
Description
Reserved
Intel VT Uncorrectable First Error Pointer
This field points to which of the unmasked uncorrectable errors happened first.
This field is only valid when the corresponding error is unmasked and the status
bit is set and this field is rearmed to load again when the status bit indicated to by
this pointer is cleared by software from 1 to 0.
Value of 0x0 corresponds to bit 0 in VTUNCERRSTS register, value of 0x1
corresponds to bit 1, and so forth.
3.5.3.34
Device: 5
Function: 0
Offset: 1C0h
Bit
Attr
Default
Description
63:42
RV
0h
Reserved
41
RW
0b
40
RV
0h
Reserved
39
RW
0b
38
RWS-O
0b
37
RW
0b
36:35
RV
0h
Reserved
287
IIOMISCCTRL
Bus: 0
288
Device: 5
Function: 0
Offset: 1C0h
Bit
Attr
Default
Description
34:32
RWS
000b
31
RV
0h
Reserved
30
RW
1b
29
RW
0b
28
RW
0b
27
RW
0b
26
RW
0b
25
RWS
1b
IIOMISCCTRL
Bus: 0
Device: 5
Function: 0
Offset: 1C0h
Bit
Attr
Default
Description
24
RW
0b
23
RV
0h
Reserved
22
RW
0b
21
RW
0b
20
RW
0b
19
RW
0b
RVGAEN
Remote VGA Enable Enables VGA accesses to be sent to remote node.
If set, accesses to the VGA region (A_0000 to B_FFFF) will be forwarded to the
CBo where it will determine the node ID where the VGA region resides. It will then
be forwarded to the given remote node.
If clear, then VGA accesses will be forwarded to the local PCIe port that has its
VGAEN set. If none have their VGAEN set, then the request will be forwarded to
the local DMI port, if operating in DMI mode. If it is not operating in DMI mode,
then the request will be aborted.
18
RW
1b
17:16
RW
01b
15
RW
0b
14
RW
0b
289
IIOMISCCTRL
Bus: 0
290
Device: 5
Function: 0
Offset: 1C0h
Bit
Attr
Default
Description
13
RW
0b
12
RW
0b
11
RV
0h
Reserved
10
RW
0b
Legacy Port
Sockets where the NodeID=0 are generally identified as having the legacy DMI
port. But there is still a possibility that another socket also has a NodeID=0. The
system is configured by software to route legacy transactions to the correct
socket. However, inbound legacy messages received on a PCIe port of a socket
with NodeID=0 that is not the true legacy port need to be routed to a remote
socket that is the true legacy port.
For a local NodeID is zero, this bit is used to determine if inbound messages
should be routed to a DMI port on a remote socket with NodeID=0, or if the
messages should be sent to the local DMI port, since the local NodeID is also 0. If
the local NodeID is not zero, then this bit is ignored.
0: indicates this socket has the true DMI legacy port, send legacy transactions to
local DMI port
1: indicates this is a non-legacy socket, send legacy transactions to the Coherent
Interface
Notes:
This bit does not affect routing for non-message transactions. It only affects
inbound messages that need to be routed to the true legacy port.
This bit is NOT used for any outbound address decode/routing purposes.
Outbound traffic that is subtractively decoded will always be forwarded to local
DMI port, if one exists, or it will be aborted.
The default value of this field is based on the NodeID and FWAGENT_DMIMODE
straps.
Software can only change this bit after reset during early boot phase, but must
guarantee there is no traffic flowing through the system, except for the write that
changes this bit.
RW
1b
RW
0b
7:3
RW
1110b
RW
TOCM
Indicates the top of Core physical addressability limit.
00000-00100: Reserved
00101: 2^37
00110: 2^38
...
1110: 2^46
01111 -11111: Reserved
iio uses this to abort all inbound transactions that cross this limit.
EN1K
This bit when set, enables 1K granularity for I/O space decode in each of the
virtual P2P bridges corresponding to root ports, and DMI ports.
IIOMISCCTRL
Bus: 0
3.5.3.35
Device: 5
Function: 0
Offset: 1C0h
Bit
Attr
Default
Description
RWS-O
UNIPHY Disable
Place entire UNIPHY in L2 (for when no ports are used, as in some multi-socket
configurations).
RW-LB
Reserved
This bit must never be set.
Device: 5
Bit
Attr
Default
31:20
RO-V
000h
Function: 0
Offset: 290h
Description
19:12
RV
0h
11:4
RW-L
00h
Reserved
RV
0h
Reserved
RW-L
0b
Command Bit
Writing a 1 to this bit will enable protection.
Writing a 0 to this bit will disable protection.
RO
0h
RW-O
0h
Lock
Bits 19:0 are locked down in this register when this bit is set. Can this be set while
other bits are being written to in the same write transaction?
291
3.5.3.36
IRP_MISC_DFX0
Bus: 0
Device: 5
292
Function: 0
Offset: 800h
Bit
Attr
Default
Description
31
RW-L
0b
30
RW-L
0b
29
RW-L
0b
28
RW-L
1b
27
RW-L
1b
26
RW-L
0b
25
RW-L
0b
24
RW-L
1b
23:22
RW-L
00b
21:15
RW-L
03h
14
RW-L
0b
IRP_MISC_DFX0
Bus: 0
Device: 5
3.5.3.37
Function: 0
Offset: 800h
Bit
Attr
Default
Description
13:9
RW-L
09h
RW-L
1b
RW-L
1b
RW-L
1b
RW-L
1b
4:1
RW-L
4h
RV
0h
Reserved
IRP_MISC_DFX1
Bus: 0
Device: 5
Bit
Attr
Function: 0
Default
Offset: 804h
Description
31:14
RV
0h
Reserved
13
RW-L
0b
12
RV
0h
11:10
RW-L
00b
9:8
RW-L
00b
7:2
RW-L
0h
RW-L
1b
RW-L
0b
293
3.5.3.38
IRP0DELS
Bus: 0
Bit
3.5.3.39
Function: 0
Offset: 808h
Attr
Default
63:36
RV
0h
Reserved
35:32
RW-L
0h
31:28
RW-L
0h
27:24
RW-L
0h
23:20
RW-L
0h
19:16
RW-L
0h
15:12
RW-L
0h
11:8
RW-L
0h
7:4
RW-L
0h
3:0
RW-L
0h
Description
IRP1DELS
Bus: 0
294
Device: 5
Device: 5
Function: 0
Offset: 810h
Bit
Attr
Default
Description
63:36
RV
0h
Reserved
35:32
RW-L
0h
31:28
RW-L
0h
27:24
RW-L
0h
23:20
RW-L
0h
19:16
RW-L
0h
15:12
RW-L
0h
11:8
RW-L
0h
7:4
RW-L
0h
3:0
RW-L
0h
3.5.3.40
IRP0DBGRING[0:1]
Bus: 0
Device: 5
3.5.3.41
Bit
Attr
Default
63:0
RO
000000
000000
0000h
Bit
Attr
Default
63:0
RO
000000
000000
0000h
Offset: 820h
Description
Device: 5
Bit
Attr
Default
7:0
RO
00h
Function: 0
Offset: 828h
Description
IRP1DBGRING1
Bus: 0
3.5.3.44
Function: 0
IRP0DBGRING1
Bus: 0
3.5.3.43
Offset: 818h
Description
IRP1DBGRING[0:1]
Bus: 0
Device: 5
3.5.3.42
Function: 0
Device: 5
Bit
Attr
Default
7:0
RO
00h
Function: 0
Offset: 829h
Description
IRP0RNG
Bus: 0
Device: 5
Bit
Attr
Default
31
RWS-L
0b
30:27
RWS-L
0000b
Function: 0
Offset: 830h
Description
Select Trigger
Selects the cluster trigger output signals (ClusterTrigOut[1:0]) from this cluster
and places them onto the two LSBs of the lane selected by primary lane
(bits[30:27]).
Note: Locked by DBGBUSLCK
Primary Lane Selection for placement of a trigger
Selects the lane this cluster will use to place the designated trigger enabled by bit
[31]. When cluster trigger out is enabled by bit [31] then the lane selected with
bits [30:27] will display the CTO triggers on its two LSB bits. Only if this cluster
support CTO outputs.
Note: Locked by DBGBUSLCK
295
IRP0RNG
Bus: 0
296
Device: 5
Function: 0
Offset: 830h
Bit
Attr
Default
Description
26:24
RWS-L
000b
23:21
RWS-L
000b
20:18
RWS-L
000b
17:15
RWS-L
000b
14:12
RWS-L
000b
11:9
RWS-L
000b
IRP0RNG
Bus: 0
3.5.3.45
Device: 5
Function: 0
Offset: 830h
Bit
Attr
Default
Description
8:6
RWS-L
011b
5:3
RWS-L
000b
2:0
RWS-L
000b
IRP1RNG
Bus: 0
Device: 5
Bit
Attr
Default
31
RWS-L
0b
30:27
RWS-L
0000b
26:24
RWS-L
000b
Function: 0
Offset: 834h
Description
Select Trigger
Selects the cluster trigger output signals (ClusterTrigOut[1:0]) from this cluster
and places them onto the two LSBs of the lane selected by primary lane
(bits[30:27]).
Note: Locked by DBGBUSLCK
Primary Lane Selection for placement of a trigger
Selects the lane this cluster will use to place the designated trigger enabled by bit
[31]. When cluster trigger out is enabled by bit [31] then the lane selected with
bits [30:27] will display the CTO triggers on its two LSB bits. Only if this cluster
support CTO outputs.
Note: Locked by DBGBUSLCK
Debug ring source lane 8 select
Select the source of data to be driven to the next cluster on lane 8.
000: Select ring contents from previous cluster onto debug ring
001: Select cluster outgoing data onto debug ring
010: Select cluster incoming data onto debug ring
011: Select debug bus lane 8 onto debug ring
111: Select debug bus lane 3 onto debug ring
Others: reserved
Note: Locked by DBGBUSLCK
297
IRP1RNG
Bus: 0
298
Device: 5
Function: 0
Offset: 834h
Bit
Attr
Default
Description
23:21
RWS-L
000b
20:18
RWS-L
000b
17:15
RWS-L
000b
14:12
RWS-L
000b
11:9
RWS-L
000b
8:6
RWS-L
011b
IRP1RNG
Bus: 0
3.5.3.46
Device: 5
Function: 0
Offset: 834h
Bit
Attr
Default
Description
5:3
RWS-L
000b
2:0
RWS-L
000b
Device: 5
Function: 0
Offset: 840h
Bit
Attr
Default
Description
63:34
RV
0h
Reserved
33:30
RW-L
8h
FIFO Credits
The IRP has a FIFO on the inbound path feeding the R2PCIe. This is only a staging
FIFO to assist in the flow of inbound traffic. This field specifies the number of FIFO
entries to use in this IRP staging FIFO.
29:28
RW-L
1h
27:24
RW-L
8h
23:22
RW-L
1h
21:20
RW-L
1h
19:18
RW-L
1h
17:14
RW-L
9h
299
IRPEGCREDITS
Bus: 0
Device: 5
Function: 0
Offset: 840h
Bit
Attr
Default
Description
13:10
RW-L
Bh
9:6
RW-L
7h
5:3
RW-L
7h
2:0
RW-L
4h
3.5.4
3.5.4.1
IRPPERRSV
Bus: 0
300
Device: 5
Function: 2
Offset: 80h
Bit
Attr
Default
Description
63:30
RV
0h
29:28
RWS
10b
27:26
RWS
10b
25:22
RV
0h
Reserved
Reserved
IRPPERRSV
Bus: 0
3.5.4.2
Device: 5
Bit
Attr
Default
21:20
RWS
10b
Function: 2
Offset: 80h
Description
19:10
RV
0h
9:8
RWS
01b
Reserved
CSR access crossing 32-bit boundary (C3)
00: Error Severity Level 0 (Correctable)
01: Error Severity Level 1 (Recoverable)
10: Error Severity Level 2 (Fatal)
11: Reserved
7:6
RWS
01b
5:4
RWS
01b
3:2
RWS
00b
1:0
RV
0h
Reserved
Attr
Device: 5
Default
Function: 2
Offset: 8Ch
Description
31:14
RV
0h
13:12
RWS
01b
Reserved
Overflow/Underflow Error Severity
00: Error Severity Level 0 (Correctable)
01: Error Severity Level 1 (Recoverable)
10: Error Severity Level 2 (Fatal)
11: Reserved
11:10
RWS
01b
301
IIOERRSV
Bus: 0
3.5.4.3
Bit
Attr
Default
9:8
RWS
01b
7:0
RV
0h
Function: 2
Offset: 8Ch
Description
MIERRSV
Bus: 0
Bit
3.5.4.4
Device: 5
Device: 5
Attr
Function: 2
Offset: 90h
Default
Description
31:10
RV
0h
9:8
RWS
00b
Reserved
DFx Injection Error
7:6
RWS
00b
5:4
RWS
00b
3:2
RWS
00b
1:0
RWS
00b
3.5.4.5
Attr
Device: 5
Function: 2
Default
Offset: 94h
Description
31:6
RV
0h
5:4
RWS
10b
Reserved
PCIe Fatal Error
10: Map this PCIe
01: Map this PCIe
00: Map this PCIe
3:2
RWS
01b
1:0
RWS
00b
Severity Map
error type to Error Severity 2
error type to Error Severity 1
error type to Error Severity 0
302
3.5.4.6
SYSMAP
Bus: 0
Bit
Device: 5
Attr
Function: 2
Default
31:11
RV
0h
10:8
RWS
101b
RV
0h
6:4
RWS
010b
RV
0h
2:0
RWS
010b
Offset: 9Ch
Description
Reserved
Severity 2 Error Map
101: Generate CPEI
010: Generate NMI
001: Generate SMI/PMI
000: No inband message
Others: Reserved
Reserved
Severity 1 Error Map
101: Generate CPEI
010: Generate NMI
001: Generate SMI/PMI
000: No inband message
Others: Reserved
Reserved
Severity 0 Error Map
101: Generate CPEI
010: Generate NMI
001: Generate SMI/PMI
000: No inband message
Others: Reserved
This register provides the option to configure an error pin to either as a special purpose
error pin which is asserted based on the detected error severity, or as a general
purpose output which is asserted based on the value in the ERRPINDAT. The assertion
of the error pins can also be completely disabled by this register.
ERRPINCTL
Bus: 0
Device: 5
Function: 2
Offset: A4h
Bit
Attr
Default
Description
31:6
RV
0h
5:4
RW
00b
3:2
RW
00b
1:0
RW
00b
Reserved
303
3.5.4.7
3.5.4.8
Device: 5
Function: 2
Offset: A8h
Bit
Attr
Default
Description
31:3
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
304
Device: 5
Function: 2
Offset: ACh
Attr
Default
Description
31:3
RV
0h
Reserved
RW-LB
0b
RW-LB
0b
ERRPINDAT
Bus: 0
3.5.4.9
Device: 5
Function: 2
Offset: ACh
Bit
Attr
Default
Description
RW-LB
0b
Device: 5
Function: 2
Offset: B0h
Bit
Attr
Default
Description
63:56
RV
0h
Reserved
55
RWS
0b
54:44
RWS
000h
43:0
RWS
000000
00000h
VPP Enable
When set, the VPP function for the corresponding root port is enabled.
Enable Root Port
[54]
Port 3d
[53]
Port 3c
[52]
Port 3b
[51]
Port 3a
[50]
Port 2d
[49]
Port 2c
[48]
Port 2b
[47]
Port 2a
[46]
Port 1b
[45]
Port 1a
[44]
Port 0 (PCIe mode only)
VPP Address
Assigns the VPP address of the device on the VPP interface and assigns the port
address for the ports within the VPP device. There are more address bits then root
ports so assignment must be spread across VPP ports.
Port Addr Root Port
[43:41] [40] Port 3d
[39:37] [36] Port 3c
[35:33] [32] Port 3b
[31:29] [28] Port 3a
[27:25] [24] Port 2d
[23:21] [20] Port 2c
[19:17] [16] Port 2b
[15:13] [12] Port 2a
[11:9] [8] Port 1b
[7:5] [6] Port 1a
[3:1] [0] Port 0 (PCIe mode only)
305
3.5.4.10
3.5.4.11
Device: 5
Attr
RV
0h
RW1CS
00b
Description
Reserved
VPP Error
VPP Port error happened, that is, an unexpected STOP of NACK was seen on the
VPP port
Device: 5
Function: 2
Offset: BCh
Bit
Attr
Default
31:24
RWS
1Eh
23:16
RWS
96h
11:0
RWS
9C4h
Description
VPP_INVERTS
Bus: 0
Bit
3.5.4.13
Offset: B8h
Default
31:1
VPPFREQ
Bus: 0
3.5.4.12
Function: 2
Device: 5
Attr
Default
Function: 2
Offset: C8h
Description
RV
0h
Reserved
2:2
RWS
0h
Invert MRL
Inverts the MRL signal
1:1
RWS
0h
Invert EMIL
Inverts the EMIL signal
RWS
00b
Invert PWREN
Inverts the PWREN signal
306
GNERRST
Bus: 0
3.5.4.14
Device: 5
Function: 2
Offset: 1C0h
Bit
Attr
Default
Description
31:26
RV
0h
Reserved
25
RW1CS
0b
24
RW1CS
0b
23
RW1CS
0b
22
RW1CS
0b
21
RV
0h
Reserved
20
RW1CS
0b
19:16
RV
0h
Reserved
15:5
RW1CS
000h
4:2
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
Device: 5
Function: 2
Offset: 1C4h
Bit
Attr
Default
Description
31:26
RV
0h
Reserved
25
RW1CS
0b
24
RV
0h
Reserved
23
RW1CS
0b
22
RW1CS
0b
307
GFERRST
Bus: 0
3.5.4.15
Device: 5
Function: 2
Offset: 1C4h
Bit
Attr
Default
Description
21
RV
0h
Reserved
20
RW1CS
0b
19:16
RV
0h
15:5
RW1CS
000h
4:2
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
308
Device: 5
Function: 2
Offset: 1C8h
Attr
Default
Description
31:26
RV
0h
Reserved
25
RW
0b
24
RW
0b
23
RW
0b
22
RW
0b
Reserved
21
RV
0h
Reserved
20
RW
0b
19:16
RV
0h
Reserved
GERRCTL
Bus: 0
3.5.4.16
Device: 5
Bit
Attr
Default
15:5
RW
000h
Function: 2
Offset: 1C8h
Description
4:2
RV
0h
Reserved
RW
0b
RW
0b
3.5.4.17
Device: 5
Attr
Function: 2
Default
Offset: 1CCh
Description
31:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
309
GSYSCTL
Bus: 0
3.5.4.18
Device: 5
Attr
Default
31:5
RV
0h
Reserved
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
Device: 5
Bit
Attr
Default
31:27
RV
0h
26:0
ROS-V
000000
0h
Function: 2
Offset: 1DCh
Description
Reserved
Global Error Status Log
This field logs the global error status register content when the first fatal error is
reported. This has the same format as the global error status register (GFERRST).
Device: 5
Bit
Attr
Default
31:27
RV
0h
26:0
ROS-V
000000
0h
Function: 2
Offset: 1E8h
Description
Reserved
Global Error Status Log
This filed logs the global error status register content when the next fatal error is
reported. This has the same format as the global error status register (GFERRST).
GNFERRST
Bus: 0
Bit
310
Description
GFNERRST
Bus: 0
3.5.4.20
Offset: 1D0h
Bit
GFFERRST
Bus: 0
3.5.4.19
Function: 2
Attr
Device: 5
Default
31:27
RV
0h
26:0
ROS-V
000000
0h
Function: 2
Offset: 1ECh
Description
Reserved
Global Error Status Log
This filed logs the global error status register content when the first non-fatal
error is reported. This has the same format as the global error status register
(GNERRST).
3.5.4.21
GNNERRST
Bus: 0
Bit
Attr
Device: 5
Function: 2
Default
31:27
RV
0h
26:0
ROS-V
000000
0h
Offset: 1F8h
Description
Reserved
Global Error Status Log
This filed logs the global error status register content when the subsequent nonfatal error is reported. This has the same format as the global error status register
(GNERRST).
3.5.5
3.5.5.1
3.5.5.2
Device: 5
Function: 2
Offset: 230h
Bit
Attr
Default
Description
31:15
RV
0h
Reserved
14
RW1CS
0b
13
RW1CS
0b
12:11
RV
0h
Reserved
10
RW1CS
0b
9:5
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RV
0h
Reserved
Device: 5
Bit
Attr
Default
31:15
RV
0h
Function: 2
Offset: 234h
Description
Reserved
311
IRPP0ERRCTL
Bus: 0
3.5.5.3
Device: 5
Function: 2
Offset: 234h
Bit
Attr
Default
Description
14
RWS
0b
13
RWS
0b
12:11
RV
0h
Reserved
10
RWS
0b
9:5
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RV
0h
Reserved
312
Device: 5
Function: 2
Offset: 238h
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
IRPP0FFERRST
Bus: 0
3.5.5.4
Device: 5
Function: 2
Offset: 238h
Bit
Attr
Default
Description
ROS-V
0b
RV
0h
Reserved
3.5.5.5
Device: 5
Offset: 23Ch
Bit
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
RV
0h
Reserved
IRPP0FFERRHD[0:3]
Bus: 0
Device: 5
3.5.5.6
Function: 2
Bit
Attr
Default
31:0
ROS-V
000000
00h
Function: 2
313
IRPP0NFERRST
Bus: 0
3.5.5.7
Device: 5
Function: 2
Offset: 250h
Bit
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
RV
0h
Reserved
314
Device: 5
Function: 2
Offset: 254h
Bit
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
RV
0h
Reserved
3.5.5.8
IRPP0NFERRHD[0:3]
Bus: 0
Device: 5
3.5.5.9
Bit
Attr
Default
31:0
ROS-V
000000
00h
Bit
Attr
Default
31:19
RV
0h
18:0
RW
00000h
Function: 2
Offset: 268h
Description
Reserved
Select Error Events for Counting
See IRPP0ERRST for per bit description of each error. Each bit in this field has the
following behavior:
0: Do not select this error type for error counting
1: Select this error type for error counting
IRPP0ERRCNT
Bus: 0
Bit
3.5.5.11
IRPP0ERRCNTSEL
Bus: 0
Device: 5
3.5.5.10
Function: 2
Attr
Device: 5
Function: 2
Default
Offset: 26Ch
Description
31:8
RV
0h
Reserved
RW1CS
0b
ERROVF
Error Accumulator Overflow
0: No overflow occurred
1: Error overflow. The error count may not be valid.
6:0
RW1CS
00h
Device: 5
Function: 2
Offset: 2B0h
Attr
Default
Description
31:15
RV
0h
Reserved
14
RW1CS
0b
13
RW1CS
0b
315
IRPP1ERRST
Bus: 0
3.5.5.12
Device: 5
Function: 2
Offset: 2B0h
Bit
Attr
Default
Description
12:11
RV
0h
Reserved
10
RW1CS
0b
9:5
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RV
0h
Reserved
316
Device: 5
Function: 2
Offset: 2B4h
Bit
Attr
Default
Description
31:15
RV
0h
Reserved
14
RWS
0b
13
RWS
0b
12:11
RV
0h
Reserved
10
RWS
0b
9:5
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RV
0h
Reserved
3.5.5.13
3.5.5.14
Device: 5
Function: 2
Offset: 2B8h
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
RV
0h
Reserved
Device: 5
Function: 2
Offset: 2BCh
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
317
IRPP1FNERRST
Bus: 0
3.5.5.15
Device: 5
Offset: 2BCh
Bit
Attr
Default
Description
ROS-V
0b
RV
0h
Reserved
IRPP1FFERRHD[0:3]
Bus: 0
Device: 5
3.5.5.16
Function: 2
Bit
Attr
Default
31:0
ROS-V
000000
00h
Function: 2
3.5.5.17
Device: 5
Function: 2
Offset: 2D0h
Bit
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
RV
0h
Reserved
318
IRPP1NNERRST
Bus: 0
3.5.5.18
Device: 5
Offset: 2D4h
Bit
Attr
Default
Description
31:15
RV
0h
Reserved
14
ROS-V
0b
13
ROS-V
0b
12:11
RV
0h
Reserved
10
ROS-V
0b
9:5
RV
0h
Reserved
ROS-V
0b
ROS-V
0b
ROS-V
0b
ROS-V
0b
RV
0h
Reserved
IRPP1NFERRHD[0:3]
Bus: 0
Device: 5
3.5.5.19
Function: 2
Bit
Attr
Default
31:0
ROS-V
000000
00h
Function: 2
IRPP1ERRCNTSEL
Bus: 0
Device: 5
Bit
Attr
Default
31:19
RV
0h
18:0
RW
00000h
Function: 2
Offset: 2E8h
Description
Reserved
Select Error Events for Counting
See IRPP0ERRST for per bit description of each error. Each bit in this field has the
following behavior:
0: Do not select this error type for error counting
1: Select this error type for error counting
319
3.5.5.20
IRPP1ERRCNT
Bus: 0
Bit
3.5.5.21
Device: 5
Function: 2
Offset: 2ECh
Attr
Default
Description
31:8
RV
0h
Reserved
RW1CS
0b
6:0
RW1CS
00h
3.5.5.22
Device: 5
Function: 2
Offset: 300h
Bit
Attr
Default
Description
31:7
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
3:0
RV
0h
Reserved
320
Device: 5
Function: 2
Offset: 304h
Bit
Attr
Default
Description
31:7
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
3:0
RV
0h
Reserved
3.5.5.23
IIOFFERRST
Bus: 0
Bit
3.5.5.24
Attr
Device: 5
Function: 2
Default
31:7
RV
0h
6:0
ROS-V
00h
Offset: 308h
Description
Reserved
IIO Core Error Status Log
The error status log indicates which error is causing the report of the first error
event. The encoding indicates the corresponding bit position of the error in the
error status register.
3.5.5.25
Bit
Attr
Default
31:0
ROS-V
000000
00h
Bit
Attr
Description
Log of Header Dword 0
Logs the first DWORD of the header on an error condition
Device: 5
Function: 2
Default
31:7
RV
0h
6:0
ROS-V
00h
Offset: 31Ch
Description
Reserved
IIO Core Error Status Log
The error status log indicates which error is causing the report of the first error
event. The encoding indicates the corresponding bit position of the error in the
error status register.
IIONFERRST
Bus: 0
3.5.5.27
IIOFNERRST
Bus: 0
3.5.5.26
Function: 2
Device: 5
Bit
Attr
Default
31:7
RV
0h
6:0
ROS-V
00h
Function: 2
Offset: 320h
Description
Reserved
IIO Core Error Status Log
The error status log indicates which error is causing the report of the first error
event. The encoding indicates the corresponding bit position of the error in the
error status register.
321
IIONFERRHD[0:3]
Bus: 0
Device: 5
3.5.5.28
Bit
Attr
Default
31:0
ROS-V
000000
00h
Attr
Default
31:7
RV
0h
6:0
ROS-V
00h
Function: 2
Offset: 334h
Description
Reserved
IIO Core Error Status Log
The error status log indicates which error is causing the report of the next error
event. The encoding indicates the corresponding bit position of the error in the
error status register.
Device: 5
Function: 2
Offset: 33Ch
Bit
Attr
Default
31:7
RV
0h
Reserved
RW
0b
RW
0b
RW
0b
3:0
RV
0h
Reserved
Description
IIOERRCNT
Bus: 0
Bit
322
Description
Device: 5
Bit
IIOERRCNTSEL
Bus: 0
3.5.5.30
IIONNERRST
Bus: 0
3.5.5.29
Function: 2
Device: 5
Function: 2
Offset: 340h
Attr
Default
Description
31:8
RV
0h
Reserved
RW1CS
0b
6:0
RW1CS
00h
Error Accumulator
This counter accumulates errors that occur when the associated error type is
selected in the ERRCNTSEL register.
Notes:
This register is cleared by writing 7Fh.
Maximum counter available is 127d (7Fh).
3.5.5.31
MIERRST
Bus: 0
Bit
3.5.5.32
Device: 5
Attr
Default
Description
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
RW1CS
0b
Bit
Attr
Device: 5
Function: 2
Offset: 384h
Default
Description
31:5
RV
0h
Reserved
RWS
0b
RWS
0b
RWS
0b
RWS
0b
RWS
0b
MIFFERRST
Bus: 0
3.5.5.34
Offset: 380h
31:5
MIERRCTL
Bus: 0
3.5.5.33
Function: 2
Device: 5
Bit
Attr
Default
31:11
RV
0h
10:0
ROS-V
000h
Function: 2
Offset: 388h
Description
Reserved
Miscellaneous Error Status Log
MIFFERRHDR_[0:3]
Bus: 0
Device: 5
Bit
Attr
Default
31:0
ROS-V
000000
00h
Function: 2
Header
323
3.5.5.35
MIFNERRST
Bus: 0
Bit
3.5.5.36
Attr
RV
0h
10:0
ROS-V
000h
Reserved
Miscellaneous Error Status Log
Device: 5
Bit
Attr
Default
31:11
RV
0h
10:0
ROS-V
000h
Bit
Attr
Default
31:0
ROS-V
000000
00h
Offset: 3A0h
Description
Reserved
Miscellaneous Error Status Log
Function: 2
Header
Device: 5
Bit
Attr
Default
31:11
RV
0h
10:0
ROS-V
000h
Function: 2
Offset: 3B4h
Description
Reserved
Miscellaneous Error Status Log
MIERRCNTSEL
Bus: 0
324
Function: 2
MINNERRST
Bus: 0
3.5.5.39
Offset: 39Ch
Description
MINFERRHDR_[0:3]
Bus: 0
Device: 5
3.5.5.38
Function: 2
Default
31:11
MINFERRST
Bus: 0
3.5.5.37
Device: 5
Device: 5
Function: 2
Offset: 3BCh
Bit
Attr
Default
Description
31:5
RV
0h
Reserved
RW
0b
RW
0b
RW
0b
RW
0b
RW
0b
3.5.5.40
MIERRCNT
Bus: 0
Bit
3.5.6
Attr
Device: 5
Function: 2
Offset: 3C0h
Default
Description
31:8
RV
0h
Reserved
RW1CS
0b
6:0
RW1CS
00h
Error Accumulator
This counter accumulates errors that occur when the associated error type is
selected in the ERRCNTSEL register.
Notes:
This register is cleared by writing 7Fh.
Maximum counter available is 127d (7Fh).
3.5.6.1
MBAR
Bus: 0
3.5.6.2
Device: 5
Function: 4
Offset: 10h
Bit
Attr
Default
Description
31:12
RW
0h
BAR
This marks the 4KB aligned 32-bit base address for memory-mapped registers of
I/OxAPICSide note: Any accesses via JTAG mini port to registers pointed to by the
MBAR address, are not gated by MSE bit (in PCICMD register) being set, that is,
even if MSE bit is a 0, accesses to the registers pointed to by MBAR address are
allowed/completed normally. These accesses are accesses from internal microcode
and JTAG and they are allowed to access the registers normally even if this bit is
clear.
11:4
RO
0h
Reserved
RO
0b
Prefetchable
The IOxAPIC registers are not prefetchable.
2:1
RO
00b
RO
0b
Type
The IOAPIC registers can only be placed below 4G system address space.
Memory Space
This Base Address Register indicates memory space.
SVID
Bus: 0
Device: 5
Bit
Attr
Default
15:0
RW-O
8086h
Function: 4
Offset: 2Ch
Description
325
3.5.6.3
SDID
Bus: 0
3.5.6.4
Device: 5
Bit
Attr
Default
15:0
RW-O
0000h
Bit
Attr
Default
7:0
RO
00h
Function: 4
Offset: 3Ch
Description
Interrupt Line
N/A for these devices
Device: 5
Bit
Attr
Default
7:0
RO
00h
Function: 4
Offset: 3Dh
Description
Interrupt Pin
N/A since these devices do not generate any interrupt on their own
ABAR
Bus: 0
326
Description
Device: 5
INTPIN
Bus: 0
3.5.6.6
Offset: 2Eh
INTL
Bus: 0
3.5.6.5
Function: 4
Device: 5
Function: 4
Offset: 40h
Bit
Attr
Default
Description
15
RW
0b
ABAR Enable
When set, the range FECX_YZ00 to FECX_YZFF is enabled as an alternate access
method to the IOxAPIC registers and these addresses are claimed by the IIOs
internal I/OxAPIC regardless of the setting the MSE bit in the I/OxAPIC config
space. Bits XYZ are defined below.Side note: Any accesses via JTAG mini port to
registers pointed to by the ABAR address, are not gated by this bit being set, that
is, even if this bit is a 0, accesses to the registers pointed to by ABAR address are
allowed/completed normally. These accesses are accesses from internal microcode
and JTAG and they are allowed to access the registers normally even if this bit is
clear.
14:12
RO
0h
Reserved
11:8
RW
0h
7:4
RW
0h
ABAR
Bus: 0
3.5.6.7
Device: 5
Offset: 40h
Bit
Attr
Default
Description
3:0
RW
0h
PMCAP
Bus: 0
3.5.6.8
Function: 4
Device: 5
Function: 4
Offset: 6Ch
Bit
Attr
Default
Description
31:27
RO
0h
PME Support
Bits 31, 30 and 27 must be set to '1' for PCI-PCI bridge structures representing
ports on root complexes.
26
RO
0b
D2 Support
I/OxAPIC does not support power management state D2.
25
RO
0b
D1 Support
I/OxAPIC does not support power management state D1.
24:22
RO
0h
AUX Current
21
RO
0b
20
RV
0h
Reserved
19
RO
0b
PME Clock
This field is hardwired to 0h as it does not apply to PCI Express.
18:16
RW-O
011b
15:8
RO
00h
7:0
RO
01h
Capability ID
Provides the PM capability ID assigned by PCI-SIG.
Version
This field is set to 3h (PM 1.2 compliant) as version number. Bit is RW-O to make
the version 2h incase legacy OSes have any issues.
PMCSR
Bus: 0
Device: 5
Function: 4
Offset: 70h
Bit
Attr
Default
Description
31:24
RO
00h
23
RO
0h
22
RO
0h
B2/B3 Support
Not relevant for I/OxAPIC
Data
Not relevant for I/OxAPIC
21:16
RV
0h
Reserved
15
RO
0h
PME Status
Not relevant for I/OxAPIC
14:13
RO
0h
Data Scale
Not relevant for I/OxAPIC
327
PMCSR
Bus: 0
3.5.6.9
Device: 5
Attr
Default
12:9
RO
0h
Data Select
Not relevant for I/OxAPIC
RO
0h
PME Enable
Not relevant for I/OxAPIC
7:4
RV
0h
Reserved
RO
1b
No Soft Reset
Indicates I/OxAPIC does not reset its registers when transitioning from D3hot to
D0.
RV
0h
Reserved
1:0
RW-V
0h
Power State
This 2-bit field is used to determine the current power state of the function and to
set a new power state as well. 00: D0
01: D1 (not supported by IOAPIC)
10: D2 (not supported by IOAPIC)
11: D3_hot
If Software tries to write 01 or 10 to this field, the power state does not change
from the existing power state (which is either D0 or D3hot) and nor do these
bits1:0 change value.
When in D3hot state, I/OxAPIC will
a) respond to only Type 0 configuration transactions targeted at the devices
configuration space, when in D3hot state
c) will not respond to memory (that is, D3hot state is equivalent to MSE),
accesses to MBAR region (note: ABAR region access still go through in D3hot
state, if it enabled)
d) will not generate any MSI writes
Description
Device: 5
Function: 4
Offset: 80h
Bit
Attr
Default
Description
7:0
RW
0h
Index
When PECI/JTAG wants to read the indirect RTE registers of I/OxAPIC, this
register is used to point to the index of the indirect register, as defined in the I/
OxAPIC indirect memory space. Software writes to this register and then does a
read of the RDWINDOW register to read the contents at that index.Note h/w does
not preclude software from accessing this register over the coherent interface but
that is not what this register is defined for.
RDWINDOW
Bus: 0
328
Offset: 70h
Bit
RDINDEX
Bus: 0
3.5.6.10
Function: 4
Device: 5
Function: 4
Offset: 90h
Bit
Attr
Default
Description
31:0
RO
0h
Window
When SMBUS/JTAG reads this register, the data contained in the indirect register
pointed to by the RDINDEX register is returned on the read.
3.5.6.11
IOAPICTETPC
Bus: 0
Bit
3.5.6.12
Attr
Device: 5
Function: 4
Default
Offset: A0h
Description
31:17
RV
0h
Reserved
16
RW
0b
15:13
RV
0h
Reserved
12
RW
0b
11
RV
0h
Reserved
10
RW
0b
RV
0h
Reserved
RW
0b
RV
0h
Reserved
RW
0b
RV
0h
Reserved
RW
0b
3:1
RV
0h
Reserved
RW
0b
IOADSELS0
Bus: 0
Device: 5
Function: 4
Offset: 288h
Bit
Attr
Default
Description
31:29
RV
0h
Reserved
28
RWS
0b
27
RWS
0b
26:0
RWS
0h
gttcfg2SIpcIOADels0
gttcfg2SIpcIOADels0[26:0]
329
3.5.6.13
IOADSELS1
Bus: 0
Bit
3.5.6.14
Device: 5
Function: 4
Attr
Default
31:18
RV
0h
Reserved
17:0
RWS
0h
gttcfg2SIpcIOADels1
gttcfg2SIpcIOADels1[17:0]
Description
IOINTSRC0
Bus: 0
Device: 5
Bit
Attr
Default
31:0
RW-V
000000
00h
Function: 4
Offset: 2A0h
Description
Interrupt Source 0
bit interrupt
31:
INTD
30:
INTC
29:
INTB
28:
INTA
27:
INTD
26:
INTC
25:
INTB
24:
INTA
23:
INTD
22:
INTC
21:
INTB
20:
INTA
19:
INTD
18:
INTC
17:
INTB
16:
INTA
15:
INTD
14:
INTC
13:
INTB
12:
INTA
11:
INTD
10:
INTC
9:
INTB
8:
INTA
7:
INTD
6:
INTC
5:
INTB
4:
INTA
3:
INTD
2:
INTC
1:
INTB
0:
INTA
330
Offset: 28Ch
source
Port 3b
Port 3b
Port 3b
Port 3b
Port 3a
Port 3a
Port 3a
Port 3a
Port 1b
Port 1b
Port 1b
Port 1b
Port 1a
Port 1a
Port 1a
Port 1a
Port 2d
Port 2d
Port 2d
Port 2d
Port 2c
Port 2c
Port 2c
Port 2c
Port 2b
Port 2b
Port 2b
Port 2b
Port 2a
Port 2a
Port 2a
Port 2a
3.5.6.15
IOINTSRC1
Bus: 0
Bit
Attr
Device: 5
Function: 4
Default
31:21
RV
0h
20:0
RW-V
000000
h
Description
Reserved
Interrupt Source 1
bit interrupt
20:
INTA
19:
INTB
18:
INTC
17:
INTD
16:
INTA
15:
INTD
14:
INTC
13:
INTB
12:
INTA
11:
INTD
10:
INTC
9:
INTB
8:
INTA
7:
INTD
6:
INTC
5:
INTB
4:
INTA
3:
INTD
2:
INTC
1:
INTB
0:
INTA
3.5.6.16
source
Root Port Core
ME KT
ME IDE-R
ME HECI
ME HECI
Intel QuickData Technology
Intel QuickData Technology
Intel QuickData Technology
Intel QuickData Technology
Port 0/DMI
Port 0/DMI
Port 0/DMI
Port 0/DMI
Port 3d
Port 3d
Port 3d
Port 3d
Port 3c
Port 3c
Port 3c
Port 3c
IOREMINTCNT
Bus: 0
3.5.6.17
Offset: 2A4h
Device: 5
Function: 4
Offset: 2A8h
Bit
Attr
Default
Description
31:24
RW
0h
REM_INT_D_CNT
Number of remote interrupts D received
23:16
RW
0h
REM_INT_C_CNT
Number of remote interrupts C received
15:8
RW
0h
REM_INT_B_CNT
Number of remote interrupts B received
7:0
RW
0h
REM_INT_A_CNT
Number of remote interrupts A received
IOREMGPECNT
Bus: 0
Device: 5
Bit
Attr
Default
31:24
RV
0h
Function: 4
Offset: 2ACh
Description
Reserved
331
IOREMGPECNT
Bus: 0
3.5.6.18
Device: 5
Attr
Default
23:16
RW
0h
REM_HPGPE_CNT
Number of remote HPGPEs received
15:8
RW
0h
REM_PMGPE_CNT
Number of remote PMGPEs received
7:0
RW
0h
REM_GPE_CNT
Number of remote GPEs received
Description
Bit
Attr
Default
31
RWS
0b
EIE
30
RWS
0b
EIRFS
29:26
RV
0h
Reserved
25:24
RWS
0b
BFS
bfs[1:0]
23:22
RV
0h
Reserved
21:18
RWS
0b
Reserved[3
0]
17:4
RV
0h
Reserved
3:0
RWS
0b
PF
pf[3:0]
Function: 4
Offset: 2C0h
Description
FAUXGV: FauxGV
FAUXGV
Bus: 0
Bit
3.5.7
Offset: 2ACh
Bit
IOXAPICPARERRINJCTL
Bus: 0
Device: 5
3.5.6.19
Function: 4
Device: 5
Function: 4
Attr
Default
31:1
RV
0h
Reserved
RWS-L
0b
Faux GV Enable
Enable Faux GV
Offset: 2C4h
Description
332
0h
4h
8h
Ch
WNDW
10h
14h
18h
1Ch
PAR
20h
24h
28h
2Ch
30h
34h
38h
3Ch
EOI
40h
44h
48h
4Ch
50h
54h
58h
5Ch
60h
64h
333
Table 3-35. I/OxAPIC Indexed Registers (Redirection Table Entries) - WINDOW 0 Register Map Table
BCFG
ARBID
VER
APICID
0h
80h
4h
84h
8h
88h
Ch
8Ch
RTH1
RTL1
RTH0
RTL0
10h
90h
RTH3
RTL3
RTH2
RTL2
14h
94h
RTH5
RTL5
RTH4
RTL4
18h
98h
RTH7
RTL7
RTH6
RTL6
1Ch
9Ch
RTH9
RTL9
RTH8
RTL8
20h
A0h
RTH11
RTL11
RTH10
RTL10
24h
A4h
RTH13
RTL13
RTH12
RTL12
28h
A8h
RTH15
RTL15
RTH14
RTL14
2Ch
ACh
RTH17
RTL17
RTH16
RTL16
30h
B0h
RTH19
RTL19
RTH18
RTL18
34h
B4h
RTH21
RTL21
RTH20
RTL20
38h
B8h
RTH23
RTL23
RTH22
RTL22
3Ch
BCh
40h
C0h
44h
C4h
3.5.7.1
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
INDX: Index
The Index Register will select which indirect register appears in the window register to
be manipulated by software. Software will program this register to select the desired
APIC internal register.
334
INDX
Bus: 0
3.5.7.2
Device: 5
Offset: 0h
Bit
Attr
Default
7:0
RW-L
00h
Description
Index
Indirect register to access.
Notes:
Locked in D3hot state
Device: 5
Offset: 10h
Bit
Attr
Default
31:0
RW-LV
000000
00h
Function: 4
Description
Data to be written to the indirect register on writes, and location of read data from
the indirect register on reads.
Notes:
Locked in D3hot state
PAR: PAR
PAR
Bus: 0
3.5.7.4
WNDW: Window
WNDW
Bus: 0
3.5.7.3
Function: 4
Device: 5
Offset: 20h
Bit
Attr
Default
7:0
RO
0h
Function: 4
Description
Pin Assertion Register
IIO does not allow writes to the PAR to cause MSI interrupts.
EOI: EOI
EOI
Bus: 0
Device: 5
Offset: 40h
Function: 4
Bit
Attr
Default
Description
7:0
RW-L
00h
EOI
The EOI register is present to provide a mechanism to efficiently convert level
interrupts to edge triggered MSI interrupts. When a write is issued to this register,
the I/O(x)APIC will check the lower 8 bits written to this register, and compare it
with the vector field for each entry in the I/O Redirection Table. When a match is
found, the Remote_IRR bit for that I/O Redirection Entry will be cleared. Note that
if multiple I/O Redirection entries, for any reason, assign the same vector, each of
those entries will have the Remote_IRR bit reset to 0. This will cause the
corresponding I/OxAPIC entries to resample their level interrupt inputs and if they
are still asserted, cause more MSI interrupt(s) (if unmasked) which will again set
the Remote_IRR bit.
Notes:
Locked in D3hot state
335
3.5.7.5
APICID: APICID
This register uniquely identifies an APIC in the system. This register is not used by
OSes anymore and is still implemented in hardware because of FUD.
APICID
Bus: 0
3.5.7.6
Device: 5
Offset: 0h
Function: 4
Bit
Attr
Default
Description
27:24
RW
0b
APICID
Allows for up to 16 unique APIC IDs in the system.
23:0
RV
0h
Reserved
7:28
RV
0h
Reserved
VER: Version
This register uniquely identifies an APIC in the system. This register is not used by
OSes anymore and is still implemented in hardware because of FUD.
VER
Bus: 0
3.5.7.7
Device: 5
Offset: 1h
Function: 4
Bit
Attr
Default
Description
23:16
RO
17h
15
RO
0b
14:8
RV
0h
7:0
RO
20h
7:24
RV
0h
Version
This identifies the implementation version. This field is hardwired to 20h indicate
this is an I/OxAPIC.
Reserved
ARBID: Arbitration ID
This is a legacy register carried over from days of serial bus interrupt delivery. This
register has no meaning in IIO. It just tracks the APICID register for compatibility
reasons.
ARBID
Bus: 0
336
Device: 5
Offset: 2h
Function: 4
Bit
Attr
Default
27:24
RO
0b
Arbitration ID
Just tracks the APICID register.
23:0
RV
0h
Reserved
7:28
RV
0h
Reserved
Description
3.5.7.8
BCFG
Bus: 0
Bit
3.5.7.9
Device: 5
Offset: 3h
Attr
Function: 4
Default
Description
7:1
RV
0h
Reserved
RW
1b
Boot Configuration
This bit is a default1 to indicate FSB delivery mode. A value of 0 has no effect. Its
left as RW for software compatibility reasons.
Device: 5
Offset: 10h
Function: 4
Bit
Attr
Default
Description
17
RW
0b
Disable Flushing
This bit has no meaning in IIO. This bit is R/W for software compatibility reasons
only
16
RW
1b
Mask
When cleared, an edge assertion or level (depending on bit 15 in this register) on
the corresponding interrupt input results in delivery of an MSI interrupt using the
contents of the corresponding redirection table high/low entry. When set, an edge
or level on the corresponding interrupt input does not cause MSI Interrupts and no
MSI interrupts are held pending as well (that is, if an edge interrupt asserted
when the mask bit is set, no MSI interrupt is sent and the hardware does not
remember the event to cause an MSI later when the mask is cleared). When set,
assertion/deassertion of the corresponding interrupt input causes Assert/
Deassert_INTx messages to be sent to the legacy ICH, provided the Disable PCI
INTx Routing to ICH bit is clear. If the latter is set, Assert/Deassert_INTx
messages are not sent to the legacy ICH.
When mask bit goes from 1 to 0 for an entry and the entry is programmed for
level input, the input is sampled and if asserted, an MSI is sent. Also, if an
Assert_INTx message was previously sent to the legacy ICH/internal-coalescing
logic on behalf of the entry, when the mask bit is clear, then a Deassert_INTx
event is scheduled on behalf of the entry (whether this event results in a
Deassert_INTx message to the legacy ICH depends on whether there were other
outstanding Deassert_INTx messages from other sources). When the mask bit
goes from 0 to 1, and the corresponding interrupt input is already asserted, an
Assert_INTx event is scheduled on behalf of the entry. Note though that if the
interrupt is deasserted when the bit transitions from 0 to 1, a Deassert_INTx is
not scheduled on behalf of the entry.
15
RW
0b
Trigger Mode
This field indicates the type of signal on the interrupt input that triggers an
interrupt. 0 indicates edge sensitive, 1 indicates level sensitive.
14
RO
0b
Remote IRR
This bit is used for level triggered interrupts; its meaning is undefined for edge
triggered interrupts. For level triggered interrupts, this bit is set when an MSI
interrupt has been issued by the I/OxAPIC into the system fabric (noting that if
BME bit is clear or when the mask bit is set, no new MSI interrupts cannot be
generated and this bit cannot transition from 0 to 1 in those conditions). It is reset
(if set) when an EOI message is received from a local APIC with the appropriate
vector number, at which time the level interrupt input corresponding to the entry
is resampled causing one more MSI interrupt (if other enable bits are set) and
causing this bit to be set again.
337
RTL[0:23]
Bus: 0
3.5.7.10
Function: 4
Bit
Attr
Default
Description
13
RW
0b
12
RO
0b
Delivery Status
When trigger mode is set to level and the entry is unmasked, this bit indicates the
state of the level interrupt, that is, 1b if interrupt is asserted else 0b. When the
trigger mode is set to level but the entry is masked, this bit is always 0b. This bit
is always 0b when trigger mode is set to edge.
11
RW
0b
Destination Mode
0 - Physical1 - Logical
10:8
RW
0b
Delivery Mode
This field specifies how the APICs listed in the destination field should act upon
reception of the interrupt. Certain Delivery Modes will only operate as intended
when used in conjunction with a specific trigger mode. The encodings are:000 Fixed: Trigger Mode can be edge or level. Examine TM bit to determine.
001 - Lowest Priority: Trigger Mode can be edge or level. Examine TM bit to
determine.
010 - SMI/PMI: Trigger mode is always edge and TM bit is ignored.
011 - Reserved
100 - NMI. Trigger mode is always edge and TM bit is ignored.
101 - INIT. Trigger mode is always edge and TM bit is ignored.
110 - Reserved
111 - ExtINT. Trigger mode is always edge and TM bit is ignored.
7:0
RW
0h
Vector
This field contains the interrupt vector for this interrupt
7:18
RV
0h
Reserved
RTH[0:23]
Bus: 0
338
Device: 5
Offset: 10h
Device: 5
Offset: 11h
Function: 4
Bit
Attr
Default
Description
31:24
RW
00h
Destination ID
They are bits [19:12] of the MSI address.
23:16
RW
00h
Extended Destination ID
These bits become bits [11:4] of the MSI address.
15:0
RV
0h
Reserved
7:32
RV
0h
Reserved
3.5.8
Figure 3-3.
339
Table 3-36. Intel VT-d Memory Mapped Registers - 0x00 - 0xFF (VTD0)
VTD0_VERSION
0h
4h
8h
VTD0_CAP
Ch
10h
VTD0_EXT_CAP
14h
VTD0_INV_QUEUE_TAIL
VTD0_INV_QUEUE_ADD
80h
84h
88h
8Ch
90h
94h
VTD0_GLBCMD
18h
VTD0_GLBSTS
1Ch
VTD0_INV_COMP_STATUS
9Ch
20h
VTD0_INV_COMP_EVT_CTL
A0h
24h
VTD0_INV_COMP_EVT_DATA
VTD0_ROOTENTRYADD
28h
VTD0_CTXCMD
2Ch
98h
VTD0_INV_COMP_EVT_ADDR
A4h
A8h
ACh
30h
B0h
B4h
VTD0_FLTSTS
34h
VTD0_FLTEVTCTRL
38h
VTD0_FLTEVTDATA
3Ch
VTD0_FLTEVTADDR
VTD0_INTR_REMAP_TABLE_BASE
B8h
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
VTD0_PMEN
64h
E4h
VTD0_PROT_LOW_MEM_BASE
68h
E8h
VTD0_PROT_LOW_MEM_LIMIT
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
VTD0_PROT_HIGH_MEM_BASE
VTD0_PROT_HIGH_MEM_LIMIT
340
VTD0_INV_QUEUE_HEAD
Table 3-37. Intel VT-d Memory Mapped Registers - 0x100 - 0x1FC (VTD0)
VTD0_FLTREC0_GPA
VTD0_FLTREC0_SRC
VTD0_FLTREC1_GPA
VTD0_FLTREC1_SRC
VTD0_FLTREC2_GPA
VTD0_FLTREC2_SRC
VTD0_FLTREC3_GPA
VTD0_FLTREC3_SRC
VTD0_FLTREC4_GPA
VTD0_FLTREC4_SRC
VTD0_FLTREC5_GPA
VTD0_FLTREC5_SRC
VTD0_FLTREC6_GPA
VTD0_FLTREC6_SRC
VTD0_FLTREC7_GPA
VTD0_FLTREC7_SRC
100h
180h
104h
184h
108h
188h
10Ch
18Ch
110h
190h
114h
194h
118h
198h
11Ch
19Ch
120h
1A0h
124h
1A4h
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
148h
1C8h
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
341
Table 3-38. Intel VT-d Memory Mapped Registers - 0x200 - 0x2FC (VTD0), 0x1200 - 0x12FC (VTD1)
VTD0_INVADDRREG
VTD0_IOTLBINV
200h
280h
204h
284h
208h
288h
20Ch
28Ch
210h
290h
214h
294h
218h
298h
21Ch
29Ch
220h
2A0h
224h
2A4h
228h
2A8h
22Ch
2ACh
230h
2B0h
234h
2B4h
238h
2B8h
23Ch
2BCh
240h
2C0h
244h
2C4h
248h
2C8h
24Ch
2CCh
250h
2D0h
254h
2D4h
258h
2D8h
25Ch
2DCh
260h
2E0h
264h
2E4h
268h
2E8h
26Ch
2ECh
270h
2F0h
274h
2F4h
278h
2F8h
27Ch
2FCh
Table 3-39. Intel VT-d Memory Mapped Registers -1000-11FC (VTD1) (Sheet 1 of 2)
VTD1_VERSION
1000h
1004h
VTD1_CAP
VTD1_EXT_CAP
342
1008h
100Ch
1010h
1014h
VTD1_GLBCMD
1018h
VTD1_GLBSTS
101Ch
VTD1_INV_QUEUE_HEAD
VTD1_INV_QUEUE_TAIL
VTD1_INV_QUEUE_ADD
1080h
1084h
1088h
108Ch
1090h
1094h
1098h
VTD1_INV_COMP_STATUS
109Ch
Table 3-39. Intel VT-d Memory Mapped Registers -1000-11FC (VTD1) (Sheet 2 of 2)
VTD1_ROOTENTRYADD
VTD1_CTXCMD
1020h
VTD1_INV_COMP_EVT_CTL
1024h
VTD1_INV_COMP_EVT_DATA
1028h
102Ch
10A4h
10A8h
10ACh
1030h
10B0h
10B4h
VTD1_FLTSTS
1034h
VTD1_FLTEVTCTRL
1038h
VTD1_FLTEVTDATA
103Ch
VTD1_FLTEVTADDR
VTD1_INV_COMP_EVT_ADDR
10A0h
VTD1_INTR_REMAP_TABLE_BASE
10B8h
10BCh
1040h
10C0h
1044h
10C4h
1048h
10C8h
104Ch
10CCh
1050h
10D0h
1054h
10D4h
1058h
10D8h
105Ch
10DCh
1060h
10E0h
VTD1_PMEN
1064h
10E4h
VTD1_PROT_LOW_MEM_BASE
1068h
10E8h
VTD1_PROT_LOW_MEM_LIMIT
106Ch
10ECh
1070h
10F0h
1074h
10F4h
1078h
10F8h
107Ch
10FCh
VTD1_PROT_HIGH_MEM_BASE
VTD1_PROT_HIGH_MEM_LIMIT
Table 3-40. Intel VT-d Memory Mapped Registers - 0x1100 - 0x11FC (VTD1) (Sheet 1 of
2)
VTD1_FLTREC0_GPA
VTD1_FLTREC0_SRC
1100h
1180h
1104h
1184h
1108h
1188h
110Ch
118Ch
1110h
1190h
1114h
1194h
1118h
1198h
111Ch
119Ch
1120h
11A0h
1124h
11A4h
1128h
11A8h
112Ch
11ACh
1130h
11B0h
1134h
11B4h
1138h
11B8h
113Ch
11BCh
343
Table 3-40. Intel VT-d Memory Mapped Registers - 0x1100 - 0x11FC (VTD1) (Sheet 2 of
2)
3.5.8.1
Bit
Attr
11C4h
1148h
11C8h
114Ch
11CCh
1150h
11D0h
1154h
11D4h
1158h
11D8h
115Ch
11DCh
1160h
11E0h
1164h
11E4h
1168h
11E8h
116Ch
11ECh
1170h
11F0h
1174h
11F4h
1178h
11F8h
117Ch
11FCh
Device: 5
Offset: 0h
Function: 0
Default
Description
31:8
RV
0h
Reserved
7:4
RO
1h
Major Revision
3:0
RO
0h
Minor Revision
VTD0_CAP
Bus: 0
344
11C0h
1144h
VTD0_VERSION
Bus: 0
3.5.8.2
1140h
Device: 5
Offset: 8h
Function: 0
Bit
Attr
Default
Description
63:56
RV
0h
Reserved
55
RO
1b
54
RO
1b
53:48
RO
12h
MAMV
Intel Xeon Processor E5 Product Family support MAMV value of 12h (up to 1G
super pages).
47:40
RO
07h
39
RO
1b
VTD0_CAP
Bus: 0
3.5.8.3
Device: 5
Offset: 8h
Function: 0
Bit
Attr
Default
Description
38
RV
0h
Reserved
37:34
RWO
3h
33:24
RO
10h
23
RW-O
0b
ISOCH
Remapping Engine has ISOCH Support.
Note: This bit used to be for Spatial Separation. This is no longer the case.
22
RWO
1b
ZLR
ZLR: Zero-length DMA requests to write-only pages supported.
21:16
RO
2Fh
MGAW
This register is set by Intel Xeon Processor E5 Product Family-based on the setting
of the GPA_LIMIT register. The value is the same for both the Azalia and nonAzalia engines. This is because the translation for Azalia has been extended to be
4-level (instead of 3).
15:13
RV
0h
Reserved
12:8
RO
04h
RO
0b
CM
Intel Xeon Processor E5 Product Family does not cache invalid pages.
This bit should always be set to 0 on HW. It can be set to one when we are doing
software virtualization of Intel VT-d.
RO
1b
PHMR Support
Intel Xeon Processor E5 Product Family supports protected high memory range
RO
1b
PLMR Support
Intel Xeon Processor E5 Product Family supports protected low memory range
RO
0b
RWBF
N/A for Intel Xeon Processor E5 Product Family
RO
0b
2:0
RO
010b
SAGAW
Supports 4-level walk on both Azalia and non-azalia engines.
VTD0_EXT_CAP
Bus: 0
Bit
Device: 5
Offset: 10h
Function: 0
Attr
Default
Description
63:24
RV
0h
Reserved
23:20
RO
Fh
19:18
RV
0h
Reserved
17:8
RO
20h
345
VTD0_EXT_CAP
Bus: 0
3.5.8.4
Function: 0
Bit
Attr
Default
Description
RWO
1b
Snoop Control
0: Hardware does not support 1-setting of the SNP field in the page-table entries.
1: Hardware supports the 1-setting of the SNP field in the page-table entries.
IIO supports snoop override only for the non-isoch Intel VT-d engine
RO
1b
Pass through
IIO supports pass through.
RO
1b
Reserved
RO
1b
RWO
1b
RW-O
1b
RWO
1b
RW-O
0b
Coherency Support
BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the
DMA/Interrupt table structures in memory (root/context/pd/pt/irt). Note that this
bit is expected to be always set to 0 for the Azalia Intel VT-d engine and
programmability is only provided for that engine for debug reasons.
VTD0_GLBCMD
Bus: 0
346
Device: 5
Offset: 10h
Device: 5
Offset: 18h
Function: 0
Bit
Attr
Default
Description
31
RW
0b
Translation Enable
Software writes to this field to request hardware to enable/disable DMAremapping hardware.0: Disable DMA-remapping hardware
1: Enable DMA-remapping hardware
Hardware reports the status of the translation enable operation through the TES
field in the Global Status register. Before enabling (or re-enabling) DMAremapping hardware through this field, software must:
- Setup the DMA-remapping structures in memory
- Flush the write buffers (through WBF field), if write buffer flushing is reported as
required.
- Set the root-entry table pointer in hardware (through SRTP field).
- Perform global invalidation of the context-cache and global invalidation of IOTLB
- If advanced fault logging supported, setup fault log pointer (through SFL field)
and enable advanced fault logging (through EAFL field).
There may be active DMA requests in the platform when software updates this
field. Hardware must enable or disable remapping logic only at deterministic
transaction boundaries, so that any in-flight transaction is either subject to
remapping or not at all.
VTD0_GLBCMD
Bus: 0
Device: 5
Offset: 18h
Function: 0
Bit
Attr
Default
Description
30
RW
0b
29
RO
0b
28
RO
0b
27
RO
0b
26
RW
0b
25
RW
0b
347
VTD0_GLBCMD
Bus: 0
3.5.8.5
Function: 0
Bit
Attr
Default
Description
24
RW
0b
23
RW
0b
22:0
RV
0h
Reserved
VTD0_GLBSTS
Bus: 0
348
Device: 5
Offset: 18h
Device: 5
Offset: 1Ch
Function: 0
Bit
Attr
Default
Description
31
RO
0b
30
RO
0b
29
RO
0b
28
RO
0b
VTD0_GLBSTS
Bus: 0
3.5.8.6
Device: 5
Offset: 1Ch
Function: 0
Bit
Attr
Default
Description
27
RO
0b
26
RO
0b
25
RO
0b
24
RO
0b
23
RO
0b
22:0
RV
0h
Reserved
VTD0_ROOTENTRYADD
Bus: 0
Device: 5
Offset: 20h
Function: 0
Bit
Attr
Default
Description
63:12
RW
0h
11:0
RV
0h
Reserved
349
3.5.8.7
VTD0_CTXCMD
Bus: 0
350
Device: 5
Offset: 28h
Function: 0
Bit
Attr
Default
Description
63
RW
0b
62:61
RW
0b
60:59
RO
0b
58:34
RV
0h
33:32
RW
00b
Function Mask
Used by Intel Xeon Processor E5 Product Family when performing device selective
invalidation.
31:16
RW
0h
Source ID
Used by Intel Xeon Processor E5 Product Family when performing device selective
context cache invalidation.
15:0
RW
0h
Domain ID
Indicates the id of the domain whose context-entries needs to be selectively
invalidated. S/W needs to program this for both domain and device selective
invalidates. Intel Xeon Processor E5 Product Family ignores bits 15:8 since it
supports only a 8 bit Domain ID.
3.5.8.8
VTD0_FLTSTS
Bus: 0
Bit
3.5.8.9
Attr
Device: 5
Offset: 34h
Function: 0
Default
Description
31:16
RV
0h
Reserved
15:8
ROS-V
0h
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
3:2
RV
0h
Reserved
ROS-V
0b
RW1CS
0b
VTD0_FLTEVTCTRL
Bus: 0
Device: 5
Offset: 38h
Function: 0
Bit
Attr
Default
Description
31
RW
1b
351
VTD0_FLTEVTCTRL
Bus: 0
Device: 5
Offset: 38h
3.5.8.10
Attr
Default
Description
30
RO
0b
Interrupt Pending
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as when an interrupt condition occurs when hardware records
a fault through one of the Fault Recording registers and sets the PPF field in Fault
Status register. - Hardware detected error associated with the Invalidation Queue,
setting the IQE field in the Fault Status register.
- Hardware detected invalidation completion timeout error, setting the ICT field in
the Fault Status register.
- If any of the above status fields in the Fault Status register was already set at
the time of setting any of these fields, it is not treated as a new interrupt
condition.
The IP field is kept set by hardware while the interrupt message is held pending.
The interrupt message could be held pending due to interrupt mask (IM field)
being set, or due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either
(a) Hardware issuing the interrupt message due to either change in the transient
hardware condition that caused interrupt message to be held pending or due to
software clearing the IM field.
(b) Software servicing all the pending interrupt status fields in the Fault Status
register.
- PPF field is cleared by hardware when it detects all the Fault Recording registers
have Fault (F) field clear.
- Other status fields in the Fault Status register is cleared by software writing back
the value read from the respective fields.
29:0
RV
0h
Reserved
Function: 0
Bit
Attr
Default
31:16
RV
0h
Reserved
15:0
RW
0h
Interrupt Data
Description
VTD0_FLTEVTADDR
Bus: 0
Device: 5
Offset: 40h
352
Bit
VTD0_FLTEVTDATA
Bus: 0
Device: 5
Offset: 3Ch
3.5.8.11
Function: 0
Bit
Attr
Default
63:2
RW
000000
000000
0000h
1:0
RV
0h
Function: 0
Description
Interrupt Address
The interrupt address is interpreted as the address of any other interrupt from a
PCI Express port.
Reserved
3.5.8.12
VTD0_PMEN
Bus: 0
3.5.8.13
Device: 5
Offset: 64h
Bit
Attr
Default
Description
31
RW-LB
0b
30:1
RV
0h
Reserved
RO
0b
VTD0_PROT_LOW_MEM_BASE
Bus: 0
Device: 5
Offset: 68h
3.5.8.14
Function: 0
Function: 0
Bit
Attr
Default
Description
31:21
RW-LB
000h
20:0
RV
0h
Reserved
VTD0_PROT_LOW_MEM_LIMIT
Bus: 0
Device: 5
Offset: 6Ch
Function: 0
Bit
Attr
Default
Description
31:21
RW-LB
000h
20:0
RV
0h
Reserved
353
3.5.8.15
VTD0_PROT_HIGH_MEM_BASE
Bus: 0
Device: 5
Offset: 70h
3.5.8.16
Attr
Default
Description
63:21
RW-LB
000000
00000h
20:0
RV
0h
Reserved
Attr
Default
Description
63:21
RW-LB
000000
00000h
20:0
RV
0h
Reserved
Bit
Attr
Default
63:19
RV
0h
18:4
RO-V
0000h
3:0
RV
0h
Function: 0
Description
Reserved
Queue Head
Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be fetched next by hardware. This field is incremented after the command
has been fetched successfully and has been verified to be a valid/supported
command.
Reserved
VTD0_INV_QUEUE_TAIL
Bus: 0
Device: 5
Offset: 88h
354
Function: 0
Bit
VTD0_INV_QUEUE_HEAD
Bus: 0
Device: 5
Offset: 80h
3.5.8.18
Bit
VTD0_PROT_HIGH_MEM_LIMIT
Bus: 0
Device: 5
Offset: 78h
3.5.8.17
Function: 0
Bit
Attr
Default
63:19
RV
0h
Function: 0
Description
Reserved
VTD0_INV_QUEUE_TAIL
Bus: 0
Device: 5
Offset: 88h
3.5.8.19
Bit
Attr
Default
18:4
RW
0000h
3:0
RV
0h
Queue Tail
Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be written next by software.
Reserved
Bit
Attr
Default
63:12
RW
000000
000000
0h
Function: 0
Description
Invalidation Request Queue Base Address
This field points to the base of size-aligned invalidation request queue.
11:3
RV
0h
Reserved
2:0
RW
0h
Queue Size
This field specifies the length of the invalidation request queue. The number of
entries in the invalidation queue is defined as 2^(X + 8), where X is the value
programmed in this field.
VTD0_INV_COMP_STATUS
Bus: 0
Device: 5
Offset: 9Ch
Bit
3.5.8.21
Description
VTD0_INV_QUEUE_ADD
Bus: 0
Device: 5
Offset: 90h
3.5.8.20
Function: 0
Attr
Function: 0
Default
Description
31:1
RV
0h
Reserved
RW1CS
0b
VTD0_INV_COMP_EVT_CTL
Bus: 0
Device: 5
Offset: A0h
Function: 0
Bit
Attr
Default
Description
31
RW
1b
Interrupt Mask
0: No masking of interrupt. When a invalidation event condition is detected,
hardware issues an interrupt message (using the Invalidation Event Data &
Invalidation Event Address register values).
1: This is the value on reset. Software may mask interrupt message generation by
setting this field. Hardware is prohibited from sending the interrupt message when
this field is set.
355
VTD0_INV_COMP_EVT_CTL
Bus: 0
Device: 5
Offset: A0h
3.5.8.22
Attr
Default
Description
30
RO
0b
Interrupt Pending
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as:- An Invalidation Wait Descriptor with Interrupt Flag (IF)
field set completed, setting the IWC field in the Fault Status register.
- If the IWC field in the Invalidation Event Status register was already set at the
time of setting this field, it is not treated as a new interrupt condition. The IP field
is kept set by hardware while the interrupt message is held pending. The interrupt
message could be held pending due to interrupt mask (IM field) being set, or due
to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either:
(a) Hardware issuing the interrupt message due to either change in the transient
hardware condition that caused interrupt message to be held pending or due to
software clearing the IM field.
(b) Software servicing the IWC field in the Fault Status register.
29:0
RV
0h
Reserved
Attr
Default
31:16
RV
0h
Reserved
15:0
RW
0h
Interrupt Data
Description
Function: 0
Bit
Attr
Default
63:2
RW
0h
Interrupt Address
1:0
RV
0h
Reserved
Description
VTD0_INTR_REMAP_TABLE_BASE
Bus: 0
Device: 5
Offset: B8h
356
Function: 0
Bit
VTD0_INV_COMP_EVT_ADDR
Bus: 0
Device: 5
Offset: A8
3.5.8.24
Bit
VTD0_INV_COMP_EVT_DATA
Bus: 0
Device: 5
Offset: A4h
3.5.8.23
Function: 0
Bit
Attr
Default
63:12
RW
0h
Function: 0
Description
Intr Remap Base
This field points to the base of page-aligned interrupt remapping table. If the
Interrupt Remapping Table is larger than 4KB in size, it must be sizealigned.Reads of this field returns value that was last programmed to it.
VTD0_INTR_REMAP_TABLE_BASE
Bus: 0
Device: 5
Offset: B8h
3.5.8.25
Bit
Attr
Default
Description
11
RW-LB
0b
10:4
RV
0h
Reserved
3:0
RW
0b
Size
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^(X+1), where X is the value
programmed in this field.
VTD0_FLTREC0_GPA
Bus: 0
Device: 5
Offset: 100h
3.5.8.26
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
VTD0_FLTREC0_SRC
Bus: 0
Device: 5
Offset: 108h
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
357
3.5.8.27
VTD0_FLTREC1_GPA
Bus: 0
Device: 5
Offset: 110h
3.5.8.28
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
VTD0_FLTREC2_GPA
Bus: 0
Device: 5
Offset: 120h
358
Bit
VTD0_FLTREC1_SRC
Bus: 0
Device: 5
Offset: 118h
3.5.8.29
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
3.5.8.30
VTD0_FLTREC2_SRC
Bus: 0
Device: 5
Offset: 128h
3.5.8.31
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
VTD0_FLTREC3_GPA
Bus: 0
Device: 5
Offset: 130h
3.5.8.32
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
VTD0_FLTREC3_SRC
Bus: 0
Device: 5
Offset: 138h
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
359
VTD0_FLTREC3_SRC
Bus: 0
Device: 5
Offset: 138h
3.5.8.33
Bit
Attr
Default
62
ROS-V
0b
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
Function: 0
Bit
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
VTD0_FLTREC4_SRC
Bus: 0
Device: 5
Offset: 148h
360
Description
VTD0_FLTREC4_GPA
Bus: 0
Device: 5
Offset: 140h
3.5.8.34
Function: 0
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
VTD0_FLTREC4_SRC
Bus: 0
Device: 5
Offset: 148h
3.5.8.35
Bit
Attr
Default
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Description
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
VTD0_FLTREC5_GPA
Bus: 0
Device: 5
Offset: 150h
3.5.8.36
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
VTD0_FLTREC5_SRC
Bus: 0
Device: 5
Offset: 158h
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
361
3.5.8.37
VTD0_FLTREC6_GPA
Bus: 0
Device: 5
Offset: 160h
3.5.8.38
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
VTD0_FLTREC7_GPA
Bus: 0
Device: 5
Offset: 170h
362
Bit
VTD0_FLTREC6_SRC
Bus: 0
Device: 5
Offset: 168h
3.5.8.39
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
3.5.8.40
VTD0_FLTREC7_SRC
Bus: 0
Device: 5
Offset: 178h
3.5.8.41
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
VTD0_INVADDRREG
Bus: 0
Device: 5
Offset: 200h
Function: 0
Bit
Attr
Default
Description
63:12
RW
000000
000000
0h
11:7
RV
0h
Reserved
RW
0b
ih
The field provides hint to hardware to preserve or flush the respective non-leaf
page-table entries that may be cached in hardware.0: Software may have
modified both leaf and non-leaf page-table entries corresponding to mappings
specified in the ADDR and AM fields. On a page-selective invalidation request, IIO
must flush both the cached leaf and nonleaf page-table entries corresponding to
mappings specified by ADDR and AM fields. IIO performs a domain-level
invalidation on non-leaf entries and page-selective-domain-level invalidation at
the leaf level
1: Software has not modified any non-leaf page-table entries corresponding to
mappings specified in the ADDR and AM fields. On a page-selective invalidation
request, IIO preserves the cached non-leaf page-table entries corresponding to
mappings specified by ADDR and AM fields and performs only a page-selective
invalidation at the leaf level
5:0
RW
0h
am
IIO supports values of 0-9. All other values result in undefined results.
addr
To request a page-specific invalidation request to hardware, software must first
write the corresponding guest physical address to this register, and then issue a
page-specific invalidate command through the IOTLB_REG.
363
3.5.8.42
VTD0_IOTLBINV
Bus: 0
Device: 5
Offset: 208h
364
Function: 0
Bit
Attr
Default
Description
63
RW
0b
62
RV
0h
Reserved
61:60
RW
00b
59
RV
0h
58:57
RO
00b
Reserved
56:50
RV
0h
Reserved
49
RW
0b
dr
Intel Xeon Processor E5 Family uses this to drain or not drain reads on an
invalidation request.
48
RW
0b
dw
Intel Xeon Processor E5 Family uses this to drain or not drain writes on an
invalidation request.
47:32
RW
0000h
31:0
RV
0h
did
Domain to be invalidated and is programmed by software for both page and
domain selective invalidation requests. Intel Xeon Processor E5 Family ignores the
bits 47:40 since it supports only an 8 bit Domain ID.
Reserved
3.5.8.43
VTD1_VERSION
Bus: 0
Bit
3.5.8.44
Attr
Device: 5
Offset: 1000h
Function: 0
Default
Description
31:8
RV
0h
Reserved
7:4
RO
1h
Major Revision
3:0
RO
0h
Minor Revision
VTD1_CAP
Bus: 0
Bit
Attr
Device: 5
Offset: 1008h
Function: 0
Default
Description
63:56
RV
0h
Reserved
55
RO
1b
54
RO
1b
53:48
RO
12h
MAMV
Intel Xeon Processor E5 Family support MAMV value of 12h (up to 1G super
pages).
47:40
RO
00h
39
RO
1b
38
RV
0h
Reserved
37:34
RWO
3h
33:24
RO
10h
23
RW-O
1b
ISOCH
Remapping Engine has ISOCH Support.
Note: This bit used to be for Spatial Separation. This is no longer the case.
22
RWO
1b
ZLR
Zero-length DMA requests to write-only pages supported.
21:16
RO
2Fh
MGAW
This register is set by Intel Xeon Processor E5 Family based on the setting of the
GPA_LIMIT register. The value is the same for both the Azalia and non-Azalia
engines. This is because the translation for Azalia has been extended to be 4-level
(instead of 3).
15:13
RV
0h
Reserved
12:8
RO
04h
RO
0b
CM
Intel Xeon Processor E5 Family does not cache invalid pages
RO
1b
PHMR Support
Intel Xeon Processor E5 Family supports protected high memory range
SAGAW
Supports 4-level walks on both Azalia and non-Azalia Intel VT-d engines.
365
VTD1_CAP
Bus: 0
3.5.8.45
Function: 0
Bit
Attr
Default
RO
1b
PLMR Support
Intel Xeon Processor E5 Family supports protected low memory range
RO
0b
RWBF
N/A for Intel Xeon Processor E5 Family
RO
0b
2:0
RO
010b
Description
VTD1_EXT_CAP
Bus: 0
Bit
366
Device: 5
Offset: 1008h
Device: 5
Offset: 1010h
Function: 0
Attr
Default
Description
63:24
RV
0h
Reserved
23:20
RO
Fh
19:18
RV
0h
Reserved
17:8
RO
20h
RWO
0b
Snoop Control
0: Hardware does not support 1-setting of the SNP field in the page-table
entries.1: Hardware supports the 1-setting of the SNP field in the page-table
entries.
IIO supports snoop override only for the non-isoch Intel VT-d engine
RW-O
1b
Pass through
IIO supports pass through.
RO
1b
Reserved
RO
1b
RWO
1b
RO
0b
RWO
1b
RW-O
0b
Coherency Support
BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the
DMA/Interrupt table structures in memory (root/context/pd/pt/irt). Note that this
bit is expected to be always set to 0 for the Azalia Intel VT-d engine and
programmability is only provided for that engine for debug reasons.
3.5.8.46
VTD1_GLBCMD
Bus: 0
Device: 5
Offset: 1018h
Function: 0
Bit
Attr
Default
Description
31
RW
0b
Translation Enable
Software writes to this field to request hardware to enable/disable DMAremapping hardware.0: Disable DMA-remapping hardware
1: Enable DMA-remapping hardware
Hardware reports the status of the translation enable operation through the TES
field in the Global Status register. Before enabling (or re-enabling) DMAremapping hardware through this field, software must:
- Setup the DMA-remapping structures in memory
- Flush the write buffers (through WBF field), if write buffer flushing is reported as
required.
- Set the root-entry table pointer in hardware (through SRTP field).
- Perform global invalidation of the context-cache and global invalidation of IOTLB
- If advanced fault logging supported, setup fault log pointer (through SFL field)
and enable advanced fault logging (through EAFL field).
There may be active DMA requests in the platform when software updates this
field. Hardware must enable or disable remapping logic only at deterministic
transaction boundaries, so that any in-flight transaction is either subject to
remapping or not at all.
30
RW
0b
29
RO
0b
28
RO
0b
27
RO
0b
26
RW
0b
367
VTD1_GLBCMD
Bus: 0
368
Device: 5
Offset: 1018h
Function: 0
Bit
Attr
Default
Description
25
RW
0b
24
RW
0b
23
RW
0b
22:0
RV
0h
Reserved
3.5.8.47
VTD1_GLBSTS
Bus: 0
3.5.8.48
Device: 5
Offset: 101Ch
Function: 0
Bit
Attr
Default
Description
31
RO
0b
30
RO
0b
29
RO
0b
28
RO
0b
27
RO
0b
26
RO
0b
25
RO
0b
24
RO
0b
23
RO
0b
22:0
RV
0h
Reserved
VTD1_ROOTENTRYADD
Bus: 0
Device: 5
Offset: 1020h
Function: 0
Bit
Attr
Default
Description
63:12
RW
0h
11:0
RV
0h
Reserved
369
3.5.8.49
VTD1_CTXCMD
Bus: 0
370
Device: 5
Offset: 1028h
Function: 0
Bit
Attr
Default
Description
63
RW
0b
62:61
RW
0b
60:59
RO
0b
58:34
RV
0h
33:32
RW
00b
31:16
RW
0h
Source ID
Used by Processor when performing device selective context cache invalidation.
15:0
RW
0h
Domain ID
Indicates the id of the domain whose context-entries needs to be selectively
invalidated. S/W needs to program this for both domain and device selective
invalidates. Intel Xeon Processor E5 Product Family ignores bits 15:8 since it
supports only a 8 bit Domain ID.
fm
Used by Processor when performing device selective invalidation.
3.5.8.50
VTD1_FLTSTS
Bus: 0
Bit
3.5.8.51
Attr
Device: 5
Offset: 1034h
Function: 0
Default
Description
31:16
RV
0h
Reserved
15:8
ROS-V
0h
RV
0h
Reserved
RW1CS
0b
RW1CS
0b
RW1CS
0b
3:2
RV
0h
Reserved
ROS-V
0b
RW1CS
0b
VTD1_FLTEVTCTRL
Bus: 0
Device: 5
Offset: 1038h
Function: 0
Bit
Attr
Default
Description
31
RW
1b
371
VTD1_FLTEVTCTRL
Bus: 0
Device: 5
Offset: 1038h
3.5.8.52
Attr
Default
Description
30
RO
0b
Interrupt Pending
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as when an interrupt condition occurs when hardware records
a fault through one of the Fault Recording registers and sets the PPF field in Fault
Status register. - Hardware detected error associated with the Invalidation Queue,
setting the IQE field in the Fault Status register.
- Hardware detected invalidation completion timeout error, setting the ICT field in
the Fault Status register.
- If any of the above status fields in the Fault Status register was already set at
the time of setting any of these fields, it is not treated as a new interrupt
condition.
The IP field is kept set by hardware while the interrupt message is held pending.
The interrupt message could be held pending due to interrupt mask (IM field)
being set, or due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either
(a) Hardware issuing the interrupt message due to either change in the transient
hardware condition that caused interrupt message to be held pending or due to
software clearing the IM field.
(b) Software servicing all the pending interrupt status fields in the Fault Status
register.
- PPF field is cleared by hardware when it detects all the Fault Recording registers
have Fault (F) field clear.
- Other status fields in the Fault Status register is cleared by software writing back
the value read from the respective fields.
29:0
RV
0h
Reserved
Function: 0
Bit
Attr
Default
31:16
RV
0h
Reserved
15:0
RW
0h
Interrupt Data
Description
VTD1_FLTEVTADDR
Bus: 0
Device: 5
Offset: 1040h
372
Bit
VTD1_FLTEVTDATA
Bus: 0
Device: 5
Offset: 103Ch
3.5.8.53
Function: 0
Bit
Attr
Default
63:2
RW
000000
000000
0000h
1:0
RV
0h
Function: 0
Description
Interrupt Address
The interrupt address is interpreted as the address of any other interrupt from a
PCI Express port.
Reserved
3.5.8.54
VTD1_PMEN
Bus: 0
3.5.8.55
Device: 5
Offset: 1064h
Bit
Attr
Default
Description
31
RW-LB
0b
30:1
RV
0h
Reserved
RO
0b
VTD1_PROT_LOW_MEM_BASE
Bus: 0
Device: 5
Offset: 1068h
3.5.8.56
Function: 0
Function: 0
Bit
Attr
Default
Description
31:21
RW-LB
000h
20:0
RV
0h
Reserved
VTD1_PROT_LOW_MEM_LIMIT
Bus: 0
Device: 5
Offset: 106Ch
Function: 0
Bit
Attr
Default
Description
31:21
RW-LB
000h
20:0
RV
0h
Reserved
373
3.5.8.57
VTD1_PROT_HIGH_MEM_BASE
Bus: 0
Device: 5
Offset: 1070h
3.5.8.58
Attr
Default
Description
63:21
RW-LB
000000
00000h
20:0
RV
0h
Reserved
Attr
Default
Description
63:21
RW-LB
000000
00000h
20:0
RV
0h
Reserved
Bit
Attr
Default
63:19
RV
0h
18:4
RO-V
0000h
3:0
RV
0h
Function: 0
Description
Reserved
Queue Head
Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be fetched next by hardware. This field is incremented after the command
has been fetched successfully and has been verified to be a valid/supported
command.
Reserved
VTD1_INV_QUEUE_TAIL
Bus: 0
Device: 5
Offset: 1088h
374
Function: 0
Bit
VTD1_INV_QUEUE_HEAD
Bus: 0
Device: 5
Offset: 1080h
3.5.8.60
Bit
VTD1_PROT_HIGH_MEM_LIMIT
Bus: 0
Device: 5
Offset: 1078h
3.5.8.59
Function: 0
Bit
Attr
Default
63:19
RV
0h
Function: 0
Description
Reserved
VTD1_INV_QUEUE_TAIL
Bus: 0
Device: 5
Offset: 1088h
3.5.8.61
Attr
Default
Description
18:4
RW
0h
Queue Tail
Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be written next by software.
3:0
RV
0h
Reserved
Bit
Attr
Default
63:12
RW
000000
000000
0h
Function: 0
Description
Invalidation Request Queue Base Address
This field points to the base of size-aligned invalidation request queue.
11:3
RV
0h
Reserved
2:0
RW
0h
Queue Size
This field specifies the length of the invalidation request queue. The number of
entries in the invalidation queue is defined as 2^(X + 8), where X is the value
programmed in this field.
VTD1_INV_COMP_STATUS
Bus: 0
Device: 5
Offset: 109Ch
Bit
3.5.8.63
Bit
VTD1_INV_QUEUE_ADD
Bus: 0
Device: 5
Offset: 1090h
3.5.8.62
Function: 0
Attr
Function: 0
Default
Description
31:1
RV
0h
Reserved
RW1CS
0b
VTD1_INV_COMP_EVT_CTL
Bus: 0
Device: 5
Offset: 10A0h
Function: 0
Bit
Attr
Default
Description
31
RW
1b
Interrupt Mask
0: No masking of interrupt. When a invalidation event condition is detected,
hardware issues an interrupt message (using the Invalidation Event Data &
Invalidation Event Address register values).
1: This is the value on reset. Software may mask interrupt message generation by
setting this field. Hardware is prohibited from sending the interrupt message when
this field is set.
375
VTD1_INV_COMP_EVT_CTL
Bus: 0
Device: 5
Offset: 10A0h
3.5.8.64
Attr
Default
Description
30
RO
0b
Interrupt Pending
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as:- An Invalidation Wait Descriptor with Interrupt Flag (IF)
field set completed, setting the IWC field in the Fault Status register.
- If the IWC field in the Invalidation Event Status register was already set at the
time of setting this field, it is not treated as a new interrupt condition. The IP field
is kept set by hardware while the interrupt message is held pending. The interrupt
message could be held pending due to interrupt mask (IM field) being set, or due
to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either:
(a) Hardware issuing the interrupt message due to either change in the transient
hardware condition that caused interrupt message to be held pending or due to
software clearing the IM field.
(b) Software servicing the IWC field in the Fault Status register.
29:0
RV
0h
Reserved
Attr
Default
31:16
RV
0h
Reserved
15:0
RW
0h
Interrupt Data
Description
Function: 0
Bit
Attr
Default
63:2
RW
0h
Interrupt Address
1:0
RV
0h
Reserved
Description
VTD1_INTR_REMAP_TABLE_BASE
Bus: 0
Device: 5
Offset: 10B8h
376
Function: 0
Bit
VTD1_INV_COMP_EVT_ADDR
Bus: 0
Device: 5
Offset: 10A8h
3.5.8.66
Bit
VTD1_INV_COMP_EVT_DATA
Bus: 0
Device: 5
Offset: 10A4h
3.5.8.65
Function: 0
Bit
Attr
Default
63:12
RW
0h
Function: 0
Description
Intr Remap Base
This field points to the base of page-aligned interrupt remapping table. If the
Interrupt Remapping Table is larger than 4KB in size, it must be sizealigned.Reads of this field returns value that was last programmed to it.
VTD1_INTR_REMAP_TABLE_BASE
Bus: 0
Device: 5
Offset: 10B8h
3.5.8.67
Bit
Attr
Default
Description
11
RW-LB
0b
10:4
RV
0h
Reserved
3:0
RW
0b
Size
This field specifies the size of the interrupt remapping table. The number of
entries in the interrupt remapping table is 2^(X+1), where X is the value
programmed in this field.
VTD1_FLTREC0_GPA
Bus: 0
Device: 5
Offset: 1100h
3.5.8.68
Function: 0
Function: 0
Bit
Attr
Default
Description
63:12
ROS-V
0h
GPA
4k aligned GPA for the faulting transaction. Valid only when F field is set
11:0
RV
0h
Reserved
VTD1_FLTREC0_SRC
Bus: 0
Device: 5
Offset: 1108h
Function: 0
Bit
Attr
Default
Description
63
RW1CS
0b
Fault
Hardware sets this field to indicate a fault is logged in this fault recording register.
The F field is set by hardware after the details of the fault is recorded in the
PADDR, SID, FR and T fields.When this field is set, hardware may collapse
additional faults from the same requestor (SID).
Software writes the value read from this field to clear it.
62
ROS-V
0b
Type
Type of the first faulted DMA request
0: DMA write
1: DMA read request
This field is only valid when Fault (F) bit is set.
61:60
ROS-V
00b
59:40
RV
0h
39:32
ROS-V
00h
31:16
RV
0h
15:0
ROS-V
0000h
Address Type
This field captures the AT field from the faulted DMA request. This field is valid
only when the F field is set.
Reserved
Fault Reason
Reason for the first translation fault. See Intel VT-d spec for details.This field is
only valid when Fault bit is set.
Reserved
Source Identifier
Requester ID of the dma request that faulted. Valid only when F bit is set
377
3.5.8.69
VTD1_INVADDRREG
Bus: 0
Device: 5
Offset: 1200h
3.5.8.70
Bit
Attr
Default
Description
63:12
RW
000000
000000
0h
11:7
RV
0h
Reserved
RW
0b
ih
The field provides hint to hardware to preserve or flush the respective non-leaf
page-table entries that may be cached in hardware.
0: Software may have modified both leaf and non-leaf page-table entries
corresponding to mappings specified in the ADDR and AM fields. On a pageselective invalidation request, IIO must flush both the cached leaf and nonleaf
page-table entries corresponding to mappings specified by ADDR and AM fields.
IIO performs a domain-level invalidation on non-leaf entries and page-selectivedomain-level invalidation at the leaf level
1: Software has not modified any non-leaf page-table entries corresponding to
mappings specified in the ADDR and AM fields. On a page-selective invalidation
request, IIO preserves the cached non-leaf page-table entries corresponding to
mappings specified by ADDR and AM fields and performs only a page-selective
invalidation at the leaf level
5:0
RW
0h
am
IIO supports values of 0-9. All other values result in undefined results.
addr
To request a page-specific invalidation request to hardware, software must first
write the corresponding guest physical address to this register, and then issue a
page-specific invalidate command through the IOTLB_REG.
VTD1_IOTLBINV
Bus: 0
Device: 5
Offset: 1208h
378
Function: 0
Function: 0
Bit
Attr
Default
Description
63
RW
0b
62
RV
0h
Reserved
61:60
RW
00b
59
RV
0h
VTD1_IOTLBINV
Bus: 0
Device: 5
Offset: 1208h
Function: 0
Bit
Attr
Default
Description
58:57
RO
00b
56:50
RV
0h
Reserved
49
RW
0b
dr
Processor uses this to drain or not drain reads on an invalidation request.
48
RW
0b
dw
Processor uses this to drain or not drain writes on an invalidation request.
47:32
RW
0000h
31:0
RV
0h
did
Domain to be invalidated and is programmed by software for both page and
domain selective invalidation requests. Intel Xeon Processor E5 Product Family
ignores the bits 47:40 since it supports only an 8 bit Domain ID.
Reserved
379
380
4.1
4.1.1
4.1.1.1
Bit
Attr
Default
15:0
RO
8086h
Description
Vendor Identification Number
The value is assigned by PCI-SIG to Intel.
Attr
15:0
RO
Default
Description
Device Identification Number
Device ID values vary from function to function. Bits 15:8 are equal to 0x3C for
the processor. The following list is a breakdown of the function groups.
0x3C00 - 0x3C1 PCI Express and DMI ports
0x3C20 - 0x3C3F: IO Features (QDDMA, APIC, Intel VT, RAS, Intel TXT)
0x3C40 - 0x3C5F: Performance Monitors
0x3C60 - 0x3C7F: DFX
0x3C80 - 0x3C9F: Intel QuickPath Interconnect
0x3CA0 - 0x3CBF: Home Agent/Memory Controller
0x3CC0 - 0x3CDF: Power Management
0x3CE0 - 0x3CFF: Cbo/Ring
1_8_0_CFG: Attr: RO Default: 3C80h
1_9_0_CFG: Attr: RO Default: 3C90h
381
4.1.1.2
4.1.1.3
Bit
Attr
Default
Description
15:11
RV
0h
Reserved
10
RO
0b
INTx Disable
N/A for these devices
RO
0b
RO
0b
SERR Enable
This bit has no impact on error reporting from these devices
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
IO Space Enable
Hardwired to 0 since these devices dont decode any IO BARs
382
Bit
Attr
Default
Description
15
RO
0b
14
RO
0b
13
RO
0b
12
RO
0b
11
RO
0b
10:9
RO
0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
RO
0b
PCISTS
Offset: 6
4.1.1.4
Bit
Attr
Default
Description
RO
0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
RO
0b
Reserved
RO
0b
66MHz capable
Not applicable to PCI Express. Hardwired to 0.
RO
0b
Capabilities List
This bit indicates the presence of a capabilities list structure
RO
0b
INTx Status
Hardwired to 0
2:0
RV
0h
Reserved
4.1.1.5
Bit
Attr
Default
Description
7:0
RO
00h
Revision_ID
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register
in any processor function.
Implementation Note:
Read and write requests from the host to any RID register in any processor
function are re-directed to the IIO cluster. Accesses to the CCR field are also
redirected due to DWORD alignment. It is possible that JTAG accesses are direct,
so will not always be redirected.
4.1.1.6
Bit
Attr
Default
Description
23:16
RO
08h
Base Class
Generic Device
15:8
RO
80h
Sub-Class
Generic Device
7:0
RO
00h
Attr
Default
7:0
RW
0h
Description
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for Intel
Xeon Processor E5 Family is always 64B.
383
4.1.1.7
4.1.1.8
Bit
Attr
Default
7:0
RO
0h
Description
Primary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
4.1.1.9
Bit
Attr
Default
RO
1b
6:0
RO
00h
Description
Multi-function Device
This bit defaults to 1b since all these devices are multi-function
Configuration Layout
This field identifies the format of the configuration header layout. It is Type 0 for
all these devices. The default is 00h, indicating a endpoint device.
4.1.1.10
Bit
Attr
Default
7:0
RO
0h
Description
BIST Tests
Not supported. Hardwired to 00h
4.1.1.11
Bit
Attr
Default
15:0
RW-O
8086h
Description
Subsystem Vendor Identification Number.
The default value specifies Intel but can be set to any value once after reset.
384
Bit
Attr
Default
15:0
RW-O
00h
Description
Subsystem Device Identification Number
Assigned by the subsystem vendor to uniquely identify the subsystem
4.1.1.12
4.1.1.13
Bit
Attr
Default
7:0
RO
00h
Description
Capability Pointer
Points to the first capability structure for the device which is the PCIe capability.
4.1.1.14
Bit
Attr
Default
7:0
RO
00h
Description
Interrupt Line
N/A for these devices
4.1.1.15
Bit
Attr
Default
7:0
RO
00h
Description
Interrupt Pin
N/A since these devices do not generate any interrupt on their own
4.1.1.16
Bit
Attr
Default
7:0
RO
00h
Description
Minimum Grant Value
This register does not apply to PCI Express. It is hard-coded to 00h.
4.2
Bit
Attr
Default
7:0
RO
00h
Description
Maximum Latency Value
This register does not apply to PCI Express. It is hard-coded to 00h.
385
4.2.1
4.2.2
Table 4-1.
DID
VID
PCISTS
PCICMD
CCR
BIST
HDR
RID
PLAT
SDID
CLSR
SVID
CAPPTR
MAXLAT
MINGNT
INTPIN
INTL
0h
80h
4h
84h
8h
88h
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
34h
B4h
38h
B8h
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
386
QPIMISCSTAT
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Table 4-2.
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
SDID
MAXLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
SVID
MINGNT
INTPIN
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
387
4.2.3
4.2.3.1
Device: 8
Function: 0
Offset: D4
Bit
Attr
Default
Description
31:5
RV
0h
Reserved
RO-V
0b
Slow Mode
Reflects the current slow mode status being driven to the PLL.
This will be set out of reset to bring Intel QPI in slow mode. And is only expected
to be set when qpi_rate is set to 6.4 GT/s.
RV
0h
Reserved
2:0
RO-V
011b
4.3
CBo Registers
4.3.1
Table 4-3.
DID
VID
PCISTS
PCICMD
CCR
BIST
HDR
RID
PLAT
SDID
CLSR
SVID
CAPPTR
MAXLAT
MINGNT
INTPIN
INTL
0h
80h
4h
84h
8h
88h
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
34h
B4h
38h
B8h
3Ch
40h
388
BCh
RTID_Config_Pool01_Base_Shadow
C0h
Table 4-3.
Table 4-4.
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
System Address Decoder (CBo): Device 12, Function 6, Offset 00h-FCh (Sheet
1 of 2)
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
SDID
MAXLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
SVID
MINGNT
INTPIN
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
389
Table 4-4.
System Address Decoder (CBo): Device 12, Function 6, Offset 00h-FCh (Sheet
2 of 2)
Table 4-5.
VID
PCISTS
PCICMD
CCR
HDR
RID
PLAT
SDID
CLSR
SVID
CAPPTR
MAXLAT
390
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Caching agent broadcast registers(CBo): Device 12, Function 7, Offset 00hFCh (Sheet 1 of 2)
DID
BIST
60h
MINGNT
INTPIN
INTL
0h
80h
4h
84h
8h
88h
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
34h
B4h
38h
B8h
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
Table 4-5.
Caching agent broadcast registers(CBo): Device 12, Function 7, Offset 00hFCh (Sheet 2 of 2)
Table 4-6.
74h
F4h
78h
F8h
7Ch
FCh
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
SDID
MAXLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
SVID
MINGNT
INTPIN
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
391
Table 4-7.
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
SDID
MAXLAT
4.4
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
SVID
MINGNT
INTPIN
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
392
4.4.1
4.4.2
4.4.3
Table 4-8.
Memory Controller MemHot and SMBus Registers: Bus N, Device 15, Function
0, Offset 100h-1FCh
MH_MAINCNTL
100h
SMB_STAT_0
180h
104h
SMBCMD_0
184h
108h
SMBCntl_0
188h
MH_SENSE_500NS_CFG
10Ch
SMB_TSOD_POLL_RATE_CNTR_0
18Ch
MH_DTYCYC_MIN_ASRT_CNTR_0
110h
SMB_STAT_1
190h
MH_DTYCYC_MIN_ASRT_CNTR_1
114h
SMBCMD_1
194h
MH_IO_500NS_CNTR
118h
SMBCntl_1
198h
MH_CHN_ASTN
11Ch
SMB_TSOD_POLL_RATE_CNTR_1
19Ch
MH_TEMP_STAT
120h
SMB_PERIOD_CFG
1A0h
MH_EXT_STAT
124h
SMB_PERIOD_CNTR
1A4h
128h
SMB_TSOD_POLL_RATE
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
148h
1C8h
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
393
Table 4-8.
394
Memory Controller MemHot and SMBus Registers: Bus N, Device 15, Function
0, Offset 100h-1FCh
174h
1F4h
178h
1F8h
17Ch
1FCh
Table 4-9.
Memory Controller RAS Registers: Bus N, Device 15, Function 1, Offset 00hFCh
DID
VID
PCISTS
PCICMD
CCR
BIST
0h
RID
HDR
PLAT
CLSR
SPAREADDRESSLO
4h
84h
8h
88h
Ch
8Ch
10h
SPARECTL
SVID
SSRSTATUS
94h
18h
SCRUBADDRESSLO
98h
1Ch
SCRUBADDRESSHI
9Ch
20h
SCRUBCTL
A0h
28h
SPAREINTERVAL
A8h
2Ch
RASENABLES
ACh
A4h
30h
CAPPTR
MAXLAT
MINGNT
INTPIN
PXPCAP
INTL
90h
14h
24h
SDID
80h
B0h
34h
SMISPARECTL
B4h
38h
LEAKY_BUCKET_CFG
B8h
3Ch
BCh
40h
LEAKY_BUCKET_CNTR_LO
44h
LEAKY_BUCKET_CNTR_HI
48h
C0h
C4h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
395
Table 4-10. Memory Controller DIMM Timing and Interleave Registers: Bus N, Device 15,
Function 2 - 5 Offset 00h-FCh
DID
VID
PCISTS
PCICMD
CCR
BIST
0h
RID
HDR
PLAT
SDID
CLSR
SVID
CAPPTR
MAXLAT
MINGNT
INTPIN
PXPCAP
INTL
DIMMMTR_0
80h
4h
DIMMMTR_1
84h
8h
DIMMMTR_2
88h
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
34h
B4h
38h
B8h
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Table 4-11. Memory Controller Channel Rank Registers: Bus N, Device 15, Function 2 - 5
Offset 100h-1FCh (Sheet 1 of 2)
PXPENHCAP
396
100h
180h
104h
184h
108h
188h
10Ch
18Ch
110h
190h
114h
194h
118h
198h
Table 4-11. Memory Controller Channel Rank Registers: Bus N, Device 15, Function 2 - 5
Offset 100h-1FCh (Sheet 2 of 2)
11Ch
19Ch
120h
1A0h
124h
1A4h
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
140h
1C0h
144h
1C4h
148h
1C8h
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
The following register maps are for memory controller control logic registers:
Table 4-12. Memory Controller Channel
Function 0, Offset 00h-FCh
Memory Controller Channel
Function 1, Offset 00h-FCh
Memory Controller Channel
Function 4, Offset 00h-FCh
Memory Controller Channel
Function 5, Offset 00h-FCh
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
A0h
397
SDID
SVID
2Ch
34h
MINGNT
INTPIN
PXPCAP
INTL
ACh
B0h
B4h
PmonCntr_2
38h
MAXLAT
A8h
PmonCntr_1
30h
CAPPTR
A4h
PmonCntr_0
28h
3Ch
B8h
BCh
PmonCntr_3
40h
44h
C0h
C4h
PmonCntr_4
48h
4Ch
C8h
CCh
PmonDbgCntResetVal
50h
54h
D0h
D4h
PmonCntr_Fixed
58h
D8h
5Ch
PmonCntrCfg_0
DCh
60h
PmonCntrCfg_1
E0h
64h
PmonCntrCfg_2
E4h
68h
PmonCntrCfg_3
E8h
6Ch
PmonCntrCfg_4
ECh
70h
F0h
74h
PmonUnitCtrl
F4h
78h
PmonUnitStatus
F8h
7Ch
FCh
100h
180h
104h
184h
CHN_TEMP_CFG
108h
188h
CHN_TEMP_STAT
10Ch
18Ch
DIMM_TEMP_OEM_0
110h
DIMM_TEMP_OEM_1
114h
DIMM_TEMP_OEM_2
398
THRT_PWR_DIMM_1
THRT_PWR_DIMM_0
190h
THRT_PWR_DIMM_2
194h
118h
198h
11Ch
19Ch
DIMM_TEMP_TH_0
120h
1A0h
DIMM_TEMP_TH_1
124h
1A4h
DIMM_TEMP_TH_2
128h
1A8h
12Ch
1ACh
DIMM_TEMP_THRT_LMT_0
130h
1B0h
DIMM_TEMP_THRT_LMT_1
134h
1B4h
DIMM_TEMP_THRT_LMT_2
138h
1B8h
13Ch
1BCh
DIMM_TEMP_EV_OFST_0
140h
1C0h
DIMM_TEMP_EV_OFST_1
144h
1C4h
DIMM_TEMP_EV_OFST_2
148h
1C8h
14Ch
1CCh
DIMMTEMPSTAT_0
150h
1D0h
DIMMTEMPSTAT_1
154h
1D4h
DIMMTEMPSTAT_2
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
399
280h
TCRAP
204h
284h
TCRWP
208h
288h
TCOTHP
20Ch
28Ch
TCRFP
210h
290h
TCRFTP
214h
294h
TCSRFTP
218h
298h
TCMR2SHADOW
21Ch
29Ch
TCZQCAL
220h
2A0h
TCSTAGGER_REF
224h
2A4h
228h
2A8h
22Ch
2ACh
230h
2B0h
TCMR0SHADOW
400
200h
RPQAGE
234h
2B4h
IDLETIME
238h
2B8h
RDIMMTIMINGCNTL
23Ch
2BCh
RDIMMTIMINGCNTL2
240h
2C0h
TCMRS
244h
2C4h
248h
2C8h
24Ch
2CCh
250h
2D0h
254h
2D4h
258h
2D8h
25Ch
2DCh
260h
2E0h
264h
2E4h
268h
2E8h
26Ch
2ECh
270h
2F0h
274h
2F4h
278h
2F8h
27Ch
2FCh
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
SDID
MAXLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
SVID
MINGNT
INTPIN
PXPCAP
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
401
CORRERRCNT_0
100h
180h
104h
184h
CORRERRCNT_1
108h
188h
CORRERRCNT_2
10Ch
18Ch
CORRERRCNT_3
110h
190h
114h
194h
118h
198h
CORRERRTHRSHLD_0
11Ch
19Ch
CORRERRTHRSHLD_1
120h
1A0h
CORRERRTHRSHLD_2
124h
1A4h
CORRERRTHRSHLD_3
CORRERRORSTATUS
LEAKY_BKT_2ND_CNTR_REG
128h
1A8h
12Ch
1ACh
130h
1B0h
134h
1B4h
138h
1B8h
13Ch
1BCh
DEVTAG_C
NTL_3
DEVTAG_C
NTL_2
DEVTAG_C
NTL_1
DEVTAG_C
NTL_0
140h
1C0h
DEVTAG_C
NTL_7
DEVTAG_C
NTL_6
DEVTAG_C
NTL_5
DEVTAG_C
NTL_4
144h
1C4h
402
148h
1C8h
14Ch
1CCh
150h
1D0h
154h
1D4h
158h
1D8h
15Ch
1DCh
160h
1E0h
164h
1E4h
168h
1E8h
16Ch
1ECh
170h
1F0h
174h
1F4h
178h
1F8h
17Ch
1FCh
x4modesel
4.4.4
280h
204h
284h
208h
288h
20Ch
28Ch
210h
290h
214h
294h
218h
298h
21Ch
29Ch
220h
2A0h
224h
2A4h
228h
2A8h
22Ch
2ACh
230h
2B0h
234h
2B4h
238h
2B8h
23Ch
2BCh
240h
2C0h
244h
2C4h
248h
2C8h
24Ch
2CCh
250h
2D0h
254h
2D4h
258h
2D8h
25Ch
2DCh
260h
2E0h
264h
2E4h
268h
2E8h
26Ch
2ECh
270h
2F0h
274h
2F4h
278h
2F8h
27Ch
2FCh
403
The following Memory Controller Main Registers are part of the address decode
functions:
4.4.4.1
PXPCAP
Bus: 1
4.4.4.2
Device: 15
Offset: 40
Bit
Attr
Default
31:30
RV
0h
29:25
RO
00h
24
RO
0b
Slot Implemented
N/A for integrated endpoints
23:20
RO
9h
Device/Port Type
Device type is Root Complex Integrated Endpoint
19:16
RO
1h
Capability Version
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since they
require additional capability registers to be reserved. The only purpose for this
capability structure is to make enhanced configuration space available. Minimizing
the size of this structure is accomplished by reporting version 1.0 compliancy and
reporting that this is an integrated root port device. As such, only three Dwords of
configuration space are required for this structure.
15:8
RO
00h
7:0
RO
10h
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
Description
Reserved
Interrupt Message Number
N/A for this device
MCMTR
Bus: 1
Bit
404
Function: 0
Device: 15
Function: 0
Offset: 7C
Attr
Default
Description
31:10
RV
0h
Reserved
RW-LB
0b
NORMAL
0: IOSAV mode
1: Normal Mode
7:4
RV
0h
Reserved
RW-LB
0b
DIR_EN
Note: This bit will only work if the SKU is enabled for this feature
It is important to know that changing this bit will require BIOS to re-initialize the
memory.
RW-LB
0h
ECC_EN
ECC enable.
Note: This bit will only work if the SKU is enabled for this feature
RW-LB
0h
LS_EN
Use lock-step channel mode if set; otherwise, independent channel mode.
Note: This bit will only work if the SKU is enabled for this feature
RW-LB
0h
CLOSE_PG
Use close page address mapping if set; otherwise, open page.
4.4.4.3
4.4.4.4
Function: 0
Function: 0
Bit
Attr
Default
Description
31:12
RW-LB
00000h
11:10
RW-LB
0h
TAD_SKT_WAY
socket interleave wayness
00 = 1 way,
01 = 2 way,
10 = 4 way,
11 = 8 way.
9:8
RW-LB
0h
TAD_CH_WAY
channel interleave wayness
00 - interleave across 1 channel or mirror pair
01 - interleave across 2 channels or mirror pairs
10 - interleave across 3 channels
11 - interleave across 4 channels
Note: This parameter effectively tells iMC how much to divide the system address
by when adjusting for the channel interleave. Since both channels in a pair store
every line of data, we want to divide by 1 when interleaving across one pair and 2
when interleaving across two pairs. For HA, it tells how may channels to distribute
the read requests across. When we interleaving across 1 pair, we want to
distribute the reads to two channels, when interleaving across 2 pairs, we
distribute the reads across 4 pairs. Writes always go to both channels in the pair
when the read target is either channel.
7:6
RW-LB
0h
TAD_CH_TGT3
target channel for channel interleave 3 (used for 4-way TAD interleaving).
This register is used in the iMC only for reverse address translation for logging
spare/patrol errors, converting a rank address back to a system address.
5:4
RW-LB
0h
TAD_CH_TGT2
target channel for channel interleave 2 (used for 3/4-way TAD interleaving).
3:2
RW-LB
0h
TAD_CH_TGT1
target channel for channel interleave 1 (used for 2/3/4-way TAD interleaving).
1:0
RW-LB
0h
TAD_CH_TGT0
target channel for channel interleave 0 (used for 1/2/3/4-way TAD interleaving).
TAD_LIMIT
highest address of the range in system address space, 64MB granularity, i.e.
TADRANGLIMIT[45:26].
405
MCMTR2
Bus: 1
4.4.4.5
Device: 15
Function: 0
Offset: B0
Bit
Attr
Default
Description
31:4
RV
0h
Reserved
3:0
RW-L
0h
MONROE_CHN_FORCE_SR
Intel Dynamic Power Technology software channel force SRcontrol. When set,
the corresponding channel is ignoring the ForceSRExit. A new transaction arrive at
this channel will still cause the SR exit. This field is locked for parts that have Intel
Dynamic Power Technology disabled
406
Function: 0
Offset: B4
Bit
Attr
Default
Description
31:13
RV
0h
Reserved
12:9
RWS-L
0h
cs_oe_en
Per channel CS output enable override
RWS-L
1b
MC is in SR
This bit indicates if it is safe to keep the MC in SR during MC-reset. If it is clear
when reset occurs, it means that the reset is without warning and the DDR-reset
should be asserted. If set when reset occurs, it indicates that DDR is already in SR
and it can keep it this way. This bit can also indicate BIOS if reset without warning
has occurred, and if it has, cold-reset flow should be selected
RW-L
0b
MRC_DONE
This bit indicates the PCU that the BIOS is done, MC is in normal mode, ready to
serve, and PCU may begin power-control operations
BIOS should set this bit when BIOS is done, but it doesnt need to wait until
training results are saved in BIOS flash
RW-L
1b
RW-L
1b
RW-L
0b
Refresh Enable
Refresh enable
If cold reset, this bit should be set by BIOS after
1) Initializing the refresh timing parameters
2) Running DDR through reset and init sequence
If warm reset or S3 exit, this bit should be set immediately after SR exit
RW-L
0b
RW-L
1b
DDR_RESET
DDR reset for all DIMM's from all channels within this socket. No IMC/DDRIO logic
is reset by asserting this register.
It is important to note that this bit is negative logic! i.e. writing 0 to induce a reset
and write 1 for not reset.
4.4.4.6
4.4.5
Device: 15
Function: 0
Offset: C0
Bit
Attr
Default
Description
31
RW
0b
rcomp_in_progress
rcomp in progress status bit
30:22
RV
0h
Reserved
21
RW
0b
ignore_mdll_locked_bit
Ignore DDRIO MDLL lock status during rcomp when set
20
RW
0b
no_mdll_fsm_override
Do not force DDRIO MDLL on during rcomp when set
19:17
RV
0h
Reserved
16
RW-LV
0b
15:0
RW
044Ch
COUNT
DCLK cycle count that MC needs to wait from the point it has triggered RCOMP
evaluation until it can trigger the load to registers
4.4.5.1
MH_MAINCNTL
Bus: 1
Device: 15
Function: 0
Offset: 104
Bit
Attr
Default
Description
31:19
RV
0h
Reserved
18
RW
0h
MHOT_EXT_SMI_EN
Generate SMI event when either MEMHOT[1:0]# is externally asserted.
17
RW
0h
MHOT_SMI_EN
Generate SMI during internal MEMHOT# event assertion
16
RW
0b
15
RW
1b
407
4.4.5.2
MH_SENSE_500NS_CFG
Bus: 1
Device: 15
Bit
408
Attr
Default
Function: 0
Offset: 10C
Description
31:26
RV
0h
25:16
RW
0C8h
15:13
RW
2h
MH_IN_SENSE_ASSERT
MEMHOT Input Sense Assertion Time in number of CNTR_500_NANOSEC. BIOS
calculates the number of CNFG_500_NANOSEC for 1 usec/2 usec input_sense
duration
Here is MH_IN_SENSE_ASSERT ranges:
0 or 1 Reserved
2 - 7 1 usec - 3.5 usec sense assertion time in 500 nsec increment
Reserved
12:10
RV
0h
9:0
RWS
190h
Reserved
MH_SENSE_PERIOD
MEMHOT Input Sense Period in number of CNTR_500_NANOSEC. BIOS calculates
the number of CNTR_500_NANOSEC for 50 usec/100 usec/200 usec/400 usec.
CNFG_500_NANOSEC
500 ns equivalent in DCLK. BIOS calculates the number of DCLK to be equivalent
to 500 nanoseconds. This value is loaded into CNTR_500_NANOSEC when it is
decremented to zero.
The following are the recommended CNFG_500_NANOSEC values based from
each DCLK frequency:
DCLK=400 MHz, CNFG_500_NANOSEC=0C8h
DCLK=533 MHz, CNFG_500_NANOSEC=10Ah
DCLK=667 MHz, CNFG_500_NANOSEC=14Dh
DCLK=800 MHz, CNFG_500_NANOSEC=190h
DCLK=933 MHz, CNFG_500_NANOSEC=1D2h
4.4.5.3
MH_DTYCYC_MIN_ASRT_CNTR_[0:1]
Bus: 1
Device: 15
Function: 0
4.4.5.4
Bit
Attr
Default
31:20
RO-V
0h
19:0
RW-LV
00000h
MH_MIN_ASRTN_CNTR
MEM_HOT[1:0]# Minimum Assertion Time Current Count in number of
CNTR_500_NANOSEC (decrement by 1 every CNTR_500_NANOSEC). When the
counter is zero, the counter is remain at zero and it is only loaded with
MH_MIN_ASRTN only when MH_DUTY_CYC_PRD_CNTR is reloaded.
MH_DUTY_CYC_PRD_CNTR
MEM_HOT[1:0]# DUTY Cycle Period Current Count in number of
CNTR_500_NANOSEC (decrement by 1 every CNTR_500_NANOSEC). When the
counter is zero, the next cycle is loaded with MH_DUTY_CYC_PRD. PMSI pause (at
quiencense) and resume (at wipe)
MH_IO_500NS_CNTR
Bus: 1
Device: 15
Function: 0
Offset: 118
Bit
Attr
Default
Description
31:22
RW-LV
000h
MH1_IO_CNTR
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When
MH0_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next
CNTR_500_NANOSEC. When count is greater than MH_IN_SENSE_ASSERT, the
MEM_HOT[1]# output driver may be turn on if the corresponding
MEM_HOT#event is asserted. The receiver is turned off during this time. When
count is equal or less than MH_IN_SENSE_ASSERT, MEM_HOT[1:0]# output is
disabled and receiver is turned on. Hardware will decrement this counter by 1
every time CNTR_500_NANOSEC is decremented to zero. When the counter is
zero, the next CNFG_500_NANOSEC count is loaded with MH_IN_SENSE_ASSERT.
This counter is subject to PMSI pause (at quiencense) and resume (at wipe).
21:12
RW-LV
000h
MH0_IO_CNTR
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When
MH_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next
CNTR_500_NANOSEC. When count is greater than MH_IN_SENSE_ASSERT, the
MEM_HOT[1:0]# output driver may be turn on if the corresponding
MEM_HOT#event is asserted. The receiver is turned off during this time. When
count is equal or less than MH_IN_SENSE_ASSERT, MEM_HOT[1:0]# output is
disabled and receiver is turned on. BIOS calculates the number of
CNTR_500_NANOSEC (hardware will decrement this register by 1 every
CNTR_500_NANOSEC). When the counter is zero, the next CNTR_500_NANOSEC
count is loaded with MH_IN_SENSE_ASSERT. This counter is subject to PMSI
pause (at quiencense) and resume (at wipe).
11:10
RV
0h
9:0
RW-LV
000h
Reserved
CNTR_500_NANOSEC
500 ns base counters used for the MEM_HOT counters and the SMBus counters.
BIOS calculates the number of DCLK to be equivalent to 500 nanoseconds.
CNTR_500_NANOSEC (hardware will decrement this register by 1 every
CNTR_500_NANOSEC). When the counter is zero, the next CNTR_500_NANOSEC
count is loaded with CNFG_500_NANOSEC. This counter is subject to PMSI pause
(at quiencense) and resume (at wipe).
409
4.4.5.5
MH_CHN_ASTN
Bus: 1
Bit
4.4.5.6
Attr
Device: 15
Default
Offset: 11C
Description
31:24
RV
0h
Reserved
23:20
RO
Bh
MH1_2ND_CHN_ASTN
MemHot[1]# 2nd Channel Association bit 23: is valid bit. Note: Valid bit means
the association is valid and it does not implies the channel is populated.
bit 22-20: 2nd channel ID within this MEMHOT domain.
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.
19:16
RO
Ah
MH1_1ST_CHN_ASTN
MemHot[1]# 1st Channel Association bit 19: is valid bit. Note: Valid bit means the
association is valid and it does not implies the channel is populated.
bit 18-16: 1st channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.
15:8
RV
0h
Reserved
7:4
RO
9h
MH0_2ND_CHN_ASTN
MemHot[0]# 2nd Channel Association bit 7: is valid bit. Note: Valid bit means the
association is valid and it does not implies the channel is populated.
Bit 6-4: 2nd channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.
3:0
RO
8h
MH0_1ST_CHN_ASTN
MemHot[0]# 1st Channel Association bit 3: is valid bit. Note: Valid bit means the
association is valid and it does not implies the channel is populated or exist.
Bit 2-0: 1st channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.
MH_TEMP_STAT
Bus: 1
410
Function: 0
Device: 15
Function: 0
Offset: 120
Bit
Attr
Default
Description
31
RW-V
0h
MH1_DIMM_VAL
Valid if set. microcode search the hottest DIMM temperature and write the hottest
temperature and the corresponding Hottest DIMM CID/ID and set the valid bit.
MEMHOT hardware logic process the corresponding MEMHOT data when there is a
MEMHOT event. Upon processing, the valid bit is reset. The microcode can write
over existing valid temperature since a valid temperature may not occur during a
MEMHOT event. If the microcode set the valid bit occur at the same cycle that the
MEMHOT logic processing and try to clear, the microcode set will dominate since it
is a new temperature is updated while processing logic tries to clear an existing
temperature.
30:28
RW
0h
MH1_DIMM_CID
Hottest DIMM Channel ID for MEM_HOT[1]#. The microcode search the hottest
DIMM temperature and write the hottest temperature and the corresponding
Hottest DIMM CID/ID.
27:24
RW
0h
MH1_DIMM_ID
Hottest DIMM ID for MEM_HOT[1]#. The microcode search the hottest DIMM
temperature and write the hottest temperature and the corresponding Hottest
DIMM CID/ID.
MH_TEMP_STAT
Bus: 1
4.4.5.7
Device: 15
Function: 0
Offset: 120
Bit
Attr
Default
Description
23:16
RW
00h
MH1_TEMP
Note: Hottest DIMM Sensor Reading for MEM_HOT[1]# - This reading
represents the temperature of the hottest DIMM. The microcode search
the hottest DIMM temperature and write the hottest temperature and the
corresponding Hottest DIMM CID/ID. iMC hardware load this value into
the MEM_HOT duty cycle generator counter since the microcode may
update this field at different rate/time. This field is ranged from 0 to 127,
i.e. the most significant bit is always zero.
15
RW-V
0h
MH0_DIMM_VAL
Valid if set. The microcode search the hottest DIMM temperature and write the
hottest temperature and the corresponding Hottest DIMM CID/ID and set the valid
bit. MEMHOT hardware logic process the corresponding MEMHOT data when there
is a MEMHOT event. Upon processing, the valid bit is reset. The microcode can
write over existing valid temperature since a valid temperature may not occur
during a MEMHOT event. If the microcode set the valid bit occur at the same cycle
that the MEMHOT logic processing and try to clear, the microcode set will
dominate since it is a new temperature is updated while processing logic tries to
clear an existing temperature.
14:12
RW
0h
MH0_DIMM_CID
Hottest DIMM Channel ID for MEM_HOT[0]#. The microcode search the hottest
DIMM temperature and write the hottest temperature and the corresponding
Hottest DIMM CID/ID.
11:8
RW
0h
MH0_DIMM_ID
Hottest DIMM ID for MEM_HOT[0]#. The microcode search the hottest DIMM
temperature and write the hottest temperature and the corresponding Hottest
DIMM CID/ID.
7:0
RW
00h
MH0_TEMP
Hottest DIMM Sensor Reading for MEM_HOT[0]# - This reading represents the
temperature of the hottest DIMM. The microcode search the hottest DIMM
temperature and write the hottest temperature and the corresponding Hottest
DIMM CID/ID.
Note: iMC hardware load this value into the MEM_HOT duty cycle generator
counter since the microcode may update this field at different rate/time.
This field is ranged from 0 to 127, i.e. the most significant bit is always
zero.
MH_EXT_STAT
Capture externally asserted MEM_HOT[1:0]# assertion detection.
MH_EXT_STAT
Bus: 1
Device: 15
Function: 0
Offset: 124
Bit
Attr
Default
Description
31:2
RV
0h
Reserved
RW1C
0b
MH_EXT_STAT_1
MEM_HOT[1]# assertion status at this sense period.
Set if MEM_HOT[1]# is asserted externally for this sense period, this running
status bit will automatically updated with the next sensed value in the next
MEM_HOT input sense phase.
RW1C
0b
MH_EXT_STAT_0
MEM_HOT[0]# assertion status at this sense period.
Set if MEM_HOT[0]# is asserted externally for this sense period, this running
status bit will automatically updated with the next sensed value in the next
MEM_HOT input sense phase.
411
4.4.6
4.4.6.1
412
Function: 0
Offset: 180
Bit
Attr
Default
Description
31
RO-V
0h
SMB_RDO
Read Data Valid
This bit is set by iMC when the Data field of this register receives read data from
the SPD/TSOD after completion of an SMBus read command. It is cleared by iMC
when a subsequent SMBus read command is issued.
30
RO-V
0h
SMB_WOD
Write Operation Done
This bit is set by iMC when a SMBus Write command has been completed on the
SMBus. It is cleared by iMC when a subsequent SMBus Write command is issued.
29
RW-V
0h
SMB_SBE
SMBus Error
This bit is set by iMC if an SMBus transaction (including the TSOD polling or SMBus
access) that does not complete successfully (non-Ack has been received from
slave at expected Ack slot of the transfer). If a slave device is asserting clock
stretching, IMC does not have logic to detect this condition to set the SBE bit
directly; however, the SMBus master will detect the error at the corresponding
transactions expected ACK slot.
Note: Once SMBUS_SBE bit is set, iMC stops issuing hardware initiated TSOD
polling SMBUS transactions until the SMB_SBE is cleared. iMC will not
increment the SMB_STAT_x.TSOD_SA until the SMB_SBE is cleared.
Manual SMBus command interface is not affected, i.e. new command
issue will clear the SMB_SBE
28
ROS-V
0h
SMB_BUSY
SMBus Busy state. This bit is set by iMC while an SMBus/I2C command (including
TSOD command issued from IMC hardware) is executing. Any transaction that is
completed normally or gracefully will clear this bit automatically. By setting the
SMB_SOFT_RST will also clear this bit.
This register bit is sticky across reset so any surprise reset during pending SMBus
operation will sustain the bit assertion across surprised warm-reset. BIOS reset
handler can read this bit before issuing any SMBus transaction to determine
whether a slave device may need special care to force the slave to idle state (e.g.
via clock override toggling (SMB_CKOVRD) and/or via induced time-out by
asserting SMB_CKOVRD for 25-35ms).
Reserved
27
RV
0h
26:24
RO-V
111b
23:16
RV
0h
SMB_STAT_[0:1]
Bus: 1
Device: 15
4.4.6.2
Function: 0
Offset: 180
Bit
Attr
Default
Description
15:0
RO-V
0000h
SMB_RDATA
Read DataHolds data read from SMBus Read commands.
Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a word
read, reading of I2C using word read should return SMB_RDATA[15:8]=I2C_MSB
and SMB_RDATA[7:0]=I2C_LSB. If reading of I2C using byte read, the
SMB_RDATA[15:8]=dont care; SMB_RDATA[7:0]=read_byte.
If we have a SMB slave connected on the bus, reading of the SMBus slave using
word read should return SMB_RDATA[15:8]=SMB_LSB and
SMB_RDATA[7:0]=SMB_MSB.
If the software is not sure whether the target is I2C or SMBus slave, please use
byte access.
Device: 15
Function: 0
Offset: 184
Bit
Attr
Default
Description
31
RW-V
0b
SMB_CMD_TRIGGER
CMD trigger: After setting this bit to 1, the SMBus master will issue the SMBus
command using the other fields written in SMBCMD_[0:1] and SMBCntl_[0:1].
Note: the -V in the attribute implies the hardware will reset this bit when the
SMBus command is being started.
30
RWS
0b
SMB_PNTR_SEL
Pointer Selection: SMBus/I2C present pointer based access enable when set;
otherwise, use random access protocol. Hardware based TSOD polling will also use
this bit to enable the pointer word read.
Important Note: The processor hardware based TSOD polling can be configured
with pointer based access. If software manually issue SMBus transaction to other
address, i.e. changing the pointer in the slave device, it is softwares responsibility
to restore the pointer in each TSOD before returning to hardware based TSOD
polling while keeping the SMB_PNTR_SEL=1.
29
RWS
0b
SMB_WORD_ACCESS
Word access: SMBus/I2C word (2B) access when set; otherwise, it is a byte
access.
28
RWS
0b
SMB_WRT_PNTR
Bit[28:27]=00: SMBus Read
Bit[28:27]=01: SMBus Write
Bit[28:27]=10: illegal combination
Bit[28:27]=11: Write to pointer register SMBus/I2C pointer update (byte). bit 30,
and 29 are ignored. Note: SMBCntl_[0:1][26] will NOT disable WrtPntr update
command.
27
RWS
0b
SMB_WRT_CMD
When 0, it is a read command
When 1, it is a write command
26:24
RWS
000b
23:16
RWS
00h
SMB_SA
Slave Address: This field identifies the DIMM SPD/TSOD to be accessed.
SMB_BA
Bus Txn Address: This field identifies the bus transaction address to be accessed.
Note: in WORD access, 23:16 specifies 2B access address. In Byte access, 23:16
specified 1B access address.
413
SMBCMD_[0:1]
Bus: 1
4.4.6.3
Function: 0
Offset: 184
Bit
Attr
Default
Description
15:0
RWS
0000h
SMB_WDATA
Write Data: Holds data to be written by SPDW commands.
Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a word
write, writing of I2C using word write should use SMB_WDATA[15:8]=I2C_MSB
and SMB_WDATA[7:0]=I2C_LSB. If writing of I2C using byte write, the
SMB_WDATA[15:8]=dont care; SMB_WDATA[7:0]=write_byte.
If we have a SMB slave connected on the bus, writing of the SMBus slave using
word write should use SMB_WDATA[15:8]=SMB_LSB and
SMB_WDATA[7:0]=SMB_MSB.
It is software responsibility to figure out the byte order of the slave access.
SMBCntl_[0:1]
Bus: 1
414
Device: 15
Device: 15
Function: 0
Offset: 188
Bit
Attr
Default
Description
31:28
RWS
1010b
SMB_DTI
Device Type Identifier: This field specifies the device type identifier. Only devices
with this device-type will respond to commands.
0011 specifies TSOD.
1010 specifies EEPROMs.
0110 specifies a write-protect operation for an EEPROM.
Other identifiers can be specified to target non-EEPROM devices on the SMBus.
Note: IMC based hardware TSOD polling uses hardcoded DTI. Changing this field
has no effect on the hardware based TSOD polling.
27
RWS-V
1h
SMB_CKOVRD
Clock Override
0 = Clock signal is driven low, overriding writing a 1 to CMD.
1 = Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to budge the port out of a stuck state.
Software can write this bit to 0 and the SMB_SOFT_RST to 1 to force hung SMBus
controller and the SMB slaves to idle state without using power good reset or
warm reset.
Note: Software need to set the SMB_CKOVRD back to 1 after 35ms in order to
force slave devices to time-out in case there is any pending transaction.
The corresponding SMB_STAT_x.SMB_SBE error status bit may be set if
there was such pending transaction time-out (non-graceful termination).
If the pending transaction was a write operation, the slave device content
may be corrupted by this clock override operation. A subsequent SMB
command will automatically cleared the SMB_SBE.
Note: iMC added SMBus time-out control timer in ES2. When the time-out
control timer expired, the SMB_CKOVRD# will de-assert, that is, return
to 1 value and clear the SMB_SBE=0.
26
RW-O
0h
SMB_DIS_WRT
Disable SMBus Write
Writing a 0 to this bit enables CMD to be set to 1; Writing a 1 to force CMD bit to
be always 0, that is, disabling SMBus write. This bit can only be written 0/1 once
to enable SMB write disable feature. SMBus Read is not affected. I2C Write Pointer
Update Command is not affected.
Important Note to BIOS: Since BIOS is the source to update SMBCNTL_x register
initially after reset, it is important to determine whether the SMBus can have write
capability before writing any upper bits (bit24-31) via byte-enable config write (or
writing any bit within this register via 32b config write) within the SMBCNTL
register.
25:24
RV
0h
Reserved
20:11
RV
0h
Reserved
SMBCntl_[0:1]
Bus: 1
4.4.6.4
Device: 15
Function: 0
Bit
Attr
Default
Description
10
RW
0h
SMB_SOFT_RST
SMBus software reset strobe to graceful terminate pending transaction (after
ACK) and keep the SMB from issuing any transaction until this bit is cleared. If
slave device is hung, software can write this bit to 1 and the SMB_CKOVRD to 0
(for more than 35 ms) to force hung the SMB slaves to time-out and put it in idle
state without using power good reset or warm reset.
Note: Software need to set the SMB_CKOVRD back to 1 after 35 ms in order to
force slave devices to time-out in case there is any pending transaction.
The corresponding SMB_STAT_x.SMB_SBE error status bit may be set if
there was such pending transaction time-out (non-graceful termination).
If the pending transaction was a write operation, the slave device content
may be corrupted by this clock override operation. A subsequent SMB
command will automatically cleared the SMB_SBE.
RV
0h
Reserved
RW-LB
0h
SMB_TSOD_POLL_EN
TSOD polling enable
0: disable TSOD polling and enable SPDCMD accesses.
1: disable SPDCMD access and enable TSOD polling.
It is important to make sure no pending SMBus transaction and the TSOD polling
must be disabled (and pending TSOD polling must be drained) before changing
the TSODPOLLEN.
7:0
RW-LB
00h
4.4.6.5
Offset: 188
Bit
Attr
Default
31:18
RV
0h
17:0
RW-LV
00000h
Offset: 18C
Description
Reserved
SMB_TSOD_POLL_RATE_CNTR
TSOD poll rate counter. When it is decremented to zero, reset to zero or written to
zero, SMB_TSOD_POLL_RATE value is loaded into this counter and appear the
updated value in the next DCLK.
415
SMB_STAT_1
Bus: 1
416
Device: 15
Function: 0
Offset: 190
Bit
Attr
Default
Description
31
RO-V
0h
SMB_RDO
Read Data Valid
This bit is set by iMC when the Data field of this register receives read data from
the SPD/TSOD after completion of an SMBus read command. It is cleared by iMC
when a subsequent SMBus read command is issued.
30
RO-V
0h
SMB_WOD
Write Operation Done
This bit is set by iMC when a SMBus Write command has been completed on the
SMBus. It is cleared by iMC when a subsequent SMBus Write command is issued.
29
RO-V
0h
SMB_SBE
SMBus Error
This bit is set by iMC if an SMBus transaction (including the TSOD polling or SMBus
access) that does not complete successfully (non-Ack has been received from
slave at expected Ack slot of the transfer). If a slave device is asserting clock
stretching, IMC does not have logic to detect this condition to set the SBE bit
directly; however, the SMBus master will detect the error at the corresponding
transactions expected ACK slot.
This bit is cleared by iMC when an SMBus read/write command is issued or by
setting the SMBSoftRst.
28
ROS-V
0h
SMB_BUSY
SMBus Busy state. This bit is set by iMC while an SMBus/I2C command (including
TSOD command issued from IMC hardware) is executing. Any transaction that is
completed normally or gracefully will clear this bit automatically. By setting the
SMB_SOFT_RST will also clear this bit.
This register bit is sticky across reset so any surprise reset during pending SMBus
operation will sustain the bit assertion across surprised warm-reset. BIOS reset
handler can read this bit before issuing any SMBus transaction to determine
whether a slave device may need special care to force the slave to idle state (e.g.
via clock override toggling (SMB_CKOVRD) and/or via induced time-out by
asserting SMB_CKOVRD for 25-35ms).
Reserved
27
RV
0h
26:24
RO-V
111b
23:16
RV
0h
15:0
RO-V
0000h
4.4.6.6
Device: 15
Function: 0
Offset: 194
Bit
Attr
Default
Description
31
RW-V
0b
SMB_CMD_TRIGGER
CMD trigger: After setting this bit to 1, the SMBus master will issue the SMBus
command using the other fields written in SMBCMD_[0:1] and SMBCntl_[0:1].
Note: the -V in the attribute implies the hardware will reset this bit when the
SMBus command is being started.
30
RWS
0b
SMB_PNTR_SEL
Pointer Selection: SMBus/I2C present pointer based access enable when set;
otherwise, use random access protocol. Hardware based TSOD polling will also use
this bit to enable the pointer word read.
Important Note: the processor hardware based TSOD polling can be configured
with pointer based access. If software manually issue SMBus transaction to other
address, i.e. changing the pointer in the slave device, it is softwares responsibility
to restore the pointer in each TSOD before returning to hardware based TSOD
polling while keeping the SMB_PNTR_SEL=1.
29
RWS
0b
SMB_WORD_ACCESS
word access: SMBus/I2C word (2B) access when set; otherwise, it is a byte
access.
28
RWS
0b
SMB_WRT_PNTR
Bit[28:27]=00: SMBus Read
Bit[28:27]=01: SMBus Write
Bit[28:27]=10: illegal combination
Bit[28:27]=11: Write to pointer register SMBus/I2C pointer update (byte). bit 30,
and 29 are ignored. Note: SMBCntl_[0:1][26] will NOT disable WrtPntr update
command.
27
RWS
0b
SMB_WRT_CMD
When 0, it is a read command
When 1, it is a write command
26:24
RWS
000b
23:16
RWS
00h
SMB_BA
Bus Txn Address: This field identifies the bus transaction address to be accessed.
Note: in WORD access, 23:16 specifies 2B access address. In Byte access, 23:16
specified 1B access address.
15:0
RWS
0000h
SMB_WDATA
Write Data: Holds data to be written by SPDW commands.
Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a word
write, writing of I2C using word write should use SMB_WDATA[15:8]=I2C_MSB
and SMB_WDATA[7:0]=I2C_LSB. If writing of I2C using byte write, the
SMB_WDATA[15:8]=dont care; SMB_WDATA[7:0]=write_byte.
If we have a SMB slave connected on the bus, writing of the SMBus slave using
word write should use SMB_WDATA[15:8]=SMB_LSB and
SMB_WDATA[7:0]=SMB_MSB.
It is software responsibility to figure out the byte order of the slave access.
SMB_SA
Slave Address: This field identifies the DIMM SPD/TSOD to be accessed.
417
4.4.6.7
SMBCntl_1
Bus: 1
Device: 15
Function: 0
Offset: 198
Bit
Attr
Default
Description
31:28
RWS
1010b
SMB_DTI
Device Type Identifier: This field specifies the device type identifier. Only devices
with this device-type will respond to commands.
0011 specifies TSOD.
1010 specifies EEPROMs.
0110 specifies a write-protect operation for an EEPROM.
Other identifiers can be specified to target non-EEPROM devices on the SMBus.
Note: IMC based hardware TSOD polling uses hardcoded DTI. Changing this field
has no effect on the hardware based TSOD polling.
27
RWS
1h
SMB_CKOVRD
Clock Override
0 = Clock signal is driven low, overriding writing a 1 to CMD.
1 = Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to budge the port out of a stuck state.
Software can write this bit to 0 and the SMB_SOFT_RST to 1 to force hung SMBus
controller and the SMB slaves to idle state without using power good reset or
warm reset.
Note: software need to set the SMB_CKOVRD back to 1 after 35ms in order to
force slave devices to time-out in case there is any pending transaction. The
corresponding SMB_STAT_x.SMB_SBE error status bit may be set if there was
such pending transaction time-out (non-graceful termination). If the pending
transaction was a write operation, the slave device content may be corrupted by
this clock override operation. A subsequent SMB command will automatically
cleared the SMB_SBE.
26
RW-O
0h
SMB_DIS_WRT
Disable SMBus Write
Writing a 0 to this bit enables CMD to be set to 1; Writing a 1 to force CMD bit to
be always 0, that is, disabling SMBus write. This bit can only be written 0/1 once
to enable SMB write disable feature. SMBus Read is not affected. I2C Write Pointer
Update Command is not affected.
Important Note to BIOS: Since BIOS is the source to update SMBCNTL_x
register initially after reset, it is important to determine whether the SMBus can
have write capability before writing any upper bits (bit24-31) via byte-enable
config write (or writing any bit within this register via 32b config write) within the
SMBCNTL register.
418
25:11
RV
0h
Reserved
10
RW
0h
SMB_SOFT_RST
SMBus software reset strobe to graceful terminate pending transaction (after
ACK) and keep the SMB from issuing any transaction until this bit is cleared. If
slave device is hung, software can write this bit to 1 and the SMB_CKOVRD to 0
(for more than 35ms) to force hung the SMB slaves to time-out and put it in idle
state without using power good reset or warm reset.
Note: Software need to set the SMB_CKOVRD back to 1 after 35ms in order to
force slave devices to time-out in case there is any pending transaction.
The corresponding SMB_STAT_x.SMB_SBE error status bit may be set if
there was such pending transaction time-out (non-graceful termination).
If the pending transaction was a write operation, the slave device content
may be corrupted by this clock override operation. A subsequent SMB
command will automatically cleared the SMB_SBE.
RV
0h
Reserved
SMBCntl_1
Bus: 1
4.4.6.8
Device: 15
Offset: 198
Bit
Attr
Default
Description
RW-LB
0h
SMB_TSOD_POLL_EN
TSOD polling enable
0: disable TSOD polling and enable SPDCMD accesses.
1: disable SPDCMD access and enable TSOD polling.
It is important to make sure no pending SMBus transaction and the TSOD polling
must be disabled (and pending TSOD polling must be drained) before changing
the TSODPOLLEN.
7:0
RW-LB
00h
SMB_TSOD_POLL_RATE_CNTR_1
Bus: 1
Device: 15
4.4.6.9
Function: 0
Bit
Attr
Default
31:18
RV
0h
17:0
RW-LV
00000h
Function: 0
Offset: 19C
Description
Reserved
SMB_TSOD_POLL_RATE_CNTR
TSOD poll rate counter. When it is decremented to zero, reset to zero or written to
zero, SMB_TSOD_POLL_RATE value is loaded into this counter and appear the
updated value in the next DCLK.
SMB_PERIOD_CFG
Bus: 1
Device: 15
Function: 0
Offset: 1A0
Bit
Attr
Default
Description
15:0
RWS
0FA0h
SMB_CLK_PRD
This field specifies both SMBus Clock in number of DCLK. Note: In order to
generate a 50% duty cycle SCL, half of the SMB_CLK_PRD is used to generate SCL
high. SCL must stay low for at least another half of the SMB_CLK_PRD before
pulling high. It is recommend to program an even value in this field since the
hardware is simply doing a right shift for the divided by 2 operation.
For pre-Si validation, minimum 8 can be set to speed up the simulation.
Note the 100 KHz SMB_CLK_PRD default value is calculated based on 800 MT/s
(400 MHz) DCLK.
419
4.4.6.10
SMB_PERIOD_CNTR
Bus: 1
Device: 15
4.4.6.11
Function: 0
Offset: 1A4
Bit
Attr
Default
Description
31:16
RO-V
0000h
SMB1_CLK_PRD_CNTR
SMBus #1 Clock Period Counter for Ch 23This field is the current SMBus Clock
Period Counter Value.
15:0
RO-V
0000h
SMB0_CLK_PRD_CNTR
SMBus #0 Clock Period Counter for Ch 01This field is the current SMBus Clock
Period Counter Value.
SMB_TSOD_POLL_RATE
Bus: 1
Device: 15
Bit
Attr
Default
31:18
RV
0h
17:0
RWS
3E800h
Function: 0
Offset: 1A8
Description
Reserved
SMB_TSOD_POLL_RATE
TSOD poll rate configuration between consecutive TSOD accesses to the TSOD
devices on the same SMBus segment. This field specifies the TSOD poll rate in
number of 500 ns per CNFG_500_NANOSEC register field definition.
4.4.7
4.4.7.1
PXPCAP
Bus: 1
Bit
420
Device: 15
Attr
Function: 1
Default
Offset: 40
Description
31:30
RV
0h
29:25
RO
00h
Reserved
24
RO
0b
Slot Implemented
N/A for integrated endpoints
23:20
RO
9h
Device/Port Type
Device type is Root Complex Integrated Endpoint
19:16
RO
1h
Capability Version
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note: This capability structure is not compliant with Versions beyond 1.0, since
they require additional capability registers to be reserved. The only
purpose for this capability structure is to make enhanced configuration
space available. Minimizing the size of this structure is accomplished by
reporting version 1.0 compliancy and reporting that this is an integrated
root port device. As such, only three Dwords of configuration space are
required for this structure.
15:8
RO
00h
7:0
RO
10h
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
4.4.7.2
4.4.7.3
Attr
Function: 1
Default
31:30
RV
0h
29:0
RW-LV
000000
00h
Offset: 80
Description
Reserved
RANKADD
Always points to the lower address for the next sparing operation. This register
will not be affected by the HA access to the spare source rank during the HA
window.
Device: 15
Function: 1
Offset: 90
Bit
Attr
Default
31:30
RV
0h
Reserved
29
RW-LB
0b
DisWPQWM
Disable WPQ level based water mark, so that sparing wm is only based on
HaFifoWM.
If DisWPQWM is clear, the spare window is started when the number of hits to the
failed DIMM exceed max(# of credits in WPQ not yet returned to the HA,
HaFifoWM)
If DisWPQWM is set, the spare window starts when the number of hits to the failed
DIMM exceed HaFifoWM.
In either case, if the number of hits to the failed DIMM do not hit the WM, the
spare window will still start after SPAREINTERVAL.NORMOPDUR timer expiration.
28:24
RW-LB
00h
HaFifoWM
minimum water mark for HA writes to failed rank. Actual wm is max of WPQ credit
level and HaFifoWM. When wm is hit the HA is backpressured and a sparing
window is started.
If DisWPQWM is clear, the spare window is started when the number of hits to the
failed DIMM exceed max(# of credits in WPQ not yet returned to the HA,
HaFifoWM)
If DisWPQWM is set, the spare window starts when the number of hits to the failed
DIMM exceed HaFifoWM.
23:16
RW
00h
SCRATCH_PAD
This field is available as a scratch pad for SSR operations
15:11
RV
0h
10:8
RW-LB
000b
RV
0h
6:4
RW-LB
000b
Description
Reserved
DST_RANK
Destination logical rank used for the memory copy.
Reserved
SRC_RANK
Source logical rank that provides the data to be copied.
421
SPARECTL
Bus: 1
4.4.7.4
Device: 15
Function: 1
Offset: 90
Bit
Attr
Default
Description
3:2
RW-LB
00b
RV
0h
Reserved
RW-LB
0h
SPARE_ENABLE
Spare enable when set to 1. Hardware clear after the sparing completion.
4.4.7.5
Device: 15
Function: 1
Offset: 94
Bit
Attr
Default
Description
31:3
RV
0h
Reserved
RW1C
0h
PATCMPLT
All memory has been scrubbed. Hardware sets this bit each time the patrol engine
steps through all memory locations. If software wants to monitor 0 --> 1
transition after the bit has been set, the software will need to clear the bit by
writing a one to clear this bit in order to distinguish the next patrol scrub
completion. Clearing the bit will not affect the patrol scrub operation.
RO-V
0h
SPRCMPLT
Spare Operation Complete. Set by hardware once operation is complete. Bit is
cleared by hardware when a new operation is enabled.
Note: just before MC release the HA block prior to the completion of the sparing
operation, iMC logic will automatically update the corresponding RIR_RNK_TGT
target to reflect new DST_RANK.
RO-V
0h
SPRINPROGRESS
Spare Operation in progress. This bit is set by hardware once operation has
started. It is cleared once operation is complete or fails.
422
Bit
Attr
Default
31:30
RV
0h
Function: 1
Offset: 98
Description
Reserved
SCRUBADDRESSLO
Bus: 1
Device: 15
4.4.7.6
Bit
Attr
Default
29:0
RW-V
000000
00h
Function: 1
Offset: 98
Description
RANKADD
Contains the rank address of the last scrub issued. Can be written to specify the
next scrub address with STARTSCRUB. RESTRICTIONS: Patrol Scrubs must be
disabled when writing to this field.
4.4.7.7
Function: 1
Offset: 9C
Bit
Attr
Default
Description
31:12
RV
0h
Reserved
11:10
RW-V
0h
CHNL
Can be written to specify the next scrub address with STARTSCRUB. This register
is updated with channel address of the last scrub address issued. Restriction:
Patrol Scrubs must be disabled when writing to this field.
9:8
RV
0h
Reserved
7:4
RW-V
0h
RANK
Contains the physical rank ID of the last scrub issued. Can be written to specify
the next scrub address with STARTSCRUB. RESTRICTION: Patrol Scrubs must be
disabled when writing to this field.
3:0
RV
0h
Reserved
Device: 15
Function: 1
Offset: A0
Bit
Attr
Default
Description
31
RW-L
0b
Scrub Enable
Scrub Enable when set.
lock bit is the DISABLE_PATROL_SCRUB.
30:27
RV
0h
Reserved
26
RW
0h
SCRUBISSUED
When Set, the scrub address registers contain the last scrub address issued
25
RW
0h
ISSUEONCE
When Set, the patrol scrub engine will issue the address in the scrub address
registers only once and stop.
24
RW
0h
STARTSCRUB
When Set, the Patrol scrub engine will start from the address in the scrub address
registers. Once the scrub is issued this bit is reset.
423
SCRUBCTL
Bus: 1
4.4.7.8
Device: 15
Bit
Attr
Default
23:0
RW
0h
Function: 1
Offset: A0
Description
SCRUBINTERVAL
Defines the interval in DCLKS between patrol scrub requests.
The calculation for this register to get a scrub of every
line in 24 hours is:(DCLK_frequency*5529600)/
(memory_installed*PkgC_safety_factor). RESTRICTIONS: Can only be changed
when patrol scrubs are disabled.
DCLK_frequency is in Hz (one-half of the DDR speed class, for example:
800,000,000 for DDR3-1600 memory)
Memory_installed is in bytes
The recommended safety factor is 10 to compensate for maximum credible
PkgC residency time (patrol scrubbing does not occur during deeper PkgC
states).
4.4.7.9
Function: 1
Offset: A8
Bit
Attr
Default
Description
31:29
RV
0h
28:16
RW
0320h
NUMSPARE
Sparing operation duration. System requests will be blocked during this interval
and only sparing copy operations will be serviced.
15:0
RW
0C80h
Reserved
4.4.7.10
Device: 15
Function: 1
Offset: AC
Bit
Attr
Default
Description
31:1
RV
0h
Reserved
RW-LB
0h
MIRROREN
Mirror mode enable. The channel mapping must be set up before this bit will have
an effect on iMC operation. This changes the error policy.
424
Attr
Device: 15
Default
Function: 1
Offset: B4
Description
31:18
RV
0h
Reserved
17
RW
0h
INTRPT_SEL_PIN
Enable pin signaling. When set the interrupt is signaled via the ERROR_N[0] pin to
get the attention of a BMC.
SMISPARECTL
Bus: 1
4.4.7.11
Device: 15
Function: 1
Offset: B4
Bit
Attr
Default
Description
16
RW
0h
INTRPT_SEL_CMCI
(CMCI used as a proxy for NMI signaling). Set to enable NMI signaling. Clear to
disable NMI signaling. If both NMI and SMI enable bits are set then only SMI is
sent
15
RW
0h
INTRPT_SEL_SMI
SMI enable. Set to enable SMI signaling. Clear to disable SMI signaling.
14:0
RV
0h
Reserved
LEAKY_BUCKET_CFG
LEAKY_BUCKET_CFG
Bus: 1
Device: 15
Function: 1
Offset: B8
Bit
Attr
Default
Description
31:12
RV
0h
11:6
RW
00h
LEAKY_BKT_CFG_HI
This is the higher order bit select mask of the two hot encoding threshold. The
value of this field specify the bit position of the mask:
00h: reserved
01h: LEAKY_BUCKET_CNTR_LO bit 1, i.e. bit 12 of the full 53b counter
...
1Fh: LEAKY_BUCKET_CNTR_LO bit 31, i.e. bit 42 of the full 53b counter
20h: LEAKY_BUCKET_CNTR_HI bit 0, i.e. bit 43 of the full 53b counter
...
29h: LEAKY_BUCKET_CNTR_HI bit 9, i.e. bit 52 of the full 53b counter
2Ah - 3F: reserved
When both counter bits selected by the LEAKY_BKT_CFG_HI and
LEAKY_BKT_CFG_LO are set, the 53b leaky bucket counter will be reset and the
logic will generate a LEAK pulse to decrement the correctable error counter by 1.
BIOS must program this register to any non-zero value before switching to
NORMAL mode.
5:0
RW
00h
LEAKY_BKT_CFG_LO
This is the lower order bit select mask of the two hot encoding threshold. The
value of this field specify the bit position of the mask:
00h: reserved
01h: LEAKY_BUCKET_CNTR_LO bit 1, i.e. bit 12 of the full 53b counter
...
1Fh: LEAKY_BUCKET_CNTR_LO bit 31, i.e. bit 42 of the full 53b counter
20h: LEAKY_BUCKET_CNTR_HI bit 0, i.e. bit 43 of the full 53b counter
...
29h: LEAKY_BUCKET_CNTR_HI bit 9, i.e. bit 52 of the full 53b counter
2Ah - 3F: reserved
When both counter bits selected by the LEAKY_BKT_CFG_HI and
LEAKY_BKT_CFG_LO are set, the 53b leaky bucket counter will be reset and the
logic will generate a LEAK pulse to decrement the correctable error counter by 1.
BIOS must program this register to any non-zero value before switching to
NORMAL mode.
Reserved
425
4.4.7.12
LEAKY_BUCKET_CNTR_LO
LEAKY_BUCKET_CNTR_LO
Bus: 1
Device: 15
4.4.7.13
Function: 1
Offset: C0
Bit
Attr
Default
Description
31:0
RW-V
000000
00h
LEAKY_BUCKET_CNTR_HI
LEAKY_BUCKET_CNTR_HI
Bus: 1
Device: 15
Bit
Attr
Default
31:10
RV
0h
9:0
RW-V
000h
Function: 1
Offset: C4
Description
Reserved
Leaky Bucket Counter High Limit
This is the upper half of the leaky bucket counter. The full counter is actually a 53b
DCLK counter. There is a least significant 11b of the 53b counter is not captured
in CSR. The carry strobe from the not-shown least significant 11b counter will
trigger this 42b counter pair to count. The 42b counter-pair is compared with the
two-hot encoding threshold specified by the LEAKY_BUCKET_CFG_HI and
LEAKY_BUCKET_CFG_LO pair. When the counter bits specified by the
LEAKY_BUCKET_CFG_HI and LEAKY_BUCKET_CFG_LO are both set, the 53b
counter is reset and the leaky bucket logic will generate a LEAK strobe last for 1
DCLK.
4.4.8
4.4.8.1
PXPCAP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
Bit
426
Device:
Device:
Device:
Device:
Attr
15
15
15
15
Function:
Function:
Function:
Function:
2
3
4
5
Default
Offset:
Offset:
Offset:
Offset:
40
40
40
40
Description
31:30
RV
0h
29:25
RO
00h
Reserved
24
RO
0b
Slot Implemented
N/A for integrated endpoints
23:20
RO
9h
Device/Port Type
Device type is Root Complex Integrated Endpoint
PXPCAP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.8.2
Device:
Device:
Device:
Device:
15
15
15
15
Function:
Function:
Function:
Function:
2
3
4
5
Offset:
Offset:
Offset:
Offset:
40
40
40
40
Bit
Attr
Default
Description
19:16
RO
1h
Capability Version
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since they
require additional capability registers to be reserved. The only purpose for this
capability structure is to make enhanced configuration space available. Minimizing
the size of this structure is accomplished by reporting version 1.0 compliancy and
reporting that this is an integrated root port device. As such, only three Dwords of
configuration space are required for this structure.
15:8
RO
00h
7:0
RO
10h
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
DIMMMTR_[0:2]
Bus: 1
Bus: 1
Bus: 1
Bus: 1
Bit
Device:
Device:
Device:
Device:
15
15
15
15
Function:
Function:
Function:
Function:
2
3
4
5
Offset:
Offset:
Offset:
Offset:
80,
80,
80,
80,
84,
84,
84,
84,
88
88
88
88
Attr
Default
Description
31:20
RV
0h
Reserved
19:16
RW-LB
0h
RANK_DISABLE control
RANK Disable Control to disable patrol, refresh and ZQCAL operation. This bit
setting must be set consistently with TERM_RNK_MSK, i.e. both corresponding
bits cannot be set at the same time. In the other word, a disabled rank must not
be selected for the termination rank.
RANK_DISABLE[3], i.e. bit 19: rank 3 disable. Note
DIMMMTR_2.RANK_DISABLE[3] is dont care since DIMM 2 must not be quad-rank
RANK_DISABLE[2], i.e. bit 18: rank 2 disable. Note
DIMMMTR_2.RANK_DISABLE[2] is dont care since DIMM 2 must not be quad-rank
RANK_DISABLE[1], i.e. bit 17: rank 1 disable
RANK_DISABLE[0], i.e. bit 16: rank 0 disable
when set, no patrol or refresh will be perform on this rank. ODT termination is not
affected by this bit.
15
RV
0h
Reserved
14
RW-LB
0h
DIMM_POP
DIMM populated if set; otherwise, unpopulated.
13:12
RW-LB
0h
RANK_CNT
00 - SR
01 - DR
10 - QR
11 - reserved
11:9
RV
0h
Reserved
427
DIMMMTR_[0:2]
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.9
Device:
Device:
Device:
Device:
15
15
15
15
Function:
Function:
Function:
Function:
2
3
4
5
Offset:
Offset:
Offset:
Offset:
80,
80,
80,
80,
84,
84,
84,
84,
88
88
88
88
Bit
Attr
Default
Description
4:2
RW-LB
0h
RA_WIDTH
000 - reserved (the processor does not support 512Mb DDR3)
001 - 13 bits
010 - 14 bits
011 - 15 bits
100 - 16 bits
101 - 17 bits
110 - 18 bits
111: reserved
1:0
RW-LB
0h
CA_WIDTH
00 - 10 bits
01 - 11 bits
10 - 12 bits
11 - reserved
4.4.9.1
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:20
RO
000h
15
15
15
15
Function:
Function:
Function:
Function:
2
3
4
5
Offset:
Offset:
Offset:
Offset:
100
100
100
100
Description
Next Capability Offset
4.4.10
4.4.10.1
428
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:30
RV
0h
29:25
RO
00h
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
40
40
40
40
Description
Reserved
Interrupt Message Number
N/A for this device
PXPCAP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.10.2
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
40
40
40
40
Bit
Attr
Default
Description
24
RO
0b
Slot Implemented
N/A for integrated endpoints
23:20
RO
9h
Device/Port Type
Device type is Root Complex Integrated Endpoint
19:16
RO
1h
Capability Version
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note: This capability structure is not compliant with Versions beyond 1.0, since
they require additional capability registers to be reserved. The only
purpose for this capability structure is to make enhanced configuration
space available. Minimizing the size of this structure is accomplished by
reporting version 1.0 compliancy and reporting that this is an integrated
root port device. As such, only three Dwords of configuration space are
required for this structure.
15:8
RO
00h
7:0
RO
10h
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
108
108
108
108
Bit
Attr
Default
31
RW
1h
OLTT_EN
Enable OLTT temperature tracking
30
RV
0h
Reserved
29
RW
0h
CLTT_OR_MCODE_TEMP_MUX_SEL
The TEMP_STAT byte update mux select control to direct the source to update
DIMMTEMPSTAT_[0:3][7:0]:0: Corresponding to the DIMM TEMP_STAT byte from
PCODE_TEMP_OUTPUT.
1: TSOD temperature reading from CLTT logic.
28
RW-O
1b
CLTT_DEBUG_DISABLE_LOCK
lock bit of DIMMTEMPSTAT_[0:3][7:0]:Set this lock bit to disable configuration
write to DIMMTEMPSTAT_[0:3][7:0]. When this bit is clear, system debug/test
software can update the DIMMTEMPSTAT_[0:3][7:0] to verify various temperature
scenerios.
27
RW
1b
26:24
RV
0h
23:16
RW
00h
Description
THRT_EXT
Max number of throttled transactions to be issued during BW_LIMIT_TF due to
externally asserted MEMHOT#.
429
CHN_TEMP_CFG
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.10.3
Device:
Device:
Device:
Device:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
108
108
108
108
Attr
Default
Description
15
RW
0b
THRT_ALLOW_ISOCH
When this bit is zero, MC will lower CKE during Thermal Throttling, and ISOCH is
blocked. When this bit is one, MC will NOT lower CKE during Thermal Throttling,
and ISOCH will be allowed base on bandwidth throttling setting. However, setting
this bit would mean more power consumption due to CKE is asserted during
thermal or power throttling.
This bit can be updated dynamically in independent channel configuration only.
For lock-step configuration, this bit must be statically set during IOSAV mode
before enabling the lock-step operation. Dynamic update in lock-step mode will
put the two lock-stepped channels out-of-sync and cause functional failure or
silent data corruption.
Reserved
14:11
RV
0h
10:0
RW
3FFh
BW_LIMIT_TF
BW Throttle Window Size in DCLK
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Bit
Attr
Default
31:3
RV
0h
Reserved
RW1C
0b
RW1C
0b
RW1C
0b
Offset:
Offset:
Offset:
Offset:
10C
10C
10C
10C
Description
430
Function:
Function:
Function:
Function:
Bit
CHN_TEMP_STAT
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.10.4
16
16
16
16
Attr
16
16
16
16
Default
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
110,
110,
110,
110,
114,
114,
114,
114,
118
118
118
118
Description
31:27
RV
0h
Reserved
26:24
RW
0h
TEMP_OEM_HI_HYST
Positive going Threshold Hysteresis Value. This value is subtracted from
TEMPOEMHI to determine the point where the asserted status for that threshold
will clear. Set to 00h if sensor does not support positive-going threshold hysteresis
23:19
RV
0h
Reserved
18:16
RW
0h
TEMP_OEM_LO_HYST
Negative going Threshold Hysteresis Value. This value is added to TEMPOEMLO to
determine the point where the asserted status for that threshold will clear. Set to
00h if sensor does not support negative-going threshold hysteresis.
DIMM_TEMP_OEM_[0:2]
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
4.4.10.5
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
110,
110,
110,
110,
114,
114,
114,
114,
118
118
118
118
Bit
Attr
Default
Description
15:8
RW
50h
TEMP_OEM_HI
Upper Threshold value - TCase threshold at which to Initiate System Interrupt
(SMI or MEMHOT#) at a + going rate. Note: the default value is listed in
decimal.valid range: 32 - 127 in degree C.
Others: reserved.
7:0
RW
4Bh
TEMP_OEM_LO
Lower Threshold Value - TCase threshold at which to Initiate System Interrupt
(SMI or MEMHOT#) at a - going rate. Note: the default value is listed in
decimal.valid range: 32 - 127 in degree C.
Others: reserved.
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
120,
120,
120,
120,
124,
124,
124,
124,
128
128
128
128
Bit
Attr
Default
Description
31:27
RV
0h
Reserved
26:24
RW
0h
TEMP_THRT_HYST
Positive going Threshold Hysteresis Value. Set to 00h if sensor does not support
positive-going threshold hysteresis. This value is subtracted from TEMP_THRT_XX
to determine the point where the asserted status for that threshold will clear.
23:16
RW
5Fh
TEMP_HI
TCase threshold at which to Initiate THRTCRIT and assert THERMTRIP# valid
range: 32 - 127 in degree C. Note: the default value is listed in decimal.
FF: Disabled
Others: reserved.
TEMP_HI should be programmed so it is greater than TEMP_MID
15:8
RW
5Ah
TEMP_MID
TCase threshold at which to Initiate THRTHI and assert valid range: 32 - 127 in
degree C.
Note: the default value is listed in decimal.
FF: Disabled
Others: reserved.
TEMP_MID should be programmed so it is less than TEMP_HI
7:0
RW
55h
TEMP_LO
TCase threshold at which to Initiate 2x refresh and/or THRTMID and initiate
Interrupt (MEMHOT#).
Note: the default value is listed in decimal.valid range: 32 - 127 in degree C.
FF: Disabled
Others: reserved.
TEMP_LO should be programmed so it is less than TEMP_MID
431
4.4.10.6
4.4.10.7
0
1
4
5
Offset:
Offset:
Offset:
Offset:
130,
130,
130,
130,
134,
134,
134,
134,
138
138
138
138
Bit
Attr
Default
Description
31:24
RV
0h
23:16
RW
00h
THRT_CRIT
Max number of throttled transactions (ACT, READ, WRITE) to be issued during
BW_LIMIT_TF.
15:8
RW
0Fh
THRT_HI
Max number of throttled transactions (ACT, READ, WRITE) to be issued during
BW_LIMIT_TF.
7:0
RW
FFh
THRT_MID
Max number of throttled transactions (ACT, READ, WRITE) to be issued during
BW_LIMIT_TF.
Reserved
432
Function:
Function:
Function:
Function:
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
140,
140,
140,
140,
144,
144,
144,
144,
148
148
148
148
Bit
Attr
Default
Description
31:24
RO
00h
TEMP_AVG_INTRVL
Temperature data is averaged over this period. At the end of averaging period
(ms), averaging process starts again. 0x1 - 0xFF = Averaging data is read via
TEMPDIMM STATUSREGISTER (Byte 1/2) as well as used for generating hysteresis
based interrupts.
00 = Instantaneous Data (non-averaged) is read via TEMPDIMM
STATUSREGISTER (Byte 1/2) as well as used for generating hysteresis based
interrupts.
Note: The processor does not support temp averaging.
23:15
RV
0h
Reserved
14
RW
0b
13
RW
1b
12
RW
0b
11
RW
0b
10
RW
0b
DIMM_TEMP_EV_OFST_[0:2]
Bus: 1
Device: 16
Bus: 1
Device: 16
Bus: 1
Device: 16
Bus: 1
Device: 16
4.4.10.8
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
140,
140,
140,
140,
Bit
Attr
Default
RW
0b
RW
0b
7:4
RV
0h
Reserved
3:0
RW
0h
DIMM_TEMP_OFFSET
Bit 3-0 - Temperature Offset Register
144,
144,
144,
144,
148
148
148
148
Description
Attr
16
16
16
16
Default
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
150,
150,
150,
150,
154,
154,
154,
154,
158
158
158
158
Description
31:29
RV
0h
Reserved
28
RW1C
0b
27
RW1C
0b
26
RW1C
0b
25
RW1C
0b
24
RW1C
0b
23:8
RV
0h
Reserved
433
DIMMTEMPSTAT_[0:2]
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
4.4.10.9
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
150,
150,
150,
150,
154,
154,
154,
154,
158
158
158
158
Bit
Attr
Default
Description
7:0
RW-LV
55h
DIMM_TEMP
Current DIMM Temperature for thermal throttling. Lock by
CLTT_DEBUG_DISABLE_LOCK
When the CLTT_DEBUG_DISABLE_LOCK is cleared (unlocked), debug software can
write to this byte to test various temperature scenarios.
When the CLTT_DEBUG_DISABLE_LOCK is set, this field becomes read-only, that
is, configuration write to this byte is aborted. This byte is updated from internal
logic from a 2:1 Mux which can be selected from either CLTT temperature or from
the corresponding uCR temperature registers output (MCODE_TEMP_OUTPUT)
updated from the microcode. The mux select is controlled by
CLTT_OR_MCODE_TEMP_MUX_SEL defined in CHN_TEMP_CFG register.
Valid range from 0 to 127 (that is, 0C to +127C). Any negative value read from
TSOD is forced to 0. TSOD decimal point value is also truncated to integer value.
The default value is changed to 85C to avoid missing refresh during S3 resume or
during warm-reset flow after the DIMM is exiting self-refresh. The correct
temperature may not be fetched from TSOD yet but the DIMM temperature may
be still high and need to be refreshed at 2x rate.
THRT_PWR_DIMM_[0:2]: THRT_PWR_DIMM_0
Bit[10:0]: Max number of transactions (ACT, READ, WRITE) to be allowed during the
1 usec throttling time frame per power throttling.
THRT_PWR_DIMM_[0:2]
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
190,
190,
190,
190,
192,
192,
192,
192,
194
194
194
194
Bit
Attr
Default
15
RW
1b
THRT_PWR_EN
bit[15]: set to one to enable the power throttling for the DIMM.
Reserved
14:12
RV
0h
11:0
RW
FFFh
Description
4.4.11
4.4.11.1
Note:
T_AL register field has been removed in this release due to design complexity.
Throughout this document, T_AL has a constant zero value.
TCDBP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
434
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:27
RV
0h
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
200
200
200
200
Description
Reserved
TCDBP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.11.2
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
200
200
200
200
Bit
Attr
Default
Description
26
RW
0b
cmd_oe_cs
Command/Address output enable follows CS output enable. Cmd_oe_on overrides
cmd_ow_cs
25
RW
0b
cmd_oe_on
Command/Address output enable always on.
24:19
RW
1Ch
T_RAS
ACT to PRE command period (must be at least 10 and at most 40)
18:14
RW
07h
T_CWL
CAS Write Latency (must be at least 5) Note: tWL=tAL+tCWL
Programming Limitation: tCL - tWL cant be more than 4 DCLK cycles
13:9
RW
0Ah
T_CL
CAS Latency (must be at least 5)Note: RL=tAL+tCL.
Programming Limitation: tCL - tWL cant be more than 4 DCLK cycles.
8:5
RW
Ah
4:0
RW
0Ah
T_RP
PRE command period (must be at least 5)
T_RCD
ACT to internal read or write delay time in DCLK (must be at least 5)
Programming Limitation: T_RCD must be smaller than T_RAS
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
204
204
204
204
Bit
Attr
Default
Description
31:30
RW
0h
CMD_STRETCH
defines for how many cycles the command is stretched00: 1N operation
01: Reserved
10: 2N operation
11: 3N operation
28:24
RW
Ch
T_WR
WRITE recovery time (must be at least 15ns equivalent)
23:22
RV
0h
Reserved
21:16
RW
20h
15:12
RW
6h
T_WTR
DCLK delay from start of internal write transaction to internal read command
(must be at least the larger value of 4 DCLK or 7.5ns)
iMCs Write to Read Same Rank (T_WRSR) is automatically calculated based from
TCDBP.T_CWL + 4 + T_WTR.
For LRDIMM running in rank multiplication mode, iMC will continue to use the
above equation for T_WRSR even if the WRITE and READ are targeting same
logical rank but at different physical ranks behind the LRDIMM buffer, In the other
word, iMC will not be able to dynamically switch to T_WRDR timing. In order to
avoid timing violation in this scenario, BIOS must configure the T_WTR parameter
to be the MAX(T_WTR of LRDIMM, (T_WRDR - T_CL + 2)).
11:8
RW
3h
T_CKE
CKE minimum pulse width (must be at least the larger value of 3 DCLK or 5 ns)
T_FAW
Four activate window (must be at least 4*tRRD and at most 63)
435
TCRAP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.11.3
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
204
204
204
204
Bit
Attr
Default
7:4
RW
Ah
T_RTP
Internal READ Command to PRECHARGE Command delay, (must be at least the
larger value of 4 DCLK or 7.5 ns)
RV
0h
Reserved
2:0
RW
5h
T_RRD
ACTIVE to ACTIVE command period, (must be at least the larger value of 4 DCLK
or 6 ns)
Description
436
16
16
16
16
Device:
Device:
Device:
Device:
Attr
16
16
16
16
Default
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
208
208
208
208
Description
31:30
RV
0h
Reserved
29:27
RW
0h
T_CCD
back to back CAS to CAS (that is, READ to READ or WRITE to WRITE) from same
rank separation parameter.The actual JEDEC CAS to CAS command separation is
(T_CCD + 4) DCLKs measured between the clock assertion edges of the two
corresponding asserted command CS#.
26:24
RW
2h
T_RWSR
This field is no longer used starting in ES2 steppings. Please refer to TCOTHP for
the new register field location.
23:21
RW
2h
T_WRDD
Back to back WRITE to READ from different DIMM separation parameter.The
actual WRITE to READ command separation is
TCDBP.T_CWL - TCDBP.T_CL + T_WRDD + 6 DCLKs measured between the clock
assertion edges of the two corresponding asserted command CS#.
20:18
RW
2h
T_WRDR
Back to back WRITE to READ from different RANK separation parameter.The actual
WRITE to READ command separation is
TCDBP.T_CWL - TCDBP.T_CL + T_WRDR + 6 DCLKs measured between the clock
assertion edges of the two corresponding asserted command CS#.
17:15
RW
2h
T_RWDD
This field is no longer used starting in ES2 steppings. Please refer to TCOTHP for
the new register field location.
14:12
RW
2h
T_RWDR
This field is no longer used starting in ES2 steppings. Please refer to TCOTHP for
the new register field location.
11:9
RW
2h
T_WWDD
Back to back WRITE to WRITE from different DIMM separation parameter. The
actual WRITE to WRITE command separation is
T_WWDD + 5 DCLKs measured between the clock assertion edges of the two
corresponding asserted command CS#. Please note that the minimum setting of
the field must meet the DDRIO requirement for WRITE to WRITE turnaround time
to be at least 6 DClk at the DDRIO pin.
The maximum design range from the above calculation is 15.
TCRWP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.11.4
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
208
208
208
208
Bit
Attr
Default
Description
8:6
RW
2h
T_WWDR
Back to back WRITE to WRITE from different RANK separation parameter. The
actual WRITE to WRITE command separation is:
T_WWDR + 5 DCLKs measured between the clock assertion edges of the two
corresponding asserted command CS#. Please note that the minimum setting of
the field must meet the DDRIO requirement for WRITE to WRITE turnaround time
to be at least 6 DClk at the DDRIO pin.
The maximum design range from the above calculation is 15.
5:3
RW
2h
T_RRDD
Back to back READ to READ from different DIMM separation parameter. The actual
READ to READ command separation is:
T_RRDD + 5 DCLKs measured between the clock assertion edges of the two
corresponding asserted command CS#. Please note that the minimum setting of
the field must meet the DDRIO requirement for READ to READ turnaround time to
be at least 5 DClk at the DDRIO pin.
The maximum design range from the above calculation is 31.
2:0
RW
2h
T_RRDR
Back to back READ to READ from different RANK separation parameter. The actual
READ to READ command separation is:
T_RRDR + 5 DCLKs measured between the clock assertion edges of the two
corresponding asserted command CS#. Please note that the minimum setting of
the field must meet the DDRIO requirement for READ to READ turnaround time to
be at least 5 DClk at the DDRIO pin.
The maximum design range from the above calculation is 31.
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
20C
20C
20C
20C
Bit
Attr
Default
Description
31:28
RW
6h
t_cs_oe
Delay in Dclks to disable CS output after all CKE pins are low
27:24
RW
6h
t_odt_oe
Delay in Dclks to disable ODT output after all CKE pins are low and either in selfrefresh or in IBTOff mode
23:20
RW
2h
t_rwsr
Back to back READ to WRITE from same rank separation parameter. The actual
READ to WRITE command separation targeting same rank is
TCDBP.T_CL - TCDBP.T_CWL + T_RWSR + 6 DCLKs measured between the clock
assertion edges of the two corresponding asserted command CS#.
The maximum design range from the above calculation is 23.
For LRDIMM running in rank multiplication mode, iMC will continue to use the
above equation for T_RWSR even if the READ and WRITE are targeting same
logical rank but at different physical ranks behind the LRDIMM buffer, i.e. iMC will
not be able to dynamically switch to T_RWDR timing. In order to avoid timing
violation in this scenario, BIOS must configure the T_RWSR parameter to be the
MAX(T_RWSR of LRDIMM, T_RWDR).
19:16
RW
2h
t_rwdd
Back to back READ to WRITE from different DIMM separation parameter. The
actual READ to WRITE command separation is
TCDBP.T_CL - TCDBP.T_CWL + T_RWDD + 6 DCLKs measured between the clock
assertion edges of the two corresponding asserted command CS#.
The maximum design range from the above calculation is 23.
437
TCOTHP
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.11.5
Device:
Device:
Device:
Device:
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
20C
20C
20C
20C
Bit
Attr
Default
15:12
RW
2h
t_rwdr
Back to back READ to WRITE from different RANK separation parameter. The
actual READ to WRITE command separation is
TCDBP.T_CL - TCDBP.T_CWL + T_RWDR + 6 DCLKs measured between the clock
assertion edges of the two corresponding asserted command CS#.
The maximum design range from the above calculation is 23.
11
RW
0b
shift_odt_early
This shifts the ODT waveform one cycle early relative to the timing set up in the
ODT_TBL2 register, when in 2N or 3N mode. This bit has no effect in 1N mode
10:8
RW
0h
T_CWL_ADJ
This register defines additional WR data delay per channel in order to overcome
the WR-flyby issue. The total CAS write latency that the DDR sees is the sum of
T_CWL and the T_CWL_ADJ.
000 - no added latency (default)
001 - 1 Dclk of added latency
010 - 2 Dclk of added latency
011 - 3 Dclk of added latency
1xx - Reduced latency by 1 Dclk. Not supported at tCWL=5
7:5
RW
3h
T_XP
Exit Power Down with DLL on to any valid command; Exit Precharge Power Down
with DLL frozen to commands not requiring a locked DLL.
4:0
RW
Ah
T_XPDLL
Exit Precharge Power Down with DLL frozen to commands requiring a locked DLL
Description
438
16
16
16
16
Device:
Device:
Device:
Device:
Attr
16
16
16
16
Default
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
210
210
210
210
Description
31:16
RV
0h
Reserved
15:12
RW
9h
REF_PANIC_WM
tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to utilize the
maximum no-refresh period possible
11:8
RW
8h
REF_HI_WM
tREFI count level that turns the refresh priority to high (default is 8)
7:0
RW
3Fh
OREFNI
Rank idle period that defines an opportunity for refresh, in DCLK cycles
4.4.11.6
4.4.11.7
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
214
214
214
214
Bit
Attr
Default
Description
31:25
RW
9h
T_REFIX9
period of min between 9*T_REFI and tRAS maximum (normally 70 us) in 1024 *
DCLK cycles.The default value will need to reduce 100 DCLK cycles - uncertainty
on timing of panic refresh
24:15
RW
080h
T_RFC
Time of refresh - from beginning of refresh until next ACT or refresh is allowed (in
DCLK cycles)
Here are the recommended T_RFC for 2Gb DDR3:
0800 MT/s: 040h
1067 MT/s: 056h
1333 MT/s: 06Bh
1600 MT/s: 080h
1867 MT/s: 096h
14:0
RW
062Ch
T_REFI
Defines the average period between refreshes in DCLK cycles. This register
defines the 15b tREFI counter limit.
Here are the recommended T_REFI[14:0] setting for 7.8 usec:
0800 MT/s: 0C30h
1067 MT/s: 1040h
1333 MT/s: 1450h
1600 MT/s: 1860h
1867 MT/s: 1C70h
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
218
218
218
218
Bit
Attr
Default
Description
31:27
RW
ch
T_MOD
Mode Register Set command update delay.
26
RV
0h
Reserved
25:16
RW
100h
15:12
RW
Bh
11:0
RW
100h
T_ZQOPER
Normal operation Full calibration time
T_XSOFFSET
tXS = T_RFC+10ns. Setup of T_XSOFFSET is # of cycles for 10 ns. Range is
between 3 and 11 DCLK cycles
T_XSDLL
Exit Self Refresh to commands requiring a locked DLL in the range of 128 to 4095
DCLK cycles
439
4.4.11.8
4.4.11.9
Bit
Attr
Default
31:27
RV
0h
26:24
RW-LV
000b
23:16
RW
02h
15
RV
0h
14:12
RW
000b
11
RV
0h
10:8
RW
000b
7:6
RV
0h
5:0
RW
18h
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
21C
21C
21C
21C
Description
Reserved
ADDR_BIT_SWIZZLE
Each bit is set in case of the corresponding 2-rank UDIMM or certain LRDIMM
requires address mirroring/swizzling. It indicates that some of the address bits are
swizzled for rank 1 (or rank 3), and this has to be considered in MRS command.
The address swizzling bits:
A3 and A4
A5 and A6
A7 and A8
BA0 and BA1
Bit 24 refers to DIMM 0
Bit 25 refers to DIMM 1
Bit 26 refers to DIMM 2
MR2_SHDW_A15TO8
Copy of MR2 A[15:8] shadow.
Bit 23-19: zero, copy of MR2 A[15:11], reserved for future JEDEC use
Bit 18-17: Rtt_WR, that is, copy of MR2 A[10:9]
Bit 16: zero, copy of MR2 A[8], reserved for future JEDEC use
Reserved
MR2_SHDW_A7_SRT
Copy of MR2 A[7] shadow which defines per DIMM availability of SRT mode - set if
extended temperature range and ASR is not supported, otherwise cleared
Bit 14: Dimm 2
Bit 13: Dimm 1
Bit 12: Dimm 0
Reserved
MR2_SHDW_A6_ASR
Copy of MR2 A[6] shadow which defines per DIMM availability of ASR mode - set if
Auto Self-Refresh (ASR) is supported, otherwise cleared
Bit 10: Dimm 2
Bit 9: Dimm 1
Bit 8: Dimm 0
Reserved
MR2_SHDW_A5TO0
Copy of MR2 A[5:0] shadow
440
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:16
RV
0h
15:8
RW
40h
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
220
220
220
220
Description
Reserved
T_ZQCS
tZQCS in DCLK cycles (32 to 255, default is 64)
TCZQCAL
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.11.10
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
220
220
220
220
Bit
Attr
Default
Description
7:0
RW
80h
ZQCSPERIOD
Time between ZQ-FSM initiated ZQCS operations in tREFI*128 (2 to 255, default
is 128).
Note: ZQCx is issued at SRX.
TCSTAGGER_REF: TCSTAGGER_REF
tRFC like timing constraint parameter except it is a timing constraint applicable to REFREF separation between different ranks on a channel.
TCSTAGGER_REF
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.11.11
Device:
Device:
Device:
Device:
Bit
Attr
Default
31:10
RV
0h
9:0
RW
080h
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
224
224
224
224
Description
Reserved
T_STAGGER_REF
tRFC like timing constraint parameter except it is a timing constraint applicable to
REF-REF separation between different ranks on a channel.
It is recommended to set T_STAGGER_REF equal or less than the TRFC parameter
which is defined as:
0800 MT/s: 040h
1067 MT/s: 056h
1333 MT/s: 06Bh
1600 MT/s: 080h
1867 MT/s: 096h
Attr
Device:
Device:
Device:
Device:
16
16
16
16
Default
31:12
RV
0h
11:0
RW
000h
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
22C
22C
22C
22C
Description
Reserved
MR0_SHADOW
BIOS programs this field for MR0 register A11:A0 for all DIMM's in this channel.
iMC hardware is dynamically issuing MRS to MR0 to control the fast and slow exit
PPD (MRS MR0 A12). Other address bits (A[11:0]) is defined by this register field.
A15:A13 are always zero.
441
4.4.11.12
RPQAGE
Read Pending Queue Age Counters.
RPQAGE
Bus: 1
Bus: 1
Bus: 1
Bus: 1
Bit
4.4.11.13
Device:
Device:
Device:
Device:
Attr
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Default
31:26
RV
0h
25:16
RW
000h
15:10
RV
0h
9:0
RW
000h
Offset:
Offset:
Offset:
Offset:
234
234
234
234
Description
Reserved
IOCount
The name is misleading. Instead, it is RPQ Age Counter for the Medium and Low
priority (VC0) non-isoch transactions issued from HA. The counter is increased by
one every time theres a CAS command sent. When the RPQ Age Counter is equal
to this configured field value, the non-isoch transaction is aged to the next priority
level. BIOS must set this field to non-zero value before setting the
MCMTR.NORMAL=1.
Reserved
Intel Xeon Processor E5 Family GTCount
The name is misleading. Instead, it is RPQ Age Counter for the High priority (VCP)
transactions and Critical priority (VC1) isoch transactions issued from HA. The
counter is increased by one every time theres a CAS command sent. When the
RPQ Age Counter is equal to this configured field value, the isoch transaction is
aged to the next priority level. BIOS must set this field to non-zero value before
setting the MCMTR.NORMAL=1.
442
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
238
238
238
238
Bit
Attr
Default
Description
31:29
RV
0h
Reserved
28
RW
1b
ADAPT_PG_CLSE
This register is programmed in conjunction with MCMTR.CLOSE_PG to enable
three different modes:
(1) Closed Page Mode -- MCMTR.CLOSE_PG = 1 and ADAPT_PG_CLSE= 0
(2) Open Page Mode -- MCMTR.CLOSE_PG = 0 and ADAPT_PG_CLSE= 0
(3) Adaptive Open -- MCMTR.CLOSE_PG = 0 and ADAPT_PG_CLSE= 1
MCMTR.CLOSE_PG = 1 and ADAPT_PG_CLSE = 1 is illegal.
When ADAPT_PG_CLSE=0, the page close idle timer gets set with
IDLE_PAGE_RST_VAL times 4.
27:21
RW
06h
OPC_TH
Overdue Page Close (OPC) Threshold
If the number of OPCs in a given window is larger than this threshold, we
decrease the RV.
IDLETIME
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.11.14
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
238
238
238
238
Bit
Attr
Default
Description
20:14
RW
06h
PPC_TH
Premature Page Close (PPC) Threshold
If the number of PPCs in a given window is larger than this threshold, we increase
the RV
13:6
RW
40h
WIN_SIZE
Window Size (WS): The number of requests that we track before making a
decision to adapt the RV.
5:0
RW
08h
IDLE_PAGE_RST_VAL
Idle Counter Reset Value (RV): This is the value that effectively adapts. It
determines what value the various ICs are set to whenever they are reset. It
therefore controls the number of cycles before an automatic page close is
triggered for an entire channel.
RDIMMTIMINGCNTL
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
23C
23C
23C
23C
Bit
Attr
Default
Description
31:29
RV
0h
28:16
RW
12C0h
15:4
RV
0h
Reserved
3:0
RW
8h
T_MRD
Command word to command word programming delay in DCLK
Reserved
T_STAB
Stabilizing time in number of DCLK, i.e. the DCLK must be stable for T_STAB
before any access to the device take place. Note #1: zero value in T_STAB is
reserved and it is important to AVOID programming a zero value in the T_STAB.
Recommended settings (Note: contains stretch goal and/or over-clock frequency
examples):
FREQ T_STAB for RDIMM (including tCKSRX value)
0800 0960h+5h=0965h
1067 0C80h+5h=0c85h
1333 0FA0h+7h=0FA7h
1600 12C0h+8h=12C8h
1867 15E0h+Ah=15EAh
2133 1900h+Bh=190Bh
FREQ T_STAB for UDIMM (i.e. tCKSRX value)
0800 5h
1067 5h
1333 7h
1600 8h
1867 Ah
2133 Bh
443
4.4.11.15
RDIMMTIMINGCNTL2: RDIMMTIMINGCNTL2
RDIMMTIMINGCNTL2
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
4.4.11.16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
240
240
240
240
Bit
Attr
Default
31:8
RV
0h
Reserved
3:0
RW
5h
T_CKOFF
tCKOFF timing parameter:
Number of tCK required for both DCKE0 and DCKE1 to remain LOW before both
CK/CK# are driven Low
Minimum setting is 2.
Description
4.4.11.17
16
16
16
16
Device:
Device:
Device:
Device:
Attr
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
Default
244
244
244
244
Description
31:4
RV
0h
Reserved
3:0
RW
8h
TMRD_DDR3
DDR3 tMRD timing parameter. MRS to MRS minimum delay in number of DCLK.
MC_INIT_STAT_C: MC_INIT_STAT_C
State register per channel. Sets control signals static values. Power-up default is state
0x0 set by global reset.
BIOS should leave this register default to zero since the processor has Read/Write ODT
table logic to control ODT dynamically during IOSAV or NORMAL modes.
MC_INIT_STAT_C
Bus: 1
Bus: 1
Bus: 1
Bus: 1
Bit
Attr
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Offset:
Offset:
Offset:
Offset:
Default
280
280
280
280
Description
31:14
RV
0h
Reserved
7:6
RV
0h
Reserved
5:0
RW-L
0h
CKE ON OVERRIDE
When set, the bit overrides and asserts the corresponding CKE[5:0] output signal
during IOSAV mode. When cleared, the CKE pin is controlled by the IMC IOSAV
logic.
4.4.12
4.4.12.1
444
CORRERRCNT_0
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.12.2
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
104h
104h
104h
104h
Bit
Attr
Default
Description
31
RW1CS
0b
RANK 1 OVERFLOW
The corrected error count for this rank has been overflowed. Once set it can only
be cleared via a write from BIOS.
30:16
RWS-V
0000h
15
RW1CS
0b
RANK 0 OVERFLOW
The corrected error count for this rank has been overflowed. Once set it can only
be cleared via a write from BIOS.
14:0
RWS-V
0000h
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
108h
108h
108h
108h
Bit
Attr
Default
Description
31
RW1CS
0b
RANK 3 OVERFLOW
The corrected error count has crested over the limit for this rank. Once set it can
only be cleared via a write from BIOS.
30:16
RWS-V
0000h
15
RW1CS
0b
RANK 3 COR_ERR_CNT
The corrected error count for this rank.
RANK 2 OVERFLOW
The corrected error count has crested over the limit for this rank. Once set it can
only be cleared via a write from BIOS.
445
CORRERRCNT_1
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.4.12.3
Device:
Device:
Device:
Device:
Bit
Attr
Default
14:0
RWS-V
0000h
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
108h
108h
108h
108h
Description
RANK 2 COR_ERR_CNT
The corrected error count for this rank.
4.4.12.4
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
10Ch
10Ch
10Ch
10Ch
Bit
Attr
Default
Description
31
RW1CS
0b
RANK 5 OVERFLOW
The corrected error count has crested over the limit for this rank. Once set it can
only be cleared via a write from BIOS.
30:16
RWS-V
0000h
15
RW1CS
0b
14:0
RWS-V
0000h
RANK 5 COR_ERR_CNT
The corrected error count for this rank.
RANK 4 OVERFLOW
The corrected error count has crested over the limit for this rank. Once set it can
only be cleared via a write from BIOS.
RANK 4 COR_ERR_CNT
The corrected error count for this rank.
4.4.12.5
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
Bit
Attr
Default
31
RW1CS
0b
RANK 7 OVERFLOW
The corrected error count for this rank.
30:16
RWS-V
0000h
RANK 7 COR_ERR_CNT_7
The corrected error count for this rank.
15
RW1CS
0b
14:0
RWS-V
0000h
110h
110h
110h
110h
Description
RANK 6 OVERFLOW
The corrected error count has crested over the limit for this rank. Once set it can
only be cleared via a write from BIOS.
RANK 6 COR_ERR_CNT
The corrected error count for this rank.
446
CORRERRTHRSHLD_0
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
4.4.12.6
Bit
Attr
Default
31
RV
0h
30:16
RW
7FFFh
15
RV
0h
14:0
RW
7FFFh
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
11Ch
11Ch
11Ch
11Ch
Description
Reserved
RANK 1 COR_ERR_TH
The corrected error threshold for this rank that will be compared to the per rank
corrected error counter.
Reserved
RANK 0 COR_ERR_TH
The corrected error threshold for this rank that will be compared to the per rank
corrected error counter.
4.4.12.7
Bit
Attr
Default
31
RV
0h
30:16
RW
7FFFh
15
RV
0h
14:0
RW
7FFFh
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
120h
120h
120h
120h
Description
Reserved
RANK 3 COR_ERR_TH
The corrected error threshold for this rank that will be compared to the per rank
corrected error counter.
Reserved
RANK 2 COR_ERR_TH
The corrected error threshold for this rank that will be compared to the per rank
corrected error counter.
4.4.12.8
16
16
16
16
Bit
Attr
Default
31
RV
0h
Reserved
31
RV
0h
Reserved
30:16
RW
7FFFh
15
RV
0h
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
124h
124h
124h
124h
Description
RANK 5 COR_ERR_TH
The corrected error threshold for this rank that will be compared to the per rank
corrected error counter.
Reserved
447
CORRERRTHRSHLD_3
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
Bus: 1
Device:
4.4.12.9
Bit
Attr
Default
31
RV
0h
30:16
RW
7FFFh
15
RV
0h
14:0
RW
7FFFh
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
128h
128h
128h
128h
Description
Reserved
RANK 7 COR_ERR_TH
The corrected error threshold for this rank that will be compared to the per rank
corrected error counter.
Reserved
RANK 6 COR_ERR_TH
The corrected error threshold for this rank that will be compared to the per rank
corrected error counter.
448
Bit
Attr
Default
31:8
RV
0h
7:0
RW1C
00h
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
134h
134h
134h
134h
Description
Reserved
ERR_OVERFLOW_STAT
This 8 bit field is the per rank error over-threshold status bits. The organization is
as follows:
Bit 0: Rank 0
Bit 1: Rank 1
Bit 2: Rank 2
Bit 3: Rank 3
Bit 4: Rank 4
Bit 5: Rank 5
Bit 6: Rank 6
Bit 7: Rank 7
Note: The register tracks which rank has reached or exceeded the corresponding
CORRERRTHRSHLD threshold settings.
4.4.12.10
LEAKY_BKT_2ND_CNTR_REG: LEAKY_BKT_2ND_CNTR_REG
LEAKY_BKT_2ND_CNTR_REG
Bus: 1
Device: 16
Bus: 1
Device: 16
4.4.12.11
Function: 2
Function: 6
Offset: 138
Offset: 138
Bit
Attr
Default
Description
31:16
RW
0000h
LEAKY_BKT_2ND_CNTR_LIMIT
Secondary Leaky Bucket Counter Limit (2b per DIMM). This register defines
secondary leaky bucket counter limit for all 8 logical ranks within channel. The
counter logic will generate the secondary LEAK pulse to decrement the ranks
correctable error counter by 1 when the corresponding rank leaky bucket rank
counter roll over at the predefined counter limit. The counter increment at the
primary leak pulse from the LEAKY_BUCKET_CNTR_LO and
LEAKY_BUCKET_CNTR_HI logic.
Bit[31:30]: Rank 7 Secondary Leaky Bucket Counter Limit
Bit[29:28]: Rank 6 Secondary Leaky Bucket Counter Limit
Bit[27:26]: Rank 5 Secondary Leaky Bucket Counter Limit
Bit[25:24]: Rank 4 Secondary Leaky Bucket Counter Limit
Bit[23:22]: Rank 3 Secondary Leaky Bucket Counter Limit
Bit[21:20]: Rank 2 Secondary Leaky Bucket Counter Limit
Bit[19:18]: Rank 1 Secondary Leaky Bucket Counter Limit
Bit[17:16]: Rank 0 Secondary Leaky Bucket Counter Limit
0: the LEAK pulse is generated one DCLK after the counter roll over at 3.
1: the LEAK pulse is generated one DCLK after the primary LEAK pulse is asserted.
2: the LEAK pulse is generated one DCLK after the counter roll over at 1.
3: the LEAK pulse is generated one DCLK after the counter roll over at 2.
15:0
RW-V
0000h
LEAKY_BKT_2ND_CNTR
Per rank secondary leaky bucket counter (2b per rank)
Bit 15:14: rank 7 secondary leaky bucket counter
Bit 13:12: rank 6 secondary leaky bucket counter
Bit 11:10: rank 5 secondary leaky bucket counter
Bit 9:8: rank 4 secondary leaky bucket counter
Bit 7:6: rank 3 secondary leaky bucket counter
Bit 5:4: rank 2 secondary leaky bucket counter
Bit 3:2: rank 1 secondary leaky bucket counter
Bit 1:0: rank 0 secondary leaky bucket counter
449
4.4.12.12
140h
140h
140h
140h
147h
147h
147h
147h
Bit
Attr
RWSLB
0b
6:5
RV
0h
Reserved
4:0
RWSV
1fh
Description
450
Defau
lt
Offset:
Offset:
Offset:
Offset:
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
2
3
6
7
Offset:
Offset:
Offset:
Offset:
268h
268h
268h
268h
Attr
Default
Description
31:3
RV
0h
Reserved
RW
0b
dimm2_mode
Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM2 DQS select.
RW
0b
dimm1_mode
Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM1 DQS select.
RW
0b
dimm0_mode
Controls the DDRIO x4 (if set) / x8 (if cleared) DIMM0 DQS select.
4.5
4.5.1
Table 4-18. Intel Xeon Processor E5 Product Family Home Agent Registers Device: 14,
Function: 0)
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CC
BIST
HDR
MLT
RID
8h
88h
CLS
Ch
8Ch
10h
90h
14h
94h
TMBAR
SID
MAXLAT
SVID
MINGNT
INTRPIN
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPOINT
34h
B4h
38h
B8h
INTRLINE
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
451
4.5.2
4.5.2.1
Device: 14
Bit
Attr
Default
63:39
RV
0h
38:15
RO
000000
h
14:0
RV
0h
Function: 0
Offset: 10
Description
Reserved
Thermal Memory Map Base Address
This field corresponds to bits 31 to 15 of the base address TMBAR address space.
BIOS will program this register resulting in a base address for a 32KB block of
contiguous memory address space. This register ensures that a naturally aligned
32KB space is allocated within total addressable memory space.
Reserved
4.6
4.6.1
Table 4-19. PCU0 Register Map: Device: 10 Function: 0 0x00h - 0x104h (Sheet 1 of 2)
DID
VID
0h
PCISTS
PCICMD
4h
CCR
BIST
HDR
PLAT
MAXLAT
452
INTPIN
84h
RID
8h
Ch
PACKAGE_POWER_SKU_UNIT
8Ch
10h
PACKAGE_ENERGY_STATUS
90h
SVID
MINGNT
PACKAGE_POWER_SKU
CLSR
14h
SDID
80h
88h
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
Table 4-19. PCU0 Register Map: Device: 10 Function: 0 0x00h - 0x104h (Sheet 2 of 2)
40h
C0h
44h
48h
MEM_TRML_TEMPERATURE_REPORT
C4h
Package_Temperature
C8h
4Ch
CCh
50h
D0h
54h
PCU_REFERENCE_CLOCK
D4h
58h
P_STATE_LIMITS
D8h
5Ch
DCh
60h
E0h
MEM_ACCUMULATED_BW_CH_0
64h
MEM_ACCUMULATED_BW_CH_1
68h
E8h
MEM_ACCUMULATED_BW_CH_2
6Ch
ECh
MEM_ACCUMULATED_BW_CH_3
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
0h
80h
DID
VID
TEMPERATURE_TARGET
E4h
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
24h
SDID
SVID
A0h
CSR_DESIRED_CORES
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
INTL
3Ch
BCh
40h
C0h
44h
C4h
38h
MAXLAT
MINGNT
INTPIN
A4h
M_COMP
B8h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
453
SSKPD
C2C3TT
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
VID
PCISTS
PCICMD
CCR
BIST
HDR
RID
PLAT
CLSR
0h
80h
4h
84h
8h
88h
Ch
8Ch
10h
14h
1Ch
9Ch
28h
2Ch
30h
CAPPTR
34h
38h
MAXLAT
MINGNT
INTPIN
INTL
3Ch
40h
44h
DRAM_ENERGY_STATUS
DRAM_ENERGY_STATUS_CH0
DRAM_ENERGY_STATUS_CH1
DRAM_ENERGY_STATUS_CH2
DRAM_ENERGY_STATUS_CH3
48h
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
CCh
50h
D0h
54h
D4h
5Ch
DRAM_RAPL_PERF_STATUS
D8h
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
MCA_ERR_SRC_LOG
70h
78h
7Ch
ECh
F0h
74h
454
A0h
4Ch
58h
PKG_CST_ENTRY_CRITERIA_MASK
94h
98h
24h
SVID
90h
18h
20h
SDID
DRAM_POWER_INFO
F4h
THERMTRIP_CONFIG
F8h
FCh
VID
PCISTS
PCICMD
CCR
BIST
HDR
RID
PLAT
SDID
CLSR
SVID
0h
80h
4h
84h
8h
88h
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
30h
CAPPTR
MAXLAT
MINGNT
INTPIN
INTL
ACh
RESOLVED_CORES_MASK
B0h
34h
B4h
38h
B8h
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
78h
F8h
7Ch
FCh
4.6.2
PCU0 Registers
4.6.2.1
MEM_TRML_TEMPERATURE_REPORT:
MEM_TRML_TEMPERATURE_REPORT
This register is used to report the thermal status of the memory.
The channel max temperature field is used to report the maximal temperature of all
ranks.
455
MEM_TRML_TEMPERATURE_REPORT
Bus: 1
Device: 10
Function: 0
4.6.2.2
Offset: 60
Bit
Attr
Default
Description
31:24
RO-V
00h
23:16
RO-V
00h
15:8
RO-V
00h
7:0
RO-V
00h
MEM_ACCUMULATED_BW_CH_[0:3]: MEM_ACCUMULATED_BW_CH_0
This register contains a measurement proportional to the weighted DRAM BW for the
channel (including all ranks). The weights are configured in the memory controller
channel register PM_CMD_PWR.
MEM_ACCUMULATED_BW_CH_[0:3]
Bus: 1
Device: 10
Function: 0
4.6.2.3
Bit
Attr
Default
31:0
RO-V
000000
00h
Data
The weighted BW value is calculated by the memory controller based on the
following formula:
Num_Precharge * PM_CMD_PWR[PWR_RAS_PRE] +
Num_Reads * PM_CMD_PWR[PWR_CAS_R] +
Num_Writes * PM_CMD_PWR[PWR_CAS_W]
456
Attr
Default
Function: 0
Offset: 84
Description
63:55
RV
0h
Reserved
54:48
RO-V
2Fh
47
RV
0h
Reserved
46:32
RO-V
Varies
PACKAGE_POWER_SKU
Bus: 1
Device: 10
4.6.2.4
Bit
Attr
Default
31
RV
0h
30:16
RO-V
Varies
15
RV
0h
14:0
RO-V
Varies
Function: 0
Offset: 84
Description
Reserved
PACKAGE_MIN_POWER: The minimum allowed power limit for a processor that
could be used in the PACKAGE_POWER_LIMIT register. The value is in the units
identified in POWER_UNIT field in PACKAGE_POWER_SKU_UNIT register.
Reserved
PACKAGE_TDP_POWER: The packages Thermal Design Power allowed for this
processor. The value is in the units identified in POWER_UNIT field in
PACKAGE_POWER_SKU_UNIT register.
4.6.2.5
Attr
Default
Function: 0
Offset: 8C
Description
31:20
RV
0h
19:16
RO-V
0Ah
Reserved
15:13
RV
0h
12:8
RO-V
10h
7:4
RV
0h
Reserved
3:0
RO-V
3h
POWER_UNIT: This field defines the unit of power used by energy fields in *_
CSRs.
The actual power unit is calculated using the formula:
Power Unit = 1 / (2 ^ POWER_UNIT) W
The default value of 3h translates to a power unit of 1/8 W.
TIME_UNIT: This field defines unit of time used by time window fields in the *_
CSRs.
The actual time unit is calculated using the formula:
Time Unit = 1 / (2 ^ TIME_UNIT) seconds
The default value of 0Ah translates to a time unit of 976 us
Reserved
ENERGY_UNIT: This field defines the unit of energy used by energy fields in
*_ENERGY_STATUS CSRs.
The actual energy unit is calculated using the formula:
Energy Unit = 1 / (2 ^ ENERGY_UNIT) J
The default value of 10h translates to a energy unit of 15.3 uJ
457
PACKAGE_ENERGY_STATUS
Bus: 1
Device: 10
4.6.2.6
Function: 0
Offset: 90
Bit
Attr
Default
Description
31:0
RO-V
000000
00h
Package_Temperature: Package_Temperature
Package temperature in degrees (C). This field is updated by FW.
Package_Temperature
Bus: 1
Device: 10
Bit
4.6.2.7
Attr
Function: 0
Default
31:8
RV
0h
7:0
RO-V
00h
Offset: C8
Description
Reserved
Temperature
Package temperature in degrees (C).
4.6.2.8
Bit
Attr
Default
31:0
RO-V
000000
00h
Function: 0
Offset: D4
Description
TIME_VAL:Time Value
Number of Cycles
458
P_STATE_LIMITS
Bus: 1
Device: 10
4.6.2.9
Function: 0
Offset: D8
Bit
Attr
Default
Description
31
RW-KL
0b
Lock
This bit will lock all settings in this register.
30:16
RV
0h
Reserved
15:8
RW-L
00h
P-State Offset
HW P-State control on the relative offset from P1. The offset field determines the
number of bins to drop P1 (dynamically).
7:0
RW-L
FFh
P-State Limitation
This field indicates the maximum frequency limit allowed during run-time.
Attr
Function: 0
Default
Offset: E4
Description
31:28
RV
0h
Reserved
27:24
RW-V
0h
TCC Activation Offset: This field indicates to the processor the offset from the
factory set TCC activation temperature at which the Thermal Control Circuit (TCC)
must be activated. TCC will be activated at a temp (TCC Activation Temperature TCC Activation Offset). Default value is 0 causing TCC to activate at TCC Activation
temperature. This field is valid only when PLATFORM_INFO[30] is set indicating
feature availability
23:16
RO-V
Varies
TCC Activation Temperature: This is the factory set temperature at which the
Thermal Control Circuit (TCC) will assert the PROCHOT# signal and activate the
Adaptive Thermal monitor.
15:8
RO-V
Varies
7:0
RV
0h
Reserved
4.6.3
PCU1 Registers
4.6.3.1
4.6.3.2
Device: 10
Bit
Attr
Default
63:0
RWS
000000
000000
0000h
Function: 1
Offset: 6C
Description
Scratchpad Data
4 WORDs of data storage.
459
4.6.3.3
Device: 10
Attr
Function: 1
Default
31:12
RV
0h
11:0
RW
32h
Offset: 74
Description
Reserved
Pop Down Initialization Value
Value in micro-seconds.
460
Function: 1
Offset: A4
Bit
Attr
Default
31
RWS-KL
0b
Lock
Lock:
once written to a 1, changes to this register cannot be done. Cleared only by a
power-on reset
30
RWS-L
0b
SMT Disable
Disable simultaneous multithreading in all cores if this bit is set to 1.
Reserved
29:16
RV
0h
15:0
RWS-L
0000h
Description
4.6.4
PCU2 Registers
4.6.4.1
PACKAGE_RAPL_PERF_STATUS
This register is used by the microcode to report Package Power limit violations in the
Platform PBM.
PACKAGE_RAPL_PERF_STATUS
Bus: 1
Device: 10
Bit
4.6.4.2
Attr
Function: 2
Default
63:32
RV
0h
31:0
RO-V
000000
00h
Offset: 88
Description
Reserved
Power Limit Throttle Counter
Reports the number of times the Power limiting algorithm had to clip the power
limit due to hitting the lowest power state available.
Accumulated PACKAGE throttled time
DRAM_POWER_INFO
Defines allowed DRAM power and timing parameters.
The microcode will update the contents of this register.
The minimal time window for the DRAM RAPL is shared with all the other RAPLs; it can
be found in the PWR_LIMIT_MISC_INFO register.
DRAM_POWER_INFO
Bus: 1
Device: 10
Function: 2
Bit
Attr
Default
63
RW-KL
0b
Lock
Lock bit to lock the Register
Reserved
62:55
RV
0h
54:48
RW-L
28h
Offset: 90
Description
47
RV
0h
46:32
RW-L
0258h
31
RV
0h
30:16
RW-L
0078h
15
RV
0h
14:0
RW-L
0118h
Reserved
Maximal Package Power
The maximal power setting allowed for DRAM. Higher values will be clamped to
this value. The maximum setting is typical (not guaranteed).
Reserved
Minimal DRAM Power
The minimal power setting allowed for DRAM. Lower values will be clamped to this
value. The minimum setting is typical (not guaranteed).
Reserved
Spec DRAM Power
The Spec power allowed for DRAM. The TDP setting is typical (not guaranteed).
461
4.6.4.3
DRAM_ENERGY_STATUS
DRAM energy consumed by all the DIMMS in all the Channels. The counter will wrap
around and continue counting when it reaches its limit.
The data is updated by the microcode and is Read Only for all SW.
DRAM_ENERGY_STATUS
Bus: 1
Device: 10
Bit
4.6.4.4
Attr
Function: 2
Default
63:32
RV
0h
31:0
RO-V
000000
00h
Offset: A0
Description
Reserved
Energy Value
Energy Value
462
Bit
Attr
Default
63:32
RV
0h
31:0
RO-V
000000
00h
Function: 2
Reserved
Energy Value
Energy Value
4.6.4.5
4.6.4.6
Attr
Function: 2
Default
63:16
RV
0h
15:0
RO-V
0000h
Offset: D8
Description
Reserved
Power Limit Violation Counter
Reports the number of times the Power limiting algorithm had to clip the power
limit due to hitting the lowest power state available.
4.6.4.7
Function: 2
Offset: EC
Bit
Attr
Default
Description
31
RWS-V
0b
CATERR
External error: This socket sensed a CATERR that it did not originate.
It is or(bit 30, bit29); functions as a Valid bit for the other two package conditions.
It has no effect when a local core is associated with the error.
30
RWS-V
0b
IERR
External error: This socket sensed an external CATERR and determined it was
IERR.
29
RWS-V
0b
MCERR
External error: This socket sensed an external CATERR and determined it was
MCERR.
Reserved
28:8
RV
0h
7:0
RWS-V
00h
Core Mask
Bit i is on if core i asserted an error.
Attr
Default
31:4
RV
0h
Function: 2
Offset: F8
Description
Reserved
463
THERMTRIP_CONFIG
Bus: 1
Device: 10
Bit
Attr
Default
RW
0b
Function: 2
Offset: F8
Description
4.6.5
PCU3 Registers
4.6.5.1
4.7
Function: 3
Offset: B0
Attr
Default
Description
31:25
RV
0h
Reserved
24
RO-V
0b
SMT Capability
Enabled threads in the package.
0b 1 thread
1b 2 threads
23:16
RO-V
0h
Core Mask
Vector of enabled IA cores in the package.
15:10
RV
0h
Reserved
9:8
RO-V
00b
Thread Mask
Thread Mask indicates which threads are enabled in the core. The LSB is the
enable bit for Thread 0, whereas the MSB is the enable bit for Thread 1.
7:0
RO-V
00h
Core Mask
The resolved IA core mask contains the functional and non-defeatured IA cores.
The mask is indexed by logical ID. It is normally contiguous, unless BIOS
defeature is activated on a particular core.
Processor Microcode will read this mask in order to decide on BSP and APIC IDs.
4.7.1
CSR Group
This section apply to the processor performance Utility Box Semaphore and Scratchpad
registers
Table 4-23. Processor Utility BOX Registers Device 11, Function 0 (Sheet 1 of 2)
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
464
HDR
PLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
Table 4-23. Processor Utility BOX Registers Device 11, Function 0 (Sheet 2 of 2)
14h
SDID
MAXLAT
SVID
MINGNT
94h
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
INTPIN
CPUNODEID
IntControl
GIDNIDMAP
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
CoreCount
60h
E0h
UBOXErrSts
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
Table 4-24. Scratchpad and Semaphore Registers (Device 11, Function 3) (Sheet 1 of 2)
DID
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
SDID
PLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
SVID
CAPPTR
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
34h
B4h
465
Table 4-24. Scratchpad and Semaphore Registers (Device 11, Function 3) (Sheet 2 of 2)
MAXLAT
MINGNT
INTPIN
INTL
38h
B8h
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
58h
D4h
SMICtrl
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
74h
F4h
78h
F8h
7Ch
FCh
4.7.2
4.7.2.1
466
Attr
Device: 11
Function: 0
Default
Offset: 40
Description
31:16
RV
0h
15:13
RW-LB
000b
12:10
RW-LB
000b
9:8
RV
0h
7:5
RW-LB
000b
4:3
RV
0h
2:0
RW-LB
000b
Reserved
Reserved
NodeId of the lock master
NodeId of the lock master
Reserved
NodeId of the local register
Node Id of the local Socket
4.7.2.2
Device: 11
Function: 0
Offset: 48
Attr
Default
Description
31:19
RV
0h
Reserved
18
RW-LB
0b
17
RW-LBV
0b
16
RW-LB
0b
15:11
RV
0h
Reserved
10:8
RW-LB
000b
RV
0h
6:4
RW-LB
000b
Reserved
3:2
RV
0h
Reserved
RW-LB
0b
RW-LB
0b
467
4.7.2.3
4.7.2.4
Attr
Device: 11
Function: 0
Default
Offset: 54
Description
31:24
RV
0h
23:21
RW-LB
000b
Reserved
Node Id 7
NodeId for group id 7
20:18
RW-LB
000b
Node Id 6
Node Id for group 6
17:15
RW-LB
000b
Node Id 5
Node Id for group 5
14:12
RW-LB
000b
Node Id 4
Node Id for group id 4
11:9
RW-LB
000b
Node Id 3
Node Id for group 3
8:6
RW-LB
000b
Node Id 2
Node Id for group Id 2
5:3
RW-LB
000b
Node Id 1
Node Id for group Id 1
2:0
RW-LB
000b
Node Id 0
Node Id for group 0
4.7.2.5
Device: 11
Function: 0
Bit
Attr
Default
31:5
RV
0h
Reserved
4:0
RO-V
0h
Core Count
Reflection of the LTCount2 uCR
Offset: 60
Description
468
Device: 11
Function: 0
Offset: 64
Bit
Attr
Default
Description
31:7
RV
0h
Reserved
RWS
0b
Unsupported Mask
Mask SMI generation on receiving unsupported opcodes.
RWS
0b
Poison Mask
Mask SMI generation on receiving poison in UBOX.
RW-V
0b
UBOXErrSts
Bus: 1
Device: 11
Function: 0
Offset: 64
Bit
Attr
Default
Description
RW-V
0b
RV
0h
Reserved
RW-V
0b
RW-V
0b
4.7.3
4.7.3.1
4.7.3.2
Device: 11
Function: 3
Offset: D0
Bit
Attr
Default
Description
31
RW-LB
0b
Valid
Indicates whether the bus numbers have been initialized or not
30:16
RV
0h
Reserved
15:8
RW-LB
00h
7:0
RW-LB
00h
Device: 11
Attr
Default
Function: 3
Offset: D8
Description
31:26
RV
0h
Reserved
25
RW
0b
24
RW
0b
23:20
RV
0h
Reserved
19:0
RW
00000h
469
4.8
4.8.1
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
18h
98h
1Ch
9Ch
20h
24h
28h
SDID
SVID
2Ch
30h
CAPPTR
34h
INTL
3Ch
38h
MAXLAT
MINGNT
INTPIN
HaPerfmonAddrMatch0
40h
HaPerfmonAddrMatch1
44h
HaPerfmonOpcodeMatch
48h
PmonCntr_0
PmonCntr_1
PmonCntr_2
PmonCntr_3
PmonCntr_4
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
C8h
4Ch
CCh
50h
D0h
54h
PmonCntr_Fixed
D4h
58h
PmonCntrCfg_0
D8h
5Ch
PmonCntrCfg_1
DCh
60h
PmonCntrCfg_2
E0h
64h
PmonCntrCfg_3
E4h
68h
PmonCntrCfg_4
E8h
6Ch
PmonDbgCtrl
ECh
70h
74h
470
A0h
F0h
PmonUnitCtrl
F4h
78h
F8h
7Ch
FCh
4.8.2
4.8.2.1
4.8.2.2
Device:
Device:
Device:
Device:
8
9
14
16
Bit
Attr
Default
63:48
RV
0h
47:0
RW-V
0000000
00000h
Function:
Function:
Function:
Function:
2
2
1
0, 1,4,5
Offset:
Offset:
Offset:
Offset:
A0,
A0,
A0,
A0,
A8,
A8,
A8,
A8,
B0,
B0,
B0,
B0,
B8,
B8,
B8,
B8,
C0
C0
C0
C0
Description
Reserved
Counter Value
This is the current value of the counter.
4.8.2.3
Attr
Device:
Device:
Device:
Device:
16
16
16
16
Function:
Function:
Function:
Function:
0
1
4
5
Default
63:48
RV
0h
47:0
RW-V
000000
000000
h
Offset:
Offset:
Offset:
Offset:
D0
D0
D0
D0
Description
Reserved
Counter Value
This is the current value of the counter.
PmonCntrCfg
Bus: 1
Bus: 1
Bus: 1
Bus: 1
Device:
Device:
Device:
Device:
8
9
14
16
Function:
Function:
Function:
Function:
2
2
1
0, 1,4,5
Offset:
Offset:
Offset:
Offset:
D8,
D8,
D8,
D8,
DC,
DC,
DC,
DC,
E0,
E0,
E0,
E0,
E4,
E4,
E4,
E4,
E8
E8
E8
E8
Bit
Attr
Default
Description
31:24
RW-V
00h
Threshold
This field is compared directly against an incoming event value for events that
can increment by 1 or more in a given cycle. Since the widest event from the
UnCore is 7bits (queue occupancy), bit 31 is Reserved. The result of the
comparison is effectively a 1 bit wide event, i.e., the counter will be
incremented by 1 when the comparison is true (the type of comparison depends
on the setting of the invert bit - see bit 23 below) no matter how wide the
original event was. When this field is zero, threshold comparison is disabled and
the event is passed without modification.
23
RW-V
0h
Invert
This bit indicates how the threshold field will be compared to the incoming
event. When 0, the comparison that will be done is threshold >= event. When
set to 1, the comparison that will be done is inverted from the case where this
bit is set to 0, i.e., threshold < event. The invert bit only works when Threshold
!= 0. So, if one would like to invert a non-occupancy event (like LLC Hit), one
needs to set the threshold to 1.
471
PmonCntrCfg
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.8.2.4
8
9
14
16
Function:
Function:
Function:
Function:
2
2
1
0, 1,4,5
Offset:
Offset:
Offset:
Offset:
D8,
D8,
D8,
D8,
DC,
DC,
DC,
DC,
E0,
E0,
E0,
E0,
E4,
E4,
E4,
E4,
E8
E8
E8
E8
Bit
Attr
Default
Description
22
RW-V
0h
Counter Enable
This field is the local enable for the PerfMon Counter. This bit must be asserted
in order for the PerfMon counter to begin counting the events selected by the
'event select', 'unit mask', and 'internal' bits (see the fields below). There is one
bit per PerfMon Counter. Note that if this bit is set to 1 but the Unit Control
Registers have determined that counting is disabled, then the counter will not
count.
21:20
RV
0h
Reserved
Software must write to 0 else behavior is undefined.
19
RV
0h
Reserved
18
RW-V
0h
Edge Detect
Edge Detect allows one to count either 0 to 1 or 1 to 0 transitions of a given
event. For example, we have an event that counts the number of cycles in L0s
mode in QPI. By using edge detect, one can count the number of times that we
entered L0s mode (by detecting the rising edge).
Edge detect only works in conjunction with thresholding. This is true even for
events that can only increment by 1 in a given cycle (like the L0s example
above). In this case, one should set a threshold of 1. One can also use Edge
Detect with queue occupancy events. For example, if one wanted to count the
number of times when the TOR occupancy was larger than 5, one would select
the TOR occupancy event with a threshold of 5 and set the Edge Detect bit.
Edge detect can also be used with the invert. This is generally not particularly
useful, as the count of falling edges compared to rising edges will always on
differ by 1.
17
WO
0h
Reserved
16
WO
0h
Reserved
15:8
RW-V
00h
Unit Mask
This mask selects the sub-events to be selected for creation of the event. The
selected sub-events are bitwise OR-ed together to create event. At least one
sub-event must be selected otherwise the PerfMon event signals will not ever
get asserted. Events with no sub-events listed effectively have only one subevent -- bit 8 must be set to 1 in this case.
7:0
RW-V
00h
Event Select
This field is used to decode the PerfMon event which is selected.
PmonUnitCtrll
Bus: 1
Bus: 1
Bus: 1
Bus: 1
472
Device:
Device:
Device:
Device:
Device:
Device:
Device:
Device:
8
9
14
16
Function:
Function:
Function:
Function:
2
2
1
0, 1,4,5
Offset:
Offset:
Offset:
Offset:
F4
F4
F4
F4
Bit
Attr
Default
Description
31:18
RV
0h
Reserved
17
RW
0h
Reserved
16
RW
0h
Freeze Enable
This bit controls what the counters in the unit will do when they receive a freeze
signal. When set, the counters will be allowed to freeze. When not set, the
counters will ignore the freeze signal. For freeze to be enabled for a given unit,
all of the unit control registers must have this bit set.
15:9
RV
0h
Reserved
PmonUnitCtrll
Bus: 1
Bus: 1
Bus: 1
Bus: 1
4.8.2.5
Device:
Device:
Device:
Device:
8
9
14
16
Function:
Function:
Function:
Function:
2
2
1
0, 1,4,5
Offset:
Offset:
Offset:
Offset:
F4
F4
F4
F4
Bit
Attr
Default
Description
RW-V
0h
Freeze Counters
This bit is written to when the counters should be frozen. If this bit is written to
and freeze is enabled, the counters in the unit will stop counting. To freeze the
counters, this bit need only be set by one of the unit control registers.
7:2
RV
0h
Reserved
WO
0h
Reset Counters
When this bit is written to, the counters data fields will be reset. The
configuration values will not be reset. To reset the counters, this bit need only be
set by one of the unit control registers.
WO
0h
4.8.2.6
Bit
Attr
Default
31:6
RWS
000000
0h
5:0
RV
00h
Function: 1
Offset: 40
Description
4.8.2.7
Attr
Default
31:14
RV
0h
13:0
RWS
0000h
Function: 1
Offset: 44
Description
Reserved
High Physical Address of a cache line
This contains 14 bits of physical address [45:32] of a cache line. The high 14 bits
address of a architectural event address match are in the register.
473
HaPerfmonOpcodeMatch
Bus: 1
Device: 14
Function: 1
Offset: 48
Bit
Attr
Default
Description
31:6
RV
0h
Reserved
5:0
RWS
0h
4.9
4.9.1
VID
0h
80h
PCISTS
PCICMD
4h
84h
CCR
BIST
HDR
PLAT
SDID
MAXLAT
474
RID
8h
88h
CLSR
Ch
8Ch
10h
90h
14h
94h
SVID
MINGNT
INTPIN
18h
98h
1Ch
9Ch
20h
A0h
24h
A4h
28h
A8h
2Ch
ACh
30h
B0h
CAPPTR
34h
B4h
38h
B8h
INTL
3Ch
BCh
40h
C0h
44h
C4h
48h
C8h
4Ch
CCh
50h
D0h
54h
D4h
58h
D8h
5Ch
DCh
60h
E0h
64h
E4h
68h
E8h
6Ch
ECh
70h
F0h
F4h
78h
F8h
7Ch
FCh
4.10
MISC Registers
4.10.1
Function: 3
Function: 3
Bit
Attr
Default
31:28
RWS-LV
0b
TL0sDriveRemote
27:26
RV
0b
Reserved
Offset: 190
Offset: 190
Description
25:24
RWS-LV
0b
TL0sSleepMinRemote
TL0S_SLEEP_MIN_REMOTE
If # of links supported is greater than 0 then
Link Select must always be used to display the current read value for this field.
There is a write dependency for this field based on the value of Can Control
Multiple Links?
If Can Control Multiple Links? = 0 then Link Select must be used to only write to
the selected Link.
If Can Control Multiple Links? = 1 then every Link selected in Link Control will
receive the written value.
Intel QPI Behavior
TL0sSleepMinRemote and TL0sWakeRemote values are captured from TS
sequence and updated in this CSR, S/W or BIOS can update these values as a
work-around.
It means S/W or BIOS will overwrite whatever values are captured from TS
sequence. On subsequent entry to InbandReset causes these values to be
overwritten again by H/W with values captured from TS sequence. To make S/W
or BIOS workaround permanent we need another control bit to tell H/W not to
update this CSR any more.
This field is decoded in the following way.
00: 32 UI
01: 48 UI
10: 64 UI
11: 96 UI
H/W loads this CSR with captured values from TS sequence if bit15 is not set.
S/W or BIOS can always write to these CSRs, whenever S/W or BIOS is written to
this CSR it also need to set bit15 to make these values permanent.
TL0s_ignore_remote_values(bit15)
When this bit is set, H/W ignores values received in TS sequence and uses values
programmed by S/W or BIOS.
23:22
RV
0b
Reserved
475
QPIREUT_PM_R0
Bus: 1
Device: 8
Bus: 1
Device: 9
Bit
476
Attr
Function: 3
Function: 3
Offset: 190
Offset: 190
Default
Description
21:16
RWS-LV
0h
TL0sWakeRemote
TL0S_WAKE_REMOTE
Link Select must always be used to display the current read value for this field.
There is a write dependency for this field based on the value of Can Control
Multiple Links?
If Can Control Multiple Links? = 0 then Link Select must be used to only write to
the selected Link.
If Can Control Multiple Links? = 1 then every Link selected in Link Control will
receive the written value.
Intel QPI Behavior
TL0sSleepMinRemote and TL0sWakeRemote values are captured from TS
sequence and updated in this CSR, S/W or BIOS can update these values as a
work-around.
It means S/W or BIOS will overwrite whatever values are captured from TS
sequence. On subsequent entry to InbandReset causes these values to be
overwritten again by H/W with values captured from TS sequence. To make S/W
or BIOS workaround permanent we need another control bit to tell H/W not to
update this CSR any more.
This field is at 16 UI granularity and the value of this field is (count + 1)*16 UI
H/W loads this CSR with captured values from TS sequence if bit15 is not set.
S/W or BIOS can always write to these CSRs, whenever S/W or BIOS is written to
this CSR it also need to set bit15 to make these values permanent.
TL0s_ignore_remote_values(bit15)
When this bit is set, H/W ignores values received in TS sequence and uses values
programmed by S/W or BIOS.
15:12
RWS-L
4h
TL0sDrive
11:10
RWS-L
1h
TL0sSleepMin
TL0S_SLEEP_MIN
If # of links supported is greater than 0 then
Link Select must always be used to display the current read value for this field.
There is a write dependency for this field based on the value of Can Control
Multiple Links?
If Can Control Multiple Links? = 0 then Link Select must be used to only write to
the selected Link.
If Can Control Multiple Links? = 1 then every Link selected in Link Control will
receive the written value.
Note: Intel QPI Specific Field
Minimum time remote TX on a port initiating L0s entry should stay in L0s. This
corresponds to the time required by local Rx to respond to L0s exit signal by
remote port.
This field is decoded in the following way.
00: 32 UI
01: 48 UI
10: 64 UI
11: 96 UI
9:6
RV
0b
Reserved
QPIREUT_PM_R0
Bus: 1
Device: 8
Bus: 1
Device: 9
Bit
5:0
4.10.2
Attr
RWS-L
Function: 3
Function: 3
Offset: 190
Offset: 190
Default
12h
Description
TL0sWake
TL0S_WAKE
If # of links supported is greater than 0 then
Link Select must always be used to display the current read value for this field.
There is a write dependency for this field based on the value of Can Control
Multiple Links?
If Can Control Multiple Links? = 0 then Link Select must be used to only write to
the selected Link.
If Can Control Multiple Links? = 1 then every Link selected in Link Control will
receive the written value.
Intel QPI Behavior
Local L0s Wake-up time the remote agent must not violate. Set by firmware on
both link ports prior to entering L0s.
This field is at 16 UI granularity and the value of this field is (count + 1)*16 UI
A value is 0 indicates that L0s is not supported on the local agent.
FWDC_LCPKAMP_CFG
FWDC_LCPKAMP_CFG
Bus: 1
Device: 8
Bus: 1
Device: 9
Bit
Attr
Default
31:17
RV
0h
Reserved
Function: 4
Function: 4
Offset: 390
Offset: 390
Description
16
RWS-L
1h
fwdc lcampen
Enable signal for LC peak amplifier. When this path is enabled, the other parallel
forwarded clock path is disabled
0 = LC peak amplifier is disabled
1 = LC peak amplifier is enabled
15:13
RV
0h
Reserved
12:8
RWS-L
8h
fwdc lcampcapctl
LC peak amplifier capacitor load control signals.
8 Gbps: 0x8 (default)
6.4 Gbps: 0x1F
7:6
RV
0h
Reserved
5:4
RWS-L
0h
fwdc lcampfbkctl
LC peak amplifier miller cap control signals.
3:2
RWS-L
0h
fwdc lcampibiasctl
LC peak amplifier pmos load control signals.
1:0
RWS-L
0h
fwdc lcamppbiasctl
LC peak amplifier tail current bias control signals
477
478