Chapter2 Clocks Resets-04
Chapter2 Clocks Resets-04
Delayed
Reset
rst_n
Vcc
master_rst_n
rst_dly_n
D
final_rst_n
Reset distribution
buffer tree
clk
rst_n
Delay
rst_dly_n
final_rst_n
Filtered
Reset
Glitch
Filter
2.6.6
Asynchronous Reset are susceptible to glitches, that means any input wide enough
to meet the minimum reset pulse width for a ip-op will cause the ip-op to reset.
If the reset line is subject to glitches, this can be a real problem. A design may not
have a very high frequency sampling clock to detect small glitch on the reset; this
section presents an approach that will work to lter out glitches [30]. This solution
requires a digital delay to lter out small glitches. The reset input pad should also
be a Schmidt triggered pad to help with glitch ltering. Figure 2.41 shows the reset
glitch lter circuit and the timing diagram.
In order to add the delay, some vendors provide a delay hard macro that can be
hand instantiated. If such a delay macro is not available, the designer could manually
instantiate the delay into the synthesized design after optimization. A second
approach is to instantiated a slow buffer in a module and then instantiated that module
multiple times to get the desired delay. Many variations could expand on this concept.
Since this approach uses delay lines, one of the disadvantages is that this delay
would vary with temperature, voltage and process. Care must be taken to make sure
that the delay meets the design requirements across all PVT corners.
2.7
Difference in clock signal arrival times across the chip is called clock skew. It is
a fundamental design principle that timing must satisfy register setup and hold
time requirements. Both data propagation delay and clock skew are parts of these
43
CLKi
CLKj
CLK
CLK
CLKi
CLKj
clock skew
Tci Tc j
where Tci and Tcj are the clock delays from the clock source to the Flops Fi and Fj,
respectively.
2.7.1
The problem of short data paths in the presence of clock skew is very similar to
hold-time violations in ip-ops. The problem arises when the data propagation
delay between two adjacent ip-ops is less than the clock skew.
44
D1
Q2
U2
U1
CLK1
CLK2
CLK
CLK
CLK1
CLK2
D1
Q1
Expected
2.7.2
As mentioned earlier, clock skew and short-path problems emerge when the data
propagation path delay between two sequentially adjacent ip-ops is less than the
clock skew between the two. Figure 2.44 shows the general diagram of the delay
blocks in a sample circuit [33].
The delays in Fig. 2.44 are as follows:
s Tcq1: The clock to out delay of the rst ip-op
s Trdq1: The propagation delay from the output of the rst ip-op to the input of
the second one
s Tck2: The clock arrival time at the second ip-op minus the clock arrival time at
the rst ip-op
45
Trdq1
D1
Routing Delay
Tcq1
CLK
CLK
CLK2
CLK
Tck2
Routing Delay
CLK
DATA2
CLK2
T1
A
SK
B
SK
C
SK
CASE A: NO PROBLEM SK < T1 - H
CASE B: PROBLEM SK > T1 - H
CASE C: PROBLEM SK > T1 - H
Q2
46
D1
CLK
Q2
CLK
CLK
Therefore, in order to identify the paths with the problem, the user needs to extract
the clock skew (e.g. Tck2) and the short-path delays (e.g. Tcq1 + Trdq1 - THOLD2).
2.7.3
Reducing the Clock skew to the minimum is the best approach to reduce the risk of
short-path problems. Maintaining the clock skew at a value less than the smallest
Flop-to-Flop delay in the design will improve the robustness of the design against
any short-path problems.
The following sections are a few well-known design techniques to make designs
more robust against clock skew.
2.7.3.1
As Shown in Fig. 2.44, by increasing the Routing Delay in the data path (Trdq1) that
eventually increases the total delay of the data path to a value greater than the clock
skew, will eliminate the short path problem.
The amount of the inserted delay in the data path should be large enough so that
the data path delay becomes sufciently greater than the clock skew.
2.7.3.2
Clock Reversing
Clock reversing is another approach to get around the problem of short data paths
and clock skew. In this technique Clock is applied in the reverse direction with
respect to data so that clock skew is automatically eliminated.
The receiving Flop will clock in the transmitting (source) value before the transmitting register receives its clock edge. Figure 2.46 shows a simple example of
implementing the clock reversing approach.
47
U3
CLK
U2
CLK
U1
CLK
CLK
1
CLK
Q
2
CLK
D
3
CLK
Q
4
CLK
As shown when sufcient delay is inserted, the receiving Flop will receive the
active-clock edge before the source Flop. This improves the Hold time at the expense
of Setup Time.
The clock reversing method will not be effective in circular structures such as
Johnson counters and Linear Feedback Shift Registers (LFSRs), because it is not
possible to dene the Sink Flop explicitly. Figure 2.47 shows an example of a circular
structure with clock reversing interconnection. As shown, short-path problem exists
between ip-ops U1 and U3.
2.7.3.3
48
1
CLK
D
2
CLK
D
3
CLK
4
CLK
Phase1
Phase2
Phase1
Phase2
As shown this method provides a short path-clock skew margin of about one half
clock cycle for clock skew.
References
49
CLK
CLK Q
CLK Q
2.7.3.4
Techniques described in the previous section are more on design techniques that
may be planned much before the nal project phase. Of course alternative to the
above, Designers may choose to balance the trace length for low skew clock drivers.
Apart from merely providing equal traces on all clock nets, the same termination
strategy should be used on each trace by placing the same load at the end of the line.
This would make sure trace lengths are properly balanced.
Below are some of the guidelines that should be followed:
1.
2.
3.
4.
5.
Pay close attention to the specications for input-to-output delay on the drivers.
Use the same drivers at every level of the clock hierarchy.
Balance the nominal trace delays at each level.
Use the same termination strategy on each line.
Balance the loading on each line, even if that means adding dummy capacitors to
one branch to balance out loads on the other branches.
References
1. Mohit Arora, Prashant Bhargava, Amit Srivastava, Optimization and Design Tips for FPGA/
ASIC(How to make the best designs), DCM Technologies, SNUG India, 2002
2. Application Note, ASIC design guidelines, Atmel Corporation, 1999
3. Cummings CE, Sunburst Design, Inc.; Mills D, LCDM Engineering (2002) Synchronous resets?
Asynchronous resets? I am so confused! How will I ever know which to use? SNUG, San Jose
4. Application Note, Clock skew and short paths timing, Actel Corporation, 2004