lm311 PDF
lm311 PDF
lm311 PDF
1 Fast Response Time: 165 ns The LM111, LM211, and LM311 devices are single
high-speed voltage comparators. These devices are
Strobe Capability designed to operate from a wide range of power-
Maximum Input Bias Current: 300 nA supply voltages, including 15-V supplies for
Maximum Input Offset Current: 70 nA operational amplifiers and 5-V supplies for logic
Can Operate From Single 5-V Supply systems. The output levels are compatible with most
TTL and MOS circuits. These comparators are
Available in Q-Temp Automotive capable of driving lamps or relays and switching
High-Reliability Automotive Applications voltages up to 50 V at 50 mA. All inputs and outputs
Configuration Control and Print Support can be isolated from system ground. The outputs can
drive loads referenced to ground, VCC+ or VCC. Offset
Qualification to Automotive Standards balancing and strobe capabilities are available, and
On Products Compliant to MIL-PRF-38535, the outputs can be wire-OR connected. If the strobe
All Parameters Are Tested Unless Otherwise is low, the output is in the off state, regardless of the
Noted. On All Other Products, Production differential input.
Processing Does Not Necessarily Include Testing
of All Parameters. Device Information(1)
PART NUMBER PACKAGE BODY SIZE
2 Applications LM111FK LCCC (20) 8.89 mm 8.89 mm
LM111JG CDIP (8) 9.60 mm 6.67 mm
Desktop PCs
LM311PS SO (8) 6.20 mm 5.30 mm
Body Control Modules
LM211D
White Goods SOIC (8) 4.90 mm 3.91 mm
LM311D
Building Automation
LM211P
Oscillators PDIP (8) 9.81 mm 6.35 mm
LM311P
Peak Detectors LM211PW
TSSOP (8) 3.00 mm 4.40 mm
LM311PW
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACER
Simplified Schematic
BALANCE
BAL/STRB
IN EMIT OUT
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM111, LM211, LM311
SLCS007K SEPTEMBER 1973 REVISED MARCH 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 11
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 11
3 Description ............................................................. 1 9 Application and Implementation ........................ 12
4 Revision History..................................................... 2 9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 12
5 Pin Configuration and Functions ......................... 3
9.3 System Examples ................................................... 14
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4 10 Power Supply Recommendations ..................... 22
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 22
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 22
6.4 Thermal Information (8-Pin Packages) ..................... 5 11.2 Layout Example .................................................... 22
6.5 Thermal Information (20-Pin Package) ..................... 5 12 Device and Documentation Support ................. 23
6.6 Electrical Characteristics........................................... 6 12.1 Related Links ........................................................ 23
6.7 Switching Characteristics .......................................... 6 12.2 Receiving Notification of Documentation Updates 23
6.8 Typical Characteristics .............................................. 7 12.3 Community Resources.......................................... 23
7 Parameter Measurement Information .................. 9 12.4 Trademarks ........................................................... 23
12.5 Electrostatic Discharge Caution ............................ 23
8 Detailed Description ............................................ 10
12.6 Glossary ................................................................ 23
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10 13 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changed Human body model (HBM) from: 1000 to: 500 in ESD Ratings table ................................................................ 4
Changed the data sheet title From: LMx11 Quad Differential Comparators To: LM111, LM211, LM311 Differential
Comparators .......................................................................................................................................................................... 1
Updated the Applications list ................................................................................................................................................. 1
Updated the Thermal Information (8-Pin Packages) table ..................................................................................................... 5
Changed text From: "over a 25C to +85C temperature range..." To: ""over a 40C to +85C temperature
range..." in the Overview section.......................................................................................................................................... 10
Added text "The LM311 has a temperature range of 40C to +125C." to the Overview section...................................... 10
EMIT OUT
EMIT OUT 1 8 VCC+
VCC+
IN+ 2 7 COL OUT
NC
NC
NC
IN 3 6 BAL/STRB
VCC 4 5 BALANCE
3 2 1 20 19
NC 4 18 NC
IN+ 5 17 COL OUT
NC 6 16 NC
IN 7 15 BAL/STRB
NC 8 14 NC
9 10 11 12 13
VCC
NC
NC
BALANCE
NC
(1) NC = No internal connection
Pin Functions
PIN
LM211,
LM311 LM111 LM111
LM311 I/O (1) DESCRIPTION
NAME
SOIC, PDIP,
SO CDIP LCCC
TSSOP
IN+ 2 2 2 5 I Noninverting comparator
IN 3 3 3 7 I Inverting input comparator
BALANCE 5 5 5 12 I Balance
BAL/STRB 6 6 6 15 I Strobe
COL OUT 7 7 7 17 O Output collector comparator
EMIT OUT 1 1 1 2 O Output emitter comparator
VCC 4 4 4 10 Negative supply
VCC+ 8 8 8 20 Positive supply
1
3
4
6
8
9
NC No connect (No internal connection)
11
13
14
16
18
19
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC+ (2) 18
Supply voltage VCC (2) 18 V
VCC+ VCC 36
VID Differential input voltage (3) 30 V
(2) (4)
VI Input voltage (either input) 15 V
Voltage from emitter output to VCC 30 V
LM111 50
LM211 50
Voltage from collector output to VCC V
LM211Q 50
LM311 40
Duration of output short circuit to ground 10 s
TJ Operating virtual-junction temperature 150 C
Case temperature for 60 s FK package 260 C
Lead temperature 1,6 mm (1/16 inch) from case, 10 s JG package 300 C
D, P, PS, or PW
Lead temperature 1,6 mm (1/16 inch) from case, 60 s 260 C
package
Tstg Storage temperature 65 150 C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, unless otherwise noted, are with respect to the midpoint between VCC+ and VCC.
(3) Differential voltages are at IN+ with respect to IN.
(4) The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Large-signal
AVD differential-voltage 5 V VO 35 V, RL = 1 k 25C 40 200 40 200 V/mV
amplification
High-level I(strobe) = 3 mA, 25C 0.2 10 nA
(collector) VOH = 35 V
IOH VID = 5 mV Full range 0.5 A
output leakage
current VID = 5 mV, VOH = 35 V 25C 0.2 50 nA
VID = 5 mV 25C 0.75 1.5
Low-level IOL = 50 mA
VID = 10 mV 25C 0.75 1.5
(collector-to-
VOL V
emitter) VCC+ = 4.5 V, VID = 6 mV Full range 0.23 0.4
output voltage VCC = 0 V,
IOL = 8 mA VID = 10 mV Full range 0.23 0.4
(1) Unless otherwise noted, all characteristics are measured with BALANCE and BAL/STRB open and EMIT OUT grounded. Full range for
LM111 is 55C to 125C, for LM211 is 40C to 85C, for LM211Q is 40C to 125C, and for LM311 is 0C to 70C.
(2) All typical values are at TA = 25C.
(3) The offset voltages and offset currents given are the maximum values required to drive the collector output up to 14 V or down to 1 V
with a pullup resistor of 7.5 k to VCC+. These parameters actually define an error band and take into account the worst-case effects of
voltage gain and input impedance.
(4) The strobe must not be shorted to ground; it must be current driven at 3 mA to 5 mA (see Figure 18 and Figure 31).
(1) The response time specified is for a 100-mV input step with 5-mV overdrive and is the interval between the input step function and the
instant when the output crosses 1.4 V.
(2) The package thermal impedance is calculated in accordance with MIL-STD-883.
Condition 1 is with BALANCE and BAL/STRB open. Condition 1 is with BALANCE and BAL/STRB open.
Condition 2 is with BALANCE and BAL/STRB connected to VCC+. Condition 2 is with BALANCE and BAL/STRB connected to VCC+.
Figure 1. Input Offset Current vs Free-Air Temperature Figure 2. Input Bias Current vs Free-Air Temperature
Figure 3. Output Response for Various Input Overdrives Figure 4. Output Response for Various Input Overdrives
Figure 5. Output Current and Dissipation vs Output Voltage Figure 6. Positive Supply Current vs Positive Supply
Voltage
LM311
VO Output Voltage V
40
20
10
0
1 0.5 0 0.5 1
VID Differential Input Voltage mV
Figure 7. Negative Supply Current vs Negative Supply Figure 8. Voltage Transfer Characteristics and Test Circuits
Voltage
1 k
Output VID
VID Output
600
VCC
VCC
Figure 9. Collector Output Transfer Characteristic Figure 10. Emitter Output Transfer Characteristic
Test Circuit Test Circuit
VCC+ = 15 V 5V VCC+ = 15 V
500
VID VO
VID
VO
VCC = 15 V
Copyright 2016, Texas Instruments Incorporated RE = 2 k
VCC = 15 V
Copyright 2016, Texas Instruments Incorporated
Figure 11. Test Circuit for Figure 3 and Figure 4 Figure 12. Test Circuit for Figure 14 and Figure 15
8 Detailed Description
8.1 Overview
The LM111, LM211 and LM311 are voltage comparators that have input currents nearly a thousand times lower
than legacy standard devices. They are also designed to operate over a wider range of supply voltages: from
standard 15V op amp supplies down to the single 5-V supply used for IC logic. Their output is compatible with
RTL, DTL and TTL as well as MOS circuits. Further, they can drive lamps or relays, switching voltages up to 50
V at currents as high as 50 mA.
Both the inputs and the outputs of the LM111, LM211 or the LM311 can be isolated from system ground, and the
output can drive loads referred to ground, the positive supply or the negative supply. Offset balancing and strobe
capability are provided and outputs can be wire ORed. The LM211 is identical to the LM111, except that its
performance is specified over a 40C to +85C temperature range instead of 55C to +125C. The LM311 has
a temperature range of 0C to +70C. The LM211Q has a temperature range of 40C to +125C.
Component Count
BAL/STRB BALANCE Resistors 20
Diodes 2
EPI FET 1
450 450 Transistors 22
VCC+
750 600
2.4 2.4
k k 70
1.2 k
IN+ 1.2 k
4 k
COL OUT
IN
400
130
60
600
450
250 200
2 k 4
EMIT OUT
VCC
Copyright 2016, Texas Instruments Incorporated
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Validate and test
the design implementation to confirm system functionality.
20 k
Input Output
VCC
Copyright 2016, Texas Instruments Incorporated
Figure 14. Output Response for Various Input Overdrives Figure 15. Output Response for Various Input Overdrives
20 k 39 k
VCC+
3 k
3 k
BAL/
BALANCE STRB
If offset balancing is not used, the BALANCE and BAL/STRB pins must be unconnected. It is also acceptable to short
pins together.
BAL/STRB
TTL
Strobe 2N2222
1 k
Do not connect strobe pin directly to ground, because the output is turned off whenever current is pulled from the
strobe pin.
5V
82 k 1 k
240 k
Input Output to TTL
47 k
82 k
Resistor values shown are for a 0- to 30-V logic swing and a 15-V threshold.
May be added to control speed and reduce susceptibility to noise spikes
Copyright 2016, Texas Instruments Incorporated
5V VCC+
100 k 2 k
100 kHz 10 pF
4.5 k 2 k
Output
to TTL Output
1 k
100 k 0.1 F
50 k
Magnetic
Transducer
Copyright 2016, Texas Instruments Incorporated
Figure 20. Detector for Magnetic Transducer Figure 21. 100-kHz Crystal Oscillator
22 k
Analog
Input
BALANCE BAL/STRB
Input
0.1 F
2N2222 TTL
Sample Strobe
1 k
Figure 22. Comparator and Solenoid Driver Figure 23. Strobing Both Input and Output Stages
Simultaneously
VCC+ VCC+ = 5 V
3.9 k 500 3 k
10 k 3 k
Output
2N3708
BAL/
BALANCE STRB
Output
Input to MOS
+
1 k 1.5 F 10 k
2N2222
VCC = 10 V
Copyright 2016, Texas Instruments Incorporated Copyright 2016, Texas Instruments Incorporated
Figure 24. Low-Voltage Adjustable Reference Figure 25. Zero-Crossing Detector Driving MOS
Supply Logic
VCC+ = 5 V
3.9 k
30 k 1 k 1 k
2N3708 1N914
Output
1N914 Input
2N2222
+ From
2N2222 1.5 F TTL
2.7 k
2N2222 510 2.2 k
VCC+ = 5 V
5V
Opto Isolator 5 k
1 k
TTL
100 Output
From
1 k
TTL
Gate
50 k 0.01 F
1 k
VCC+ = 15 V
2 k
Input
TL081
10 k Output
+
+
1.5 F
1 M
VCC = 15 V
Copyright 2016, Texas Instruments Incorporated
VCC+ = 15 V
1 M
TL081
10 k
2 k +
Input Output
+
15 F
VCC = 15 V
Copyright 2016, Texas Instruments Incorporated
VCC+ = 5 V
3.9 k
1N2175 1 k
2N3708
Output
to TTL
2N2222
R1
30 k
R1 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing dark current by an order of magnitude.
Copyright 2016, Texas Instruments Incorporated
VCC+
Inputs
BAL/STRB
TTL VCC
Strobe
2N3708
1 k
VCC+
620
BAL/STRB 300
100 k Output
100 k
BAL/STRB
2
10 k
Input
VCC
VCC+
39 k
620
300 k
BAL/STRB 620
15 k
Reference VCC
0.22 F 620
Outputs
V+
510
15 k 510 620
BAL/STRB
Input
VCC 620
39 k
300 k
620
11 Layout
Bypass
Capacitor
0.1F
EMIT OUT 1 8 VCC+ Positive Supply
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 17-Mar-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
JM38510/10304BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10304BPA
LM111FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 LM111FKB
LM111JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 LM111JG
LM111JGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 LM111JGB
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM211QDG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM211Q
& no Sb/Br)
LM211QDR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM211Q
& no Sb/Br)
LM211QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 LM211Q
& no Sb/Br)
LM311-MWC ACTIVE WAFERSALE YS 0 1 Green (RoHS Call TI Level-1-NA-UNLIM -40 to 85
& no Sb/Br)
LM311D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM311
& no Sb/Br)
LM311DE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM311
& no Sb/Br)
LM311DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM311
& no Sb/Br)
LM311DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 LM311
& no Sb/Br)
LM311DRE4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM311
& no Sb/Br)
LM311DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LM311
& no Sb/Br)
LM311P ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 LM311P
(RoHS)
LM311PE4 ACTIVE PDIP P 8 50 Pb-Free CU NIPDAU N / A for Pkg Type 0 to 70 LM311P
(RoHS)
LM311PSR ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 L311
& no Sb/Br)
LM311PSRE4 ACTIVE SO PS 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 L311
& no Sb/Br)
LM311PW ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 L311
& no Sb/Br)
LM311PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 L311
& no Sb/Br)
LM311PWR ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 L311
& no Sb/Br)
LM311PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 L311
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
M38510/10304BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510
/10304BPA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com 17-Mar-2017
Automotive: LM211-Q1
Enhanced Product: LM211-EP
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jan-2017
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Jan-2017
Pack Materials-Page 2
MECHANICAL DATA
0.400 (10,16)
0.355 (9,00)
8 5
0.280 (7,11)
0.245 (6,22)
1 4
0.065 (1,65)
0.045 (1,14)
0.023 (0,58)
015
0.015 (0,38)
0.100 (2,54) 0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
C
6.6 SEATING PLANE
TYP
6.2
A PIN 1 ID 0.1 C
AREA
6X 0.65
8
1
3.1 2X
2.9
NOTE 3 1.95
4
5
0.30
8X
0.19
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.75 0.15
0 -8 0.05
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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EXAMPLE BOARD LAYOUT
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45) SYMM
(R0.05)
1 TYP
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
PW0008A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM (R0.05) TYP
8X (0.45)
1
8
SYMM
6X (0.65)
5
4
(5.8)
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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